signal link_tx_ready_i : std_logic;
signal status_raw : std_logic_vector(4 * 32 - 1 downto 0);
- -- for SCRL endpoint (old style)
- signal mac_ready_conf : std_logic;
- signal mac_reconf : std_logic;
- signal mac_an_ready : std_logic;
- signal mac_fifoavail : std_logic;
- signal mac_fifoeof : std_logic;
- signal mac_fifoempty : std_logic;
- signal mac_rx_fifofull : std_logic;
- signal mac_tx_data : std_logic_vector(7 downto 0);
- signal mac_tx_read : std_logic;
- signal mac_tx_discrfrm : std_logic;
- signal mac_tx_stat_en : std_logic;
- signal mac_tx_stats : std_logic_vector(30 downto 0);
- signal mac_tx_done : std_logic;
- signal mac_rx_fifo_err : std_logic;
- signal mac_rx_stats : std_logic_vector(31 downto 0);
- signal mac_rx_data : std_logic_vector(7 downto 0);
- signal mac_rx_write : std_logic;
- signal mac_rx_stat_en : std_logic;
- signal mac_rx_eof : std_logic;
- signal mac_rx_err : std_logic;
-- the new FIFO interface
-- 9 : fifo_wr
-- 8 : fifo_eof
-- 7..0: fifo_data
- type dl_rx_data_t is array(0 to 3) of std_logic_vector(10 downto 0);
+ type dl_rx_data_t is array(0 to 10) of std_logic_vector(10 downto 0);
signal dl_rx_data : dl_rx_data_t;
- signal dl_rx_frame_req : std_logic_vector(3 downto 0);
- signal dl_rx_frame_ack : std_logic_vector(3 downto 0);
- signal dl_rx_frame_avail : std_logic_vector(3 downto 0);
- signal dl_tx_fifofull : std_logic_vector(3 downto 0);
+ signal dl_rx_frame_req : std_logic_vector(10 downto 0);
+ signal dl_rx_frame_ack : std_logic_vector(10 downto 0);
+ signal dl_rx_frame_avail : std_logic_vector(10 downto 0);
+ signal dl_tx_fifofull : std_logic_vector(10 downto 0);
-- 10: frame_start
-- 9 : fifo_wr
signal ul_rx_frame_ack : std_logic;
signal ul_rx_fifofull : std_logic;
- signal port_sel : std_logic_vector(3 downto 0);
+ signal port_sel : std_logic_vector(10 downto 0);
signal pcs_an_ready : std_logic;
signal link_active : std_logic;
CLEAR => clear_i,
CLEAR_N => clear_n_i,
CLK_125 => clk_sys,
- -- SerDes 0 -- UPLINK
- -- FIFO interface RX
- FIFO_FULL_IN(0) => ul_rx_fifofull,
- FIFO_WR_OUT(0) => ul_rx_data(9),
- FIFO_DATA_OUT(8 downto 0) => ul_rx_data(8 downto 0),
- FRAME_START_OUT(0) => ul_rx_data(10),
- FRAME_REQ_IN(0) => ul_rx_frame_req,
- FRAME_ACK_OUT(0) => ul_rx_frame_ack,
- FRAME_AVAIL_OUT(0) => ul_rx_frame_avail,
+ -- SerDes 0 -- DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(0) => ul_tx_fifofull,
+ FIFO_WR_OUT(0) => dl_rx_data(6)(9),
+ FIFO_DATA_OUT(8 downto 0) => dl_rx_data(6)(8 downto 0),
+ FRAME_START_OUT(0) => dl_rx_data(6)(10),
+ FRAME_REQ_IN(0) => dl_rx_frame_req(6),
+ FRAME_ACK_OUT(0) => dl_rx_frame_ack(6),
+ FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(6),
-- FIFO interface TX
- FIFO_WR_IN(0) => ul_tx_data_q(9),
- FIFO_DATA_IN(8 downto 0) => ul_tx_data_q(8 downto 0),
- FRAME_START_IN(0) => ul_tx_data_q(10),
- FIFO_FULL_OUT(0) => ul_tx_fifofull,
+ FIFO_WR_IN(0) => ul_rx_data(9),
+ FIFO_DATA_IN(8 downto 0) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(0) => ul_rx_data(10),
+ FIFO_FULL_OUT(0) => dl_tx_fifofull(6),
-- SerDes 1 - DOWNLINK
-- FIFO interface RX
FIFO_FULL_IN(1) => ul_tx_fifofull,
- FIFO_WR_OUT(1) => dl_rx_data(1)(9),
- FIFO_DATA_OUT(17 downto 9) => dl_rx_data(1)(8 downto 0),
- FRAME_START_OUT(1) => dl_rx_data(1)(10),
- FRAME_REQ_IN(1) => dl_rx_frame_req(1),
- FRAME_ACK_OUT(1) => dl_rx_frame_ack(1),
- FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(1),
+ FIFO_WR_OUT(1) => dl_rx_data(7)(9),
+ FIFO_DATA_OUT(17 downto 9) => dl_rx_data(7)(8 downto 0),
+ FRAME_START_OUT(1) => dl_rx_data(7)(10),
+ FRAME_REQ_IN(1) => dl_rx_frame_req(7),
+ FRAME_ACK_OUT(1) => dl_rx_frame_ack(7),
+ FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(7),
-- FIFO interface TX
FIFO_WR_IN(1) => ul_rx_data(9),
FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0),
FRAME_START_IN(1) => ul_rx_data(10),
- FIFO_FULL_OUT(1) => dl_tx_fifofull(1),
+ FIFO_FULL_OUT(1) => dl_tx_fifofull(7),
-- SerDes 2 -- DOWNLINK
-- FIFO interface RX
FIFO_FULL_IN(2) => ul_tx_fifofull,
- FIFO_WR_OUT(2) => dl_rx_data(2)(9),
- FIFO_DATA_OUT(26 downto 18) => dl_rx_data(2)(8 downto 0),
- FRAME_START_OUT(2) => dl_rx_data(2)(10),
- FRAME_REQ_IN(2) => dl_rx_frame_req(2),
- FRAME_ACK_OUT(2) => dl_rx_frame_ack(2),
- FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(2),
+ FIFO_WR_OUT(2) => dl_rx_data(4)(9),
+ FIFO_DATA_OUT(26 downto 18) => dl_rx_data(4)(8 downto 0),
+ FRAME_START_OUT(2) => dl_rx_data(4)(10),
+ FRAME_REQ_IN(2) => dl_rx_frame_req(4),
+ FRAME_ACK_OUT(2) => dl_rx_frame_ack(4),
+ FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(4),
-- FIFO interface TX
FIFO_WR_IN(2) => ul_rx_data(9),
FIFO_DATA_IN(26 downto 18) => ul_rx_data(8 downto 0),
FRAME_START_IN(2) => ul_rx_data(10),
- FIFO_FULL_OUT(2) => dl_tx_fifofull(2),
+ FIFO_FULL_OUT(2) => dl_tx_fifofull(4),
-- SerDes 3 -- DOWNLINK
-- FIFO interface RX
FIFO_FULL_IN(3) => ul_tx_fifofull,
- FIFO_WR_OUT(3) => dl_rx_data(3)(9),
- FIFO_DATA_OUT(35 downto 27) => dl_rx_data(3)(8 downto 0),
- FRAME_START_OUT(3) => dl_rx_data(3)(10),
- FRAME_REQ_IN(3) => dl_rx_frame_req(3),
- FRAME_ACK_OUT(3) => dl_rx_frame_ack(3),
- FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(3),
+ FIFO_WR_OUT(3) => dl_rx_data(5)(9),
+ FIFO_DATA_OUT(35 downto 27) => dl_rx_data(5)(8 downto 0),
+ FRAME_START_OUT(3) => dl_rx_data(5)(10),
+ FRAME_REQ_IN(3) => dl_rx_frame_req(5),
+ FRAME_ACK_OUT(3) => dl_rx_frame_ack(5),
+ FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(5),
-- FIFO interface TX
FIFO_WR_IN(3) => ul_rx_data(9),
FIFO_DATA_IN(35 downto 27) => ul_rx_data(8 downto 0),
FRAME_START_IN(3) => ul_rx_data(10),
- FIFO_FULL_OUT(3) => dl_tx_fifofull(3),
+ FIFO_FULL_OUT(3) => dl_tx_fifofull(5),
-- SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(3),
SD_PRSNT_N_IN(1) => HUB_MOD0(4),
CLK => clk_sys,
RESET => reset_i,
--
- FRAME_AVAIL_IN(3 downto 0) => dl_rx_frame_avail,
- FRAME_REQ_OUT(3 downto 0) => dl_rx_frame_req,
- FRAME_ACK_IN(3 downto 0) => dl_rx_frame_ack,
- PORT_SELECT_OUT(3 downto 0) => port_sel,
+ FRAME_AVAIL_IN(10 downto 0) => dl_rx_frame_avail,
+ FRAME_REQ_OUT(10 downto 0) => dl_rx_frame_req,
+ FRAME_ACK_IN(10 downto 0) => dl_rx_frame_ack,
+ PORT_SELECT_OUT(10 downto 0) => port_sel,
CYCLE_DONE_OUT => open,
--
DEBUG => open
THE_QUICK_MUX: process( port_sel, dl_rx_data )
begin
case port_sel is
- when b"0001" => ul_tx_data <= dl_rx_data(0);
- when b"0010" => ul_tx_data <= dl_rx_data(1);
- when b"0100" => ul_tx_data <= dl_rx_data(2);
- when b"1000" => ul_tx_data <= dl_rx_data(3);
+ when b"00000000001" => ul_tx_data <= dl_rx_data(0);
+ when b"00000000010" => ul_tx_data <= dl_rx_data(1);
+ when b"00000000100" => ul_tx_data <= dl_rx_data(2);
+ when b"00000001000" => ul_tx_data <= dl_rx_data(3);
+ when b"00000010000" => ul_tx_data <= dl_rx_data(4);
+ when b"00000100000" => ul_tx_data <= dl_rx_data(5);
+ when b"00001000000" => ul_tx_data <= dl_rx_data(6);
+ when b"00010000000" => ul_tx_data <= dl_rx_data(7);
+ when b"00100000000" => ul_tx_data <= dl_rx_data(8);
+ when b"01000000000" => ul_tx_data <= dl_rx_data(9);
+ when b"10000000000" => ul_tx_data <= dl_rx_data(10);
when others => ul_tx_data <= (others => '0');
end case;
end process THE_QUICK_MUX;
-- 8 : fifo_eof
-- 7..0: data
- DBG(3 downto 0) <= port_sel;
+ DBG(3 downto 0) <= port_sel(3 downto 0);
DBG(11 downto 4) <= ul_rx_data(7 downto 0);
DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0);
DBG(20) <= ul_rx_frame_avail;
DBG(29) <= ul_rx_data(9);
DBG(30) <= debug(1); --ul_rx_data(10);
DBG(31) <= ul_rx_fifofull;
- DBG(32) <= debug(4); --dl_rx_data(0)(8);
+ DBG(32) <= debug(2); --dl_rx_data(0)(8);
DBG(33) <= clk_sys;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon)
---------------------------------------------------------------------------
- THE_GBE_MED_RAW_PCSB: entity gbe_med_raw
+ THE_GBE_MED_RAW_PCSB: entity gbe_med_fifo
generic map(
- LINKS_ACTIVE => "1111"
+ LINKS_ACTIVE => "1111"
)
port map(
- RESET => reset_i,
- GSR_N => reset_n_i,
- CLK_125 => clk_sys,
- -- MAC status and config
- MAC_READY_CONF_OUT => open,
- MAC_RECONF_IN => (others => '0'),
- MAC_AN_READY_OUT => open,
- -- MAC data interface
- MAC_FIFOAVAIL_IN => (others => '0'),
- MAC_FIFOEOF_IN => (others => '0'),
- MAC_FIFOEMPTY_IN => (others => '0'),
- MAC_RX_FIFOFULL_IN => (others => '0'),
- -- MAC TX interface
- MAC_TX_DATA_IN => (others => '0'),
- MAC_TX_READ_OUT => open,
- MAC_TX_DISCRFRM_OUT => open,
- MAC_TX_STAT_EN_OUT => open,
- MAC_TX_STATS_OUT => open,
- MAC_TX_DONE_OUT => open,
- -- MAC RX interface
- MAC_RX_FIFO_ERR_OUT => open,
- MAC_RX_STATS_OUT => open,
- MAC_RX_DATA_OUT => open,
- MAC_RX_WRITE_OUT => open,
- MAC_RX_STAT_EN_OUT => open,
- MAC_RX_EOF_OUT => open,
- MAC_RX_ERROR_OUT => open,
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- SerDes 0 -- DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(0) => ul_tx_fifofull,
+ FIFO_WR_OUT(0) => dl_rx_data(8)(9),
+ FIFO_DATA_OUT(8 downto 0) => dl_rx_data(8)(8 downto 0),
+ FRAME_START_OUT(0) => dl_rx_data(8)(10),
+ FRAME_REQ_IN(0) => dl_rx_frame_req(8),
+ FRAME_ACK_OUT(0) => dl_rx_frame_ack(8),
+ FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(8),
+ -- FIFO interface TX
+ FIFO_WR_IN(0) => ul_rx_data(9),
+ FIFO_DATA_IN(8 downto 0) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(0) => ul_rx_data(10),
+ FIFO_FULL_OUT(0) => dl_tx_fifofull(8),
+ -- SerDes 1 - DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(1) => ul_tx_fifofull,
+ FIFO_WR_OUT(1) => dl_rx_data(9)(9),
+ FIFO_DATA_OUT(17 downto 9) => dl_rx_data(9)(8 downto 0),
+ FRAME_START_OUT(1) => dl_rx_data(9)(10),
+ FRAME_REQ_IN(1) => dl_rx_frame_req(9),
+ FRAME_ACK_OUT(1) => dl_rx_frame_ack(9),
+ FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(9),
+ -- FIFO interface TX
+ FIFO_WR_IN(1) => ul_rx_data(9),
+ FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(1) => ul_rx_data(10),
+ FIFO_FULL_OUT(1) => dl_tx_fifofull(9),
+ -- SerDes 2 -- DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(2) => ul_tx_fifofull,
+ FIFO_WR_OUT(2) => dl_rx_data(3)(9),
+ FIFO_DATA_OUT(26 downto 18) => dl_rx_data(3)(8 downto 0),
+ FRAME_START_OUT(2) => dl_rx_data(3)(10),
+ FRAME_REQ_IN(2) => dl_rx_frame_req(3),
+ FRAME_ACK_OUT(2) => dl_rx_frame_ack(3),
+ FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(3),
+ -- FIFO interface TX
+ FIFO_WR_IN(2) => ul_rx_data(9),
+ FIFO_DATA_IN(26 downto 18) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(2) => ul_rx_data(10),
+ FIFO_FULL_OUT(2) => dl_tx_fifofull(3),
+ -- SerDes 3 -- DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(3) => ul_tx_fifofull,
+ FIFO_WR_OUT(3) => dl_rx_data(2)(9),
+ FIFO_DATA_OUT(35 downto 27) => dl_rx_data(2)(8 downto 0),
+ FRAME_START_OUT(3) => dl_rx_data(2)(10),
+ FRAME_REQ_IN(3) => dl_rx_frame_req(2),
+ FRAME_ACK_OUT(3) => dl_rx_frame_ack(2),
+ FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(2),
+ -- FIFO interface TX
+ FIFO_WR_IN(3) => ul_rx_data(9),
+ FIFO_DATA_IN(35 downto 27) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(3) => ul_rx_data(10),
+ FIFO_FULL_OUT(3) => dl_tx_fifofull(2),
-- SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
- SD_PRSNT_N_IN(2) => HUB_MOD0(7), --'1',
- SD_PRSNT_N_IN(3) => HUB_MOD0(8), --'1',
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7), --'1',
- SD_LOS_IN(3) => HUB_LOS(8), --'1',
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7), --open,
- SD_TXDIS_OUT(3) => HUB_TXDIS(8), --open,
- -- SerDes control
- TX_PLOL_LOL_OUT => tx_pll_lol_b_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- RX_LINK_READY_OUT => open,
- TX_LINK_READY_IN => open,
- -- Debug
- STATUS_OUT => status_raw(2 * 32 - 1 downto 1 * 32),
- DEBUG_OUT => open
+ SD_PRSNT_N_IN(0) => HUB_MOD0(5),
+ SD_PRSNT_N_IN(1) => HUB_MOD0(6),
+ SD_PRSNT_N_IN(2) => HUB_MOD0(7), --'1',
+ SD_PRSNT_N_IN(3) => HUB_MOD0(8), --'1',
+ SD_LOS_IN(0) => HUB_LOS(5),
+ SD_LOS_IN(1) => HUB_LOS(6),
+ SD_LOS_IN(2) => HUB_LOS(7), --'1',
+ SD_LOS_IN(3) => HUB_LOS(8), --'1',
+ SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(7), --open,
+ SD_TXDIS_OUT(3) => HUB_TXDIS(8), --open,
+ -- SerDes control
+ TX_PLOL_LOL_OUT => tx_pll_lol_b_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ RX_LINK_READY_OUT => open,
+ TX_LINK_READY_IN => link_tx_ready_i,
+ PCS_AN_READY_OUT(0) => open, -- for internal SCTRL
+ LINK_ACTIVE_OUT(0) => open, -- for internal SCTRL
+ -- Debug
+ STATUS_OUT => status_raw(2 * 32 - 1 downto 1 * 32),
+ DEBUG_OUT => open
);
---------------------------------------------------------------------------
--- PCSD is on uplink / one downlink (no backplane) or two downlinks (backplane)
+-- PCSD is one uplink / one downlink
---------------------------------------------------------------------------
- THE_GBE_MED_RAW_PCSD: entity gbe_med_raw
+ THE_GBE_MED_RAW_PCSD: entity gbe_med_fifo
generic map(
- LINKS_ACTIVE => "0011"
+ LINKS_ACTIVE => "0011"
)
port map(
- RESET => reset_i,
- GSR_N => reset_n_i,
- CLK_125 => clk_sys,
- -- MAC status and config
- MAC_READY_CONF_OUT(0) => mac_ready_conf, -- open,
- MAC_RECONF_IN(0) => mac_reconf, -- (others => '0'),
- MAC_AN_READY_OUT(0) => mac_an_ready, -- open,
- -- MAC data interface
- MAC_FIFOAVAIL_IN(0) => mac_fifoavail, -- (others => '0'),
- MAC_FIFOEOF_IN(0) => mac_fifoeof, -- (others => '0'),
- MAC_FIFOEMPTY_IN(0) => mac_fifoempty, -- (others => '0'),
- MAC_RX_FIFOFULL_IN(0) => mac_rx_fifofull, -- (others => '0'),
- -- MAC TX interface
- MAC_TX_DATA_IN(7 downto 0) => mac_tx_data, -- (others => '0'),
- MAC_TX_READ_OUT(0) => mac_tx_read, -- open,
- MAC_TX_DISCRFRM_OUT(0) => mac_tx_discrfrm, -- open,
- MAC_TX_STAT_EN_OUT(0) => mac_tx_stat_en, -- open,
- MAC_TX_STATS_OUT(30 downto 0) => mac_tx_stats, -- open,
- MAC_TX_DONE_OUT(0) => mac_tx_done, -- open,
- -- MAC RX interface
- MAC_RX_FIFO_ERR_OUT(0) => mac_rx_fifo_err, -- open,
- MAC_RX_STATS_OUT(31 downto 0) => mac_rx_stats, -- open,
- MAC_RX_DATA_OUT(7 downto 0) => mac_rx_data, -- open,
- MAC_RX_WRITE_OUT(0) => mac_rx_write, -- open,
- MAC_RX_STAT_EN_OUT(0) => mac_rx_stat_en, -- open,
- MAC_RX_EOF_OUT(0) => mac_rx_eof, -- open,
- MAC_RX_ERROR_OUT(0) => mac_rx_err, -- open,
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- SerDes 0 -- UPLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(0) => ul_rx_fifofull,
+ FIFO_WR_OUT(0) => ul_rx_data(9),
+ FIFO_DATA_OUT(8 downto 0) => ul_rx_data(8 downto 0),
+ FRAME_START_OUT(0) => ul_rx_data(10),
+ FRAME_REQ_IN(0) => ul_rx_frame_req,
+ FRAME_ACK_OUT(0) => ul_rx_frame_ack,
+ FRAME_AVAIL_OUT(0) => ul_rx_frame_avail,
+ -- FIFO interface TX
+ FIFO_WR_IN(0) => ul_tx_data_q(9),
+ FIFO_DATA_IN(8 downto 0) => ul_tx_data_q(8 downto 0),
+ FRAME_START_IN(0) => ul_tx_data_q(10),
+ FIFO_FULL_OUT(0) => ul_tx_fifofull,
+ -- SerDes 1 - DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(1) => ul_tx_fifofull,
+ FIFO_WR_OUT(1) => dl_rx_data(1)(9),
+ FIFO_DATA_OUT(17 downto 9) => dl_rx_data(1)(8 downto 0),
+ FRAME_START_OUT(1) => dl_rx_data(1)(10),
+ FRAME_REQ_IN(1) => dl_rx_frame_req(1),
+ FRAME_ACK_OUT(1) => dl_rx_frame_ack(1),
+ FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(1),
+ -- FIFO interface TX
+ FIFO_WR_IN(1) => ul_rx_data(9),
+ FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(1) => ul_rx_data(10),
+ FIFO_FULL_OUT(1) => dl_tx_fifofull(1),
+ -- SerDes 2 -- UNUSED
+ -- SerDes 3 -- UNUSED
-- SFP Connection
- SD_PRSNT_N_IN(0) => SFP_MOD0(0),
- SD_PRSNT_N_IN(1) => SFP_MOD0(1),
- SD_PRSNT_N_IN(2) => '1',
- SD_PRSNT_N_IN(3) => '1',
- SD_LOS_IN(0) => SFP_LOS(0),
- SD_LOS_IN(1) => SFP_LOS(1),
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => '1',
- SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
- SD_TXDIS_OUT(1) => SFP_TX_DIS(1),
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => open,
- -- SerDes control
- TX_PLOL_LOL_OUT => tx_pll_lol_d_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- RX_LINK_READY_OUT => open,
- TX_LINK_READY_IN => open,
- -- Debug
- STATUS_OUT => status_raw(4 * 32 - 1 downto 3 * 32),
- DEBUG_OUT => open
+ SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+ SD_PRSNT_N_IN(1) => SFP_MOD0(1),
+ SD_LOS_IN(0) => SFP_LOS(0),
+ SD_LOS_IN(1) => SFP_LOS(1),
+ SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+ SD_TXDIS_OUT(1) => SFP_TX_DIS(1),
+ -- SerDes control
+ TX_PLOL_LOL_OUT => tx_pll_lol_d_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ RX_LINK_READY_OUT => open,
+ TX_LINK_READY_IN => link_tx_ready_i,
+ PCS_AN_READY_OUT(0) => open, -- for internal SCTRL
+ LINK_ACTIVE_OUT(0) => open, -- for internal SCTRL
+ -- Debug
+ STATUS_OUT => status_raw(4 * 32 - 1 downto 3 * 32),
+ DEBUG_OUT => open
);
---------------------------------------------------------------------------
--- PCSA is one port uplink (backplane)
+-- PCSA is one port downlink (backplane)
---------------------------------------------------------------------------
- THE_GBE_MED_RAW_PCSA: entity gbe_med_raw
+ THE_GBE_MED_RAW_PCSA: entity gbe_med_fifo
generic map(
- LINKS_ACTIVE => "0001"
+ LINKS_ACTIVE => "0001"
)
port map(
- RESET => reset_i,
- GSR_N => reset_n_i,
- CLK_125 => clk_sys,
- -- MAC status and config
- MAC_READY_CONF_OUT => open,
- MAC_RECONF_IN => (others => '0'),
- MAC_AN_READY_OUT => open,
- -- MAC data interface
- MAC_FIFOAVAIL_IN => (others => '0'),
- MAC_FIFOEOF_IN => (others => '0'),
- MAC_FIFOEMPTY_IN => (others => '0'),
- MAC_RX_FIFOFULL_IN => (others => '0'),
- -- MAC TX interface
- MAC_TX_DATA_IN => (others => '0'),
- MAC_TX_READ_OUT => open,
- MAC_TX_DISCRFRM_OUT => open,
- MAC_TX_STAT_EN_OUT => open,
- MAC_TX_STATS_OUT => open,
- MAC_TX_DONE_OUT => open,
- -- MAC RX interface
- MAC_RX_FIFO_ERR_OUT => open,
- MAC_RX_STATS_OUT => open,
- MAC_RX_DATA_OUT => open,
- MAC_RX_WRITE_OUT => open,
- MAC_RX_STAT_EN_OUT => open,
- MAC_RX_EOF_OUT => open,
- MAC_RX_ERROR_OUT => open,
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- SerDes 0 -- DOWNLINK
+ -- FIFO interface RX
+ FIFO_FULL_IN(0) => ul_tx_fifofull,
+ FIFO_WR_OUT(0) => dl_rx_data(10)(9),
+ FIFO_DATA_OUT(8 downto 0) => dl_rx_data(10)(8 downto 0),
+ FRAME_START_OUT(0) => dl_rx_data(10)(10),
+ FRAME_REQ_IN(0) => dl_rx_frame_req(10),
+ FRAME_ACK_OUT(0) => dl_rx_frame_ack(10),
+ FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(10),
+ -- FIFO interface TX
+ FIFO_WR_IN(0) => ul_rx_data(9),
+ FIFO_DATA_IN(8 downto 0) => ul_rx_data(8 downto 0),
+ FRAME_START_IN(0) => ul_rx_data(10),
+ FIFO_FULL_OUT(0) => dl_tx_fifofull(10),
+ -- SerDes 1 -- UNUSED
+ -- SerDes 2 -- UNUSED
+ -- SerDes 3 -- UNUSED
-- SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
- SD_PRSNT_N_IN(1) => '1',
- SD_PRSNT_N_IN(2) => '1',
- SD_PRSNT_N_IN(3) => '1',
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => '1',
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => '1',
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => open,
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => open,
- -- SerDes control
- TX_PLOL_LOL_OUT => tx_pll_lol_a_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- RX_LINK_READY_OUT => open,
- TX_LINK_READY_IN => open,
- -- Debug
- STATUS_OUT => status_raw(1 * 32 - 1 downto 0 * 32),
- DEBUG_OUT => open
+ SD_PRSNT_N_IN(0) => HUB_MOD0(5),
+ SD_PRSNT_N_IN(1) => '1',
+ SD_PRSNT_N_IN(2) => '1',
+ SD_PRSNT_N_IN(3) => '1',
+ SD_LOS_IN(0) => HUB_LOS(5),
+ SD_LOS_IN(1) => '1',
+ SD_LOS_IN(2) => '1',
+ SD_LOS_IN(3) => '1',
+ SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+ SD_TXDIS_OUT(1) => open,
+ SD_TXDIS_OUT(2) => open,
+ SD_TXDIS_OUT(3) => open,
+ -- SerDes control
+ TX_PLOL_LOL_OUT => tx_pll_lol_a_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ RX_LINK_READY_OUT => open,
+ TX_LINK_READY_IN => link_tx_ready_i,
+ PCS_AN_READY_OUT(0) => open, -- for internal SCTRL
+ LINK_ACTIVE_OUT(0) => open, -- for internal SCTRL
+ -- Debug
+ STATUS_OUT => status_raw(1 * 32 - 1 downto 0 * 32),
+ DEBUG_OUT => open
);
---------------------------------------------------------------------------
jspc29 / trb3sc.git / commitdiff