library ieee;
use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
library xpm;
use xpm.vcomponents.all;
signal rx_cdr_lol : std_logic;
signal tx_lol : std_logic;
- signal rxpmaresetdone_i : std_logic;
+ signal rxresetdone : std_logic;
signal txpmaresetdone_i : std_logic;
+ signal rx_data_valid_count : unsigned(7 downto 0) := (others => '0');
+
signal debug_rx_control_i : std_logic_vector(31 downto 0);
signal debug_tx_control_i : std_logic_vector(31 downto 0);
TXPMARESET => '0',
TXPCSRESET => '0',
INIT_DONE => open,
- RXRESETDONE => open,
+ RXRESETDONE => rxresetdone,
TXRESETDONE => open,
- RXPMARESETDONE => rxpmaresetdone_i,
+ RXPMARESETDONE => RXPMARESETDONE,
TXPMARESETDONE => txpmaresetdone_i,
RXBYTEISALIGNED => open,
RXN => RXN,
);
tx_lol <= not txpmaresetdone_i;
- rx_cdr_lol <= not rxpmaresetdone_i;
- RXPMARESETDONE <= rxpmaresetdone_i;
+ process (RXUSRCLK_DOUBLE) is
+ begin
+ if rising_edge(RXUSRCLK_DOUBLE) then
+ if rxresetdone = '0' then
+ rx_cdr_lol <= '1';
+ else
+ if rxnotintable = '1' then
+ rx_data_valid_count <= (others => '0');
+ rx_cdr_lol <= '1';
+ else
+ rx_data_valid_count <= rx_data_valid_count + 1;
+ if rx_data_valid_count(rx_data_valid_count'left) = '1' then
+ rx_cdr_lol <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
TXPMARESETDONE <= txpmaresetdone_i;
THE_MED_CONTROL : entity work.med_sync_control