-- Clocks and reset
CLK_REF_FULL : in std_logic; -- TRBnet reference clock
SYSCLK : in std_logic; -- FPGA fabric clock
+ SAMPLE_CLK : in std_logic; -- DLM measurement clock
RESET : in std_logic; -- synchronous reset
-- Media Interface TX/RX
MEDIA_MED2INT : out med2int_array_t(0 to 3);
DESTROY_LINK_IN : in std_logic_vector(3 downto 0); -- hard reset for links
WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST
RX_INDEX_OUT : out std_logic_vector(3 downto 0); -- TESTTESTTEST
+ DLM_RESULT_OUT : out std_logic_vector(4*32-1 downto 0); -- TESTTESTTEST
--SFP Connection
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0);
signal rx_rst_i : std_logic_vector(3 downto 0);
+ signal rx_dlm_i : std_logic_vector(3 downto 0);
signal global_reset_i : std_logic_vector(3 downto 0);
signal wap_requested_i : std_logic_vector(15 downto 0);
signal rx_index_i : std_logic_vector(3 downto 0);
+ signal dlm_result_i : std_logic_vector(4*32-1 downto 0);
+
signal quad_mode : integer range 0 to 100;
TX_DLM_WORD_IN => TX_DLM_WORD_IN,
TX_RST_IN => tx_rst_i(i),
TX_RST_WORD_IN => TX_RST_WORD_IN,
- RX_DLM_OUT => RX_DLM_OUT(i),
+ RX_DLM_OUT => rx_dlm_i(i),
RX_DLM_WORD_OUT => RX_DLM_WORD_OUT(i*8+7 downto i*8),
RX_RST_OUT => rx_rst_i(i),
RX_RST_WORD_OUT => rx_rst_word_i(i*8+7 downto i*8),
MEDIA_MED2INT(i).stat_op <= x"0007";
end generate;
+ gen_phaser : if (IS_MODE(i) = c_IS_MASTER) generate
+ THE_PHASER : entity work.phaser
+ port map(
+ SAMPLE_CLK => SAMPLE_CLK,
+ RESET => RESET,
+ START_IN => TX_DLM_IN, -- TX DLM
+ STOP_IN => rx_dlm_i(i), -- RX DLM
+ PING_IN => word_sync_sel, -- TX K
+ CLK_PING => MASTER_CLK_IN, -- TX CLK
+ PONG_IN => rx_index_i(i), -- RX K
+ CLK_PONG => clk_rx_full(i), -- RX CLK
+ RESULT_OUT => dlm_result_i(i*32+31 downto i*32),
+ UPDATE_OUT => open
+ );
+
+ --- BUG BUG BUG word_sync_sel works not always
+ end generate;
+
end generate;
+ RX_DLM_OUT <= rx_dlm_i;
+ DLM_RESULT_OUT <= dlm_result_i;
+
THE_SCI_READER : entity work.sci_reader_RS
port map(
CLK => SYSCLK,
\r
entity phaser is\r
port( \r
- SAMPLE_CLK : in std_logic;\r
+ SAMPLE_CLK : in std_logic; -- clock for sampling XOR\r
RESET : in std_logic;\r
- SIGNAL_A_IN : in std_logic;\r
- SIGNAL_B_IN : in std_logic;\r
- LOW_CNT_OUT : out std_logic_vector(15 downto 0);\r
- HI_CNT_OUT : out std_logic_vector(15 downto 0);\r
+ START_IN : in std_logic; -- TX DLM\r
+ STOP_IN : in std_logic; -- RX DLM\r
+ PING_IN : in std_logic; -- TX K\r
+ CLK_PING : in std_logic; -- TX CLK\r
+ PONG_IN : in std_logic; -- RX K\r
+ CLK_PONG : in std_logic; -- RX CLK\r
+ RESULT_OUT : out std_logic_vector(31 downto 0);\r
UPDATE_OUT : out std_logic\r
);\r
end entity phaser;\r
-- state machine signals\r
\r
-- Signals\r
- signal low_cnt : unsigned(15 downto 0);\r
- signal hi_cnt : unsigned(15 downto 0);\r
- signal cyc_cnt : unsigned(15 downto 0);\r
- signal update : std_logic;\r
- signal cycle_done_x : std_logic;\r
- signal cycle_done : std_logic;\r
- signal phase_x : std_logic;\r
- signal phase : std_logic;\r
-\r
- signal low_cnt_int : std_logic_vector(15 downto 0);\r
- signal hi_cnt_int : std_logic_vector(15 downto 0);\r
-\r
---attribute HGROUP: string;\r
---attribute BBOX: string;\r
---attribute HGROUP of behavioural: architecture is "phaser";\r
---attribute BBOX of behavioural: architecture is "5,5";\r
+ signal hi_cnt : unsigned(20 downto 0);\r
+ signal cyc_cnt : unsigned(20 downto 0);\r
+ signal update : std_logic;\r
+ signal cyc_done_x : std_logic;\r
+ signal cyc_done : std_logic;\r
+ signal phase_x : std_logic;\r
+ signal phase : std_logic;\r
+ signal hi_cnt_int : std_logic_vector(20 downto 0);\r
+\r
+ signal coarse_counter : unsigned(11 downto 0);\r
+ signal coarse_delay : std_logic_vector(11 downto 0);\r
\r
begin\r
\r
---------------------------------------------------------------------------\r
--- Sync process\r
+-- coarse delay measurement, based on TX clock\r
---------------------------------------------------------------------------\r
- THE_SYNC_PROCESS: process( SAMPLE_CLK ) \r
+ THE_COARSE_COUNTER_PROC: process( CLK_PING )\r
begin\r
- if( rising_edge(SAMPLE_CLK) ) then\r
- cycle_done <= cycle_done_x;\r
- update <= cycle_done;\r
- phase <= phase_x;\r
+ if( rising_edge(CLK_PING) ) then\r
+ if( START_IN = '1' ) then\r
+ coarse_counter <= (others => '0');\r
+ else\r
+ coarse_counter <= coarse_counter + 1;\r
+ end if;\r
+ if( STOP_IN = '1' ) then\r
+ coarse_delay <= std_logic_vector(coarse_counter);\r
+ end if;\r
end if;\r
- end process THE_SYNC_PROCESS;\r
-\r
- phase_x <= SIGNAL_A_IN xor SIGNAL_B_IN;\r
+ end process THE_COARSE_COUNTER_PROC;\r
+ \r
+---------------------------------------------------------------------------\r
+---------------------------------------------------------------------------\r
+ THE_PHASER_CORE: entity phaser_core \r
+ port map(\r
+ SAMPLE_CLK => SAMPLE_CLK,\r
+ PING_IN => PING_IN,\r
+ CLK_PING => CLK_PING,\r
+ PONG_IN => PONG_IN,\r
+ CLK_PONG => CLK_PONG,\r
+ PHASE_OUT => phase\r
+ );\r
\r
-- Cycle counter\r
THE_CYC_CNT_PROC: process( SAMPLE_CLK, RESET )\r
begin\r
if( RESET = '1' ) then\r
- cyc_cnt <= (others => '0');\r
+ cyc_cnt <= (others => '0');\r
+ cyc_done <= '0';\r
+ update <= '0';\r
elsif( rising_edge(SAMPLE_CLK) ) then\r
- if( cycle_done = '1' ) then\r
+ if( cyc_done = '1' ) then\r
cyc_cnt <= (others => '0');\r
else\r
cyc_cnt <= cyc_cnt + 1;\r
end if;\r
+ cyc_done <= cyc_done_x;\r
+ update <= cyc_done;\r
end if;\r
end process THE_CYC_CNT_PROC;\r
\r
- cycle_done_x <= '1' when (cyc_cnt = x"fffc") else '0';\r
-\r
- -- low signal count\r
- THE_LOW_CNT_PROC: process( SAMPLE_CLK, RESET )\r
- begin\r
- if( RESET = '1' ) then\r
- low_cnt <= (others => '0');\r
- elsif( rising_edge(SAMPLE_CLK) ) then\r
- if( cycle_done = '1' ) then\r
- low_cnt <= (others => '0');\r
- elsif( phase = '0') then\r
- low_cnt <= low_cnt + 1;\r
- end if;\r
- end if;\r
- end process THE_LOW_CNT_PROC;\r
+ cyc_done_x <= '1' when (cyc_cnt = x"fffffc") else '0';\r
\r
-- high signal count\r
THE_HI_CNT_PROC: process( SAMPLE_CLK, RESET )\r
if( RESET = '1' ) then\r
hi_cnt <= (others => '0');\r
elsif( rising_edge(SAMPLE_CLK) ) then\r
- if( cycle_done = '1' ) then\r
+ if( cyc_done = '1' ) then\r
hi_cnt <= (others => '0');\r
elsif( phase = '1') then\r
hi_cnt <= hi_cnt + 1;\r
THE_COUNTER_STORE_PROC: process( SAMPLE_CLK, RESET )\r
begin\r
if( RESET = '1' ) then\r
- low_cnt_int <= (others => '0');\r
hi_cnt_int <= (others => '0');\r
elsif( rising_edge(SAMPLE_CLK) ) then -- added\r
- if( cycle_done = '1' ) then\r
- low_cnt_int <= std_logic_vector(low_cnt);\r
+ if( cyc_done = '1' ) then\r
hi_cnt_int <= std_logic_vector(hi_cnt);\r
end if;\r
end if;\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
\r
- LOW_CNT_OUT <= low_cnt_int;\r
- HI_CNT_OUT <= hi_cnt_int;\r
- UPDATE_OUT <= update;\r
+ RESULT_OUT(31 downto 20) <= coarse_delay(11 downto 0);\r
+ RESULT_OUT(19 downto 0) <= hi_cnt_int(19 downto 0);\r
+ UPDATE_OUT <= update;\r
\r
end architecture;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity phaser_core is\r
+ port(\r
+ SAMPLE_CLK : in std_logic;\r
+ PING_IN : in std_logic; -- TX K\r
+ CLK_PING : in std_logic; -- TX CLK\r
+ PONG_IN : in std_logic; -- RX K\r
+ CLK_PONG : in std_logic; -- RX CLK\r
+ PHASE_OUT : out std_logic\r
+ );\r
+end entity phaser_core;\r
+\r
+architecture phaser_core_arch of phaser_core is\r
+\r
+-- Components\r
+\r
+-- state machine signals\r
+\r
+-- Signals\r
+ signal ping_i : std_logic;\r
+ signal pong_i : std_logic;\r
+ signal phase_x : std_logic;\r
+ signal phase : std_logic;\r
+\r
+ attribute HGROUP : string;\r
+ attribute BBOX : string;\r
+ attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group";\r
+ attribute BBOX of phaser_core_arch : architecture is "1,1";\r
+ attribute syn_sharing : string;\r
+ attribute syn_sharing of phaser_core_arch : architecture is "off";\r
+ attribute syn_hier : string;\r
+ attribute syn_hier of phaser_core_arch : architecture is "hard";\r
+ \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- we want all logic in here in one PFU (defined timing)!\r
+---------------------------------------------------------------------------\r
+\r
+ -- slice 0\r
+ ping_i <= PING_IN when rising_edge(CLK_PING); -- FF\r
+ -- slice 1\r
+ pong_i <= PONG_IN when rising_edge(CLK_PONG); -- FF\r
+ -- slice 2\r
+ phase_x <= ping_i xor pong_i; -- LUT4\r
+ phase <= phase_x when rising_edge(SAMPLE_CLK); -- FF\r
+\r
+ PHASE_OUT <= phase;\r
+\r
+end architecture;\r
jspc29 / trbnet.git / commitdiff