-Backplane 0\r
-===========\r
-\r
-ADC0/0 0 0/6 3 0xb000 0x20030001\r
-ADC0/1 1 0/7 5 0xb001 0x20050001\r
-ADC0/2 2 0/0 10 0xb002 0x200a0001\r
-ADC0/3 3 0/2 12 0xb003 0x200c0001\r
-ADC0/4 4 0/1 9 0xb004 0x20090001\r
-ADC0/5 5 0/3 7 0xb005 0x20070001\r
-ADC0/6 6 0/5 0 0xb006 0x20000001\r
-ADC0/7 7 -/- -- 0xb007 0x200f0001\r
- \r
-ADC1/0 8 1/6 4 0xb008 0x20040001\r
-ADC1/1 9 1/7 6 0xb009 0x20060001\r
-ADC1/2 10 1/1 11 0xb00a 0x200b0001\r
-ADC1/3 11 1/0 8 0xb00b 0x20080001\r
-ADC1/4 12 1/3 14 0xb00c 0x200e0001\r
-ADC1/5 13 1/2 13 0xb00d 0x200d0001\r
-ADC1/6 14 1/5 2 0xb00e 0x20020001\r
-ADC1/7 15 1/4 1 0xb00f 0x20010001\r
-\r
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
-mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1\r
-\r
-Backplane 1\r
-==========\r
-\r
-ADC0/0 0 0/6 12 0xb000 0x200c0001\r
-ADC0/1 1 0/7 11 0xb001 0x200b0001\r
-ADC0/2 2 0/0 10 0xb002 0x200a0001\r
-ADC0/3 3 0/2 9 0xb003 0x20090001\r
-ADC0/4 4 0/1 8 0xb004 0x20080001\r
-ADC0/5 5 0/3 7 0xb005 0x20070001\r
-ADC0/6 6 0/5 13 0xb006 0x200d0001\r
-ADC0/7 7 0/4 14 0xb007 0x200e0001\r
- \r
-ADC1/0 8 1/6 3 0xb008 0x20030001\r
-ADC1/1 9 1/7 2 0xb009 0x20020001\r
-ADC1/2 10 1/1 1 0xb00a 0x20010001\r
-ADC1/3 11 1/0 0 0xb00b 0x20000001\r
-ADC1/4 12 1/3 6 0xb00c 0x20060001\r
-ADC1/5 13 1/2 5 0xb00d 0x20050001\r
-ADC1/6 14 1/5 4 0xb00e 0x20040001\r
-ADC1/7 15 -/- -- 0xb00f 0x200f0001\r
-\r
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
-mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -\r
-\r
-Backplane 2\r
-===========\r
-\r
-ADC0/0 0 -/- -- 0xb000 0x200f0001 \r
-ADC0/1 1 0/7 4 0xb001 0x20040001\r
-ADC0/2 2 0/0 5 0xb002 0x20050001\r
-ADC0/3 3 0/2 6 0xb003 0x20060001\r
-ADC0/4 4 0/1 0 0xb004 0x20000001\r
-ADC0/5 5 0/3 1 0xb005 0x20010001\r
-ADC0/6 6 0/5 2 0xb006 0x20020001\r
-ADC0/7 7 0/4 3 0xb007 0x20030001\r
- \r
-ADC1/0 8 1/6 14 0xb008 0x200e0001\r
-ADC1/1 9 1/7 13 0xb009 0x200d0001\r
-ADC1/2 10 1/1 7 0xb00a 0x20070001\r
-ADC1/3 11 1/0 8 0xb00b 0x20080001\r
-ADC1/4 12 1/3 9 0xb00c 0x20090001\r
-ADC1/5 13 1/2 10 0xb00d 0x200a0001\r
-ADC1/6 14 1/5 11 0xb00e 0x200b0001\r
-ADC1/7 15 1/4 12 0xb00f 0x200c0001\r
-\r
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
-mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12\r
-\r
-Backplane 3\r
-===========\r
-\r
-ADC0/0 0 0/6 10 0xb000 0x200a0001\r
-ADC0/1 1 0/7 9 0xb001 0x20090001\r
-ADC0/2 2 0/0 8 0xb002 0x20080001\r
-ADC0/3 3 0/2 7 0xb003 0x20070001\r
-ADC0/4 4 0/1 6 0xb004 0x20060001\r
-ADC0/5 5 0/3 5 0xb005 0x20050001\r
-ADC0/6 6 0/5 12 0xb006 0x200c0001\r
-ADC0/7 7 0/4 11 0xb007 0x200b0001\r
- \r
-ADC1/0 8 1/6 4 0xb008 0x20040001\r
-ADC1/1 9 1/7 3 0xb009 0x20030001\r
-ADC1/2 10 1/1 0 0xb00a 0x20000001\r
-ADC1/3 11 1/0 2 0xb00b 0x20020001\r
-ADC1/4 12 1/3 1 0xb00c 0x20010001\r
-ADC1/5 13 -/- -- 0xb00d 0x200f0001\r
-ADC1/6 14 1/5 13 0xb00e 0x200d0001\r
-ADC1/7 15 1/4 14 0xb00f 0x200e0001\r
-\r
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
-mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14\r
-\r
-Backplane 4\r
-===========\r
-\r
-ADC0/0 0 0/6 14 0xb000 0x200e0001\r
-ADC0/1 1 0/7 13 0xb001 0x200d0001\r
-ADC0/2 2 -/- -- 0xb002 0x200f0001\r
-ADC0/3 3 0/2 1 0xb003 0x20010001\r
-ADC0/4 4 0/1 2 0xb004 0x20020001\r
-ADC0/5 5 0/3 0 0xb005 0x20000001\r
-ADC0/6 6 0/5 3 0xb006 0x20030001\r
-ADC0/7 7 0/4 4 0xb007 0x20040001\r
- \r
-ADC1/0 8 1/6 11 0xb008 0x200b0001\r
-ADC1/1 9 1/7 12 0xb009 0x200c0001\r
-ADC1/2 10 1/1 5 0xb00a 0x20050001\r
-ADC1/3 11 1/0 6 0xb00b 0x20060001\r
-ADC1/4 12 1/3 7 0xb00c 0x20070001\r
-ADC1/5 13 1/2 8 0xb00d 0x20080001\r
-ADC1/6 14 1/5 9 0xb00e 0x20090001\r
-ADC1/7 15 1/4 10 0xb00f 0x200a0001\r
-\r
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
-mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10\r
+Backplane 0
+===========
+
+ADC0/0 0 0/6 3 0xb000 0x20030001
+ADC0/1 1 0/7 5 0xb001 0x20050001
+ADC0/2 2 0/0 10 0xb002 0x200a0001
+ADC0/3 3 0/2 12 0xb003 0x200c0001
+ADC0/4 4 0/1 9 0xb004 0x20090001
+ADC0/5 5 0/3 7 0xb005 0x20070001
+ADC0/6 6 0/5 0 0xb006 0x20000001
+ADC0/7 7 -/- -- 0xb007 0x200f0001
+
+ADC1/0 8 1/6 4 0xb008 0x20040001
+ADC1/1 9 1/7 6 0xb009 0x20060001
+ADC1/2 10 1/1 11 0xb00a 0x200b0001
+ADC1/3 11 1/0 8 0xb00b 0x20080001
+ADC1/4 12 1/3 14 0xb00c 0x200e0001
+ADC1/5 13 1/2 13 0xb00d 0x200d0001
+ADC1/6 14 1/5 2 0xb00e 0x20020001
+ADC1/7 15 1/4 1 0xb00f 0x20010001
+
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1
+
+Backplane 1
+==========
+
+ADC0/0 0 0/6 12 0xb000 0x200c0001
+ADC0/1 1 0/7 11 0xb001 0x200b0001
+ADC0/2 2 0/0 10 0xb002 0x200a0001
+ADC0/3 3 0/2 9 0xb003 0x20090001
+ADC0/4 4 0/1 8 0xb004 0x20080001
+ADC0/5 5 0/3 7 0xb005 0x20070001
+ADC0/6 6 0/5 13 0xb006 0x200d0001
+ADC0/7 7 0/4 14 0xb007 0x200e0001
+
+ADC1/0 8 1/6 3 0xb008 0x20030001
+ADC1/1 9 1/7 2 0xb009 0x20020001
+ADC1/2 10 1/1 1 0xb00a 0x20010001
+ADC1/3 11 1/0 0 0xb00b 0x20000001
+ADC1/4 12 1/3 6 0xb00c 0x20060001
+ADC1/5 13 1/2 5 0xb00d 0x20050001
+ADC1/6 14 1/5 4 0xb00e 0x20040001
+ADC1/7 15 -/- -- 0xb00f 0x200f0001
+
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -
+
+Backplane 2
+===========
+
+ADC0/0 0 -/- -- 0xb000 0x200f0001
+ADC0/1 1 0/7 4 0xb001 0x20040001
+ADC0/2 2 0/0 5 0xb002 0x20050001
+ADC0/3 3 0/2 6 0xb003 0x20060001
+ADC0/4 4 0/1 0 0xb004 0x20000001
+ADC0/5 5 0/3 1 0xb005 0x20010001
+ADC0/6 6 0/5 2 0xb006 0x20020001
+ADC0/7 7 0/4 3 0xb007 0x20030001
+
+ADC1/0 8 1/6 14 0xb008 0x200e0001
+ADC1/1 9 1/7 13 0xb009 0x200d0001
+ADC1/2 10 1/1 7 0xb00a 0x20070001
+ADC1/3 11 1/0 8 0xb00b 0x20080001
+ADC1/4 12 1/3 9 0xb00c 0x20090001
+ADC1/5 13 1/2 10 0xb00d 0x200a0001
+ADC1/6 14 1/5 11 0xb00e 0x200b0001
+ADC1/7 15 1/4 12 0xb00f 0x200c0001
+
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12
+
+Backplane 3
+===========
+
+ADC0/0 0 0/6 10 0xb000 0x200a0001
+ADC0/1 1 0/7 9 0xb001 0x20090001
+ADC0/2 2 0/0 8 0xb002 0x20080001
+ADC0/3 3 0/2 7 0xb003 0x20070001
+ADC0/4 4 0/1 6 0xb004 0x20060001
+ADC0/5 5 0/3 5 0xb005 0x20050001
+ADC0/6 6 0/5 12 0xb006 0x200c0001
+ADC0/7 7 0/4 11 0xb007 0x200b0001
+
+ADC1/0 8 1/6 4 0xb008 0x20040001
+ADC1/1 9 1/7 3 0xb009 0x20030001
+ADC1/2 10 1/1 0 0xb00a 0x20000001
+ADC1/3 11 1/0 2 0xb00b 0x20020001
+ADC1/4 12 1/3 1 0xb00c 0x20010001
+ADC1/5 13 -/- -- 0xb00d 0x200f0001
+ADC1/6 14 1/5 13 0xb00e 0x200d0001
+ADC1/7 15 1/4 14 0xb00f 0x200e0001
+
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14
+
+Backplane 4
+===========
+
+ADC0/0 0 0/6 14 0xb000 0x200e0001
+ADC0/1 1 0/7 13 0xb001 0x200d0001
+ADC0/2 2 -/- -- 0xb002 0x200f0001
+ADC0/3 3 0/2 1 0xb003 0x20010001
+ADC0/4 4 0/1 2 0xb004 0x20020001
+ADC0/5 5 0/3 0 0xb005 0x20000001
+ADC0/6 6 0/5 3 0xb006 0x20030001
+ADC0/7 7 0/4 4 0xb007 0x20040001
+
+ADC1/0 8 1/6 11 0xb008 0x200b0001
+ADC1/1 9 1/7 12 0xb009 0x200c0001
+ADC1/2 10 1/1 5 0xb00a 0x20050001
+ADC1/3 11 1/0 6 0xb00b 0x20060001
+ADC1/4 12 1/3 7 0xb00c 0x20070001
+ADC1/5 13 1/2 8 0xb00d 0x20080001
+ADC1/6 14 1/5 9 0xb00e 0x20090001
+ADC1/7 15 1/4 10 0xb00f 0x200a0001
+
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10
-library ieee; \r
-use ieee.std_logic_1164.all; \r
-use ieee.std_logic_arith.all; \r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
entity adc_channel_select is\r
- port( RESET_IN : in std_logic;\r
- ADC_CLK_IN : in std_logic;\r
- ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
- ADC_7_IN : in std_logic_vector(11 downto 0);\r
- ADC_6_IN : in std_logic_vector(11 downto 0);\r
- ADC_5_IN : in std_logic_vector(11 downto 0);\r
- ADC_4_IN : in std_logic_vector(11 downto 0);\r
- ADC_3_IN : in std_logic_vector(11 downto 0);\r
- ADC_2_IN : in std_logic_vector(11 downto 0);\r
- ADC_1_IN : in std_logic_vector(11 downto 0);\r
- ADC_0_IN : in std_logic_vector(11 downto 0);\r
- ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ RESET_IN : in std_logic;\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
+ ADC_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_0_IN : in std_logic_vector(11 downto 0);\r
+ ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of adc_channel_select is\r
\r
- -- Placer Directives\r
+-- Placer Directives\r
\r
- -- normal signals \r
- signal adc_ch : std_logic_vector(11 downto 0);\r
- signal adc_sel : std_logic_vector(2 downto 0);\r
- signal reset : std_logic;\r
+-- normal signals\r
+signal adc_ch : std_logic_vector(11 downto 0);\r
+signal adc_sel : std_logic_vector(2 downto 0);\r
+signal reset : std_logic;\r
\r
- signal debug : std_logic_vector(15 downto 0);\r
+signal debug : std_logic_vector(15 downto 0);\r
\r
\r
-begin \r
+begin\r
\r
-- Reset synchronizer\r
THE_RESET_SYNC: state_sync\r
-port map( STATE_A_IN => reset_in,\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => reset\r
- );\r
+port map(\r
+ STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+);\r
\r
-- select signals are from 100MHz clock domain!\r
THE_SEL2_SYNC: state_sync\r
-port map( STATE_A_IN => adc_sel_in(2),\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset,\r
- STATE_B_OUT => adc_sel(2)\r
- );\r
+port map(\r
+ STATE_A_IN => adc_sel_in(2),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => adc_sel(2)\r
+);\r
THE_SEL1_SYNC: state_sync\r
-port map( STATE_A_IN => adc_sel_in(1),\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset,\r
- STATE_B_OUT => adc_sel(1)\r
- );\r
+port map(\r
+ STATE_A_IN => adc_sel_in(1),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => adc_sel(1)\r
+);\r
THE_SEL0_SYNC: state_sync\r
-port map( STATE_A_IN => adc_sel_in(0),\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset,\r
- STATE_B_OUT => adc_sel(0)\r
- );\r
+port map(\r
+ STATE_A_IN => adc_sel_in(0),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => adc_sel(0)\r
+);\r
+\r
\r
- \r
-- registered multiplexer\r
THE_SEL_PROC: process( adc_clk_in )\r
begin\r
adc_ch <= (others => '0');\r
else\r
case adc_sel is\r
- when b"000" => adc_ch <= adc_0_in;\r
- when b"001" => adc_ch <= adc_1_in;\r
- when b"010" => adc_ch <= adc_2_in;\r
- when b"011" => adc_ch <= adc_3_in;\r
- when b"100" => adc_ch <= adc_4_in;\r
- when b"101" => adc_ch <= adc_5_in;\r
- when b"110" => adc_ch <= adc_6_in;\r
- when b"111" => adc_ch <= adc_7_in;\r
- when others => adc_ch <= x"000"; -- never\r
+ when b"000" => adc_ch <= adc_0_in;\r
+ when b"001" => adc_ch <= adc_1_in;\r
+ when b"010" => adc_ch <= adc_2_in;\r
+ when b"011" => adc_ch <= adc_3_in;\r
+ when b"100" => adc_ch <= adc_4_in;\r
+ when b"101" => adc_ch <= adc_5_in;\r
+ when b"110" => adc_ch <= adc_6_in;\r
+ when b"111" => adc_ch <= adc_7_in;\r
+ when others => adc_ch <= x"000"; -- never\r
end case;\r
end if;\r
- end if; \r
+ end if;\r
end process THE_SEL_PROC;\r
\r
-- debug signals\r
\r
-- output signals\r
adc_ch_out <= adc_ch;\r
-debug_out <= debug; \r
+debug_out <= debug;\r
\r
-end behavioral; \r
+end behavioral;\r
use work.adcmv3_components.all;\r
\r
entity adc_crossover is\r
- port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
- RESET_IN : in std_logic; -- general reset (100MHz)\r
- -- ADC clock domain signals\r
- ADC_CLK_IN : in std_logic;\r
- ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
- ADC_DATA_VALID_IN : in std_logic;\r
- ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
- LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
- -- APV clock domain signals\r
- APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_VALID_OUT : out std_logic;\r
- LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
+ ADC_DATA_VALID_IN : in std_logic;\r
+ ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
+ LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : out std_logic;\r
+ LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of adc_crossover is\r
\r
- signal debug : std_logic_vector(31 downto 0);\r
-\r
- signal fifo_rd_level : std_logic_vector(4 downto 0);\r
- signal fifo_wr_level : std_logic_vector(4 downto 0);\r
- signal next_fifo_rd_ena : std_logic;\r
- signal fifo_rd_ena : std_logic;\r
- signal next_fifo_wr_ena : std_logic;\r
- signal fifo_wr_ena : std_logic;\r
- signal next_reset : std_logic;\r
- signal reset : std_logic;\r
- signal apv_data_valid : std_logic_vector(2 downto 0);\r
- \r
+signal debug : std_logic_vector(31 downto 0);\r
+\r
+signal fifo_rd_level : std_logic_vector(4 downto 0);\r
+signal fifo_wr_level : std_logic_vector(4 downto 0);\r
+signal next_fifo_rd_ena : std_logic;\r
+signal fifo_rd_ena : std_logic;\r
+signal next_fifo_wr_ena : std_logic;\r
+signal fifo_wr_ena : std_logic;\r
+signal next_reset : std_logic;\r
+signal reset : std_logic;\r
+signal apv_data_valid : std_logic_vector(2 downto 0);\r
+\r
begin\r
\r
---------------------------------------------------------------------------\r
next_reset <= reset_in or not adc_data_valid_in;\r
\r
THE_RESET_STATE_SYNC: state_sync\r
-port map( STATE_A_IN => next_reset,\r
- CLK_B_IN => clk_apv_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => reset\r
- );\r
+port map(\r
+ STATE_A_IN => next_reset,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+);\r
\r
\r
---------------------------------------------------------------------------\r
--- Crossover fifo for ADC \r
+-- Crossover fifo for ADC\r
---------------------------------------------------------------------------\r
next_fifo_wr_ena <= adc_ce_in and adc_data_valid_in;\r
next_fifo_rd_ena <= '1' when ( fifo_rd_level > b"0_0101" ) else '0';\r
\r
-SYNC_WRCLK_PROC: process( adc_clk_in ) \r
+SYNC_WRCLK_PROC: process( adc_clk_in )\r
begin\r
if( rising_edge(adc_clk_in) ) then\r
fifo_wr_ena <= next_fifo_wr_ena;\r
end if;\r
end process SYNC_WRCLK_PROC;\r
\r
-SYNC_RDCLK_PROC: process( clk_apv_in ) \r
+SYNC_RDCLK_PROC: process( clk_apv_in )\r
begin\r
if( rising_edge(clk_apv_in) ) then\r
fifo_rd_ena <= next_fifo_rd_ena;\r
end process SYNC_RDCLK_PROC;\r
\r
THE_CROSSOVER: crossover\r
-port map( DATA(95 downto 84) => adc_data_7_in,\r
- DATA(83 downto 72) => adc_data_6_in,\r
- DATA(71 downto 60) => adc_data_5_in,\r
- DATA(59 downto 48) => adc_data_4_in,\r
- DATA(47 downto 36) => adc_data_3_in,\r
- DATA(35 downto 24) => adc_data_2_in,\r
- DATA(23 downto 12) => adc_data_1_in,\r
- DATA(11 downto 0) => adc_data_0_in,\r
- WRCLOCK => adc_clk_in,\r
- RDCLOCK => clk_apv_in,\r
- WREN => fifo_wr_ena,\r
- RDEN => fifo_rd_ena,\r
- RESET => reset, -- this is an async clear input!\r
- RPRESET => '0', -- not needed, as OR'ed with RESET\r
- Q(95 downto 84) => apv_data_7_out,\r
- Q(83 downto 72) => apv_data_6_out,\r
- Q(71 downto 60) => apv_data_5_out,\r
- Q(59 downto 48) => apv_data_4_out,\r
- Q(47 downto 36) => apv_data_3_out,\r
- Q(35 downto 24) => apv_data_2_out,\r
- Q(23 downto 12) => apv_data_1_out,\r
- Q(11 downto 0) => apv_data_0_out,\r
- WCNT => fifo_wr_level,\r
- RCNT => fifo_rd_level,\r
- EMPTY => open,\r
- FULL => open\r
- );\r
+port map(\r
+ DATA(95 downto 84) => adc_data_7_in,\r
+ DATA(83 downto 72) => adc_data_6_in,\r
+ DATA(71 downto 60) => adc_data_5_in,\r
+ DATA(59 downto 48) => adc_data_4_in,\r
+ DATA(47 downto 36) => adc_data_3_in,\r
+ DATA(35 downto 24) => adc_data_2_in,\r
+ DATA(23 downto 12) => adc_data_1_in,\r
+ DATA(11 downto 0) => adc_data_0_in,\r
+ WRCLOCK => adc_clk_in,\r
+ RDCLOCK => clk_apv_in,\r
+ WREN => fifo_wr_ena,\r
+ RDEN => fifo_rd_ena,\r
+ RESET => reset, -- this is an async clear input!\r
+ RPRESET => '0', -- not needed, as OR'ed with RESET\r
+ Q(95 downto 84) => apv_data_7_out,\r
+ Q(83 downto 72) => apv_data_6_out,\r
+ Q(71 downto 60) => apv_data_5_out,\r
+ Q(59 downto 48) => apv_data_4_out,\r
+ Q(47 downto 36) => apv_data_3_out,\r
+ Q(35 downto 24) => apv_data_2_out,\r
+ Q(23 downto 12) => apv_data_1_out,\r
+ Q(11 downto 0) => apv_data_0_out,\r
+ WCNT => fifo_wr_level,\r
+ RCNT => fifo_rd_level,\r
+ EMPTY => open,\r
+ FULL => open\r
+);\r
\r
\r
---------------------------------------------------------------------------\r
-library ieee; \r
-use ieee.std_logic_1164.all; \r
-use ieee.std_logic_arith.all; \r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
entity adc_data_handler_new is\r
- port( RESET_IN : in std_logic;\r
- ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
- ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
- ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
- PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
- ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
- ADC_CE_OUT : out std_logic;\r
- ADC_VALID_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ RESET_IN : in std_logic;\r
+ ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
+ ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
+ ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
+ ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : out std_logic;\r
+ ADC_VALID_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of adc_data_handler_new is\r
\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of behavioral : architecture is "ADC_DATA_HANDLER_group";\r
-\r
- -- normal signals \r
- signal adc_adclk_vec : std_logic_vector(0 downto 0);\r
- signal adc_adclk : std_logic_vector(1 downto 0);\r
- \r
- signal adc_ch_7_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_6_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_5_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_4_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_3_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_2_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_1_mux : std_logic_vector(1 downto 0);\r
- signal adc_ch_0_mux : std_logic_vector(1 downto 0);\r
- \r
- signal last_adc_7_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_6_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_5_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_4_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_3_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_2_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_1_ch : std_logic_vector(11 downto 0);\r
- signal last_adc_0_ch : std_logic_vector(11 downto 0);\r
-\r
- signal buf_adc_7_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_6_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_5_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_4_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_3_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_2_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_1_ch : std_logic_vector(11 downto 0);\r
- signal buf_adc_0_ch : std_logic_vector(11 downto 0);\r
-\r
- signal realstore : std_logic_vector(3 downto 0);\r
- signal next_recstore : std_logic;\r
- signal recstore : std_logic_vector(3 downto 0);\r
-\r
- signal reset : std_logic; -- synchronized to 240MHz local clock\r
-\r
- signal input_delay : std_logic_vector(3 downto 0);\r
-\r
- signal bitcounter : std_logic_vector(2 downto 0);\r
- signal synccounter : std_logic_vector(2 downto 0);\r
- signal next_ce_inc : std_logic;\r
- signal ce_inc : std_logic;\r
- signal next_ce_dec : std_logic;\r
- signal ce_dec : std_logic;\r
- signal next_sync_low : std_logic;\r
- signal sync_low : std_logic;\r
- signal next_sync_high : std_logic;\r
- signal sync_high : std_logic;\r
-\r
- signal debug : std_logic_vector(15 downto 0);\r
- \r
-begin \r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behavioral : architecture is "ADC_DATA_HANDLER_group";\r
+\r
+-- normal signals\r
+signal adc_adclk_vec : std_logic_vector(0 downto 0);\r
+signal adc_adclk : std_logic_vector(1 downto 0);\r
+\r
+signal adc_ch_7_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_6_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_5_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_4_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_3_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_2_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_1_mux : std_logic_vector(1 downto 0);\r
+signal adc_ch_0_mux : std_logic_vector(1 downto 0);\r
+\r
+signal last_adc_7_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_6_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_5_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_4_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_3_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_2_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_1_ch : std_logic_vector(11 downto 0);\r
+signal last_adc_0_ch : std_logic_vector(11 downto 0);\r
+\r
+signal buf_adc_7_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_6_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_5_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_4_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_3_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_2_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_1_ch : std_logic_vector(11 downto 0);\r
+signal buf_adc_0_ch : std_logic_vector(11 downto 0);\r
+\r
+signal realstore : std_logic_vector(3 downto 0);\r
+signal next_recstore : std_logic;\r
+signal recstore : std_logic_vector(3 downto 0);\r
+\r
+signal reset : std_logic; -- synchronized to 240MHz local clock\r
+\r
+signal input_delay : std_logic_vector(3 downto 0);\r
+\r
+signal bitcounter : std_logic_vector(2 downto 0);\r
+signal synccounter : std_logic_vector(2 downto 0);\r
+signal next_ce_inc : std_logic;\r
+signal ce_inc : std_logic;\r
+signal next_ce_dec : std_logic;\r
+signal ce_dec : std_logic;\r
+signal next_sync_low : std_logic;\r
+signal sync_low : std_logic;\r
+signal next_sync_high : std_logic;\r
+signal sync_high : std_logic;\r
+\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
+begin\r
\r
-- input delay for IDDR, 50ps / unit\r
input_delay <= pll_ctrl_in;\r
\r
--- Reset synchronizer \r
+-- Reset synchronizer\r
THE_RESET_SYNC: state_sync\r
-port map( STATE_A_IN => reset_in,\r
- CLK_B_IN => adc_lclk_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => reset\r
- );\r
+port map(\r
+ STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_lclk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+);\r
\r
-- We have to reconstruct the ADC word clock (ADCLK).\r
--- Mind the vector! \r
-adc_adclk_vec(0) <= adc_adclk_in; \r
- \r
-THE_ADC_ADCLK_IN: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_adclk_vec, \r
- Q => adc_adclk \r
- ); \r
+-- Mind the vector!\r
+adc_adclk_vec(0) <= adc_adclk_in;\r
+\r
+THE_ADC_ADCLK_IN: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_adclk_vec,\r
+ Q => adc_adclk\r
+);\r
\r
-- First group of channels (0 and 1)\r
-THE_DIN_0: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(0 downto 0), \r
- Q => adc_ch_0_mux \r
- ); \r
-THE_DIN_1: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(1 downto 1), \r
- Q => adc_ch_1_mux \r
- ); \r
+THE_DIN_0: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(0 downto 0),\r
+ Q => adc_ch_0_mux\r
+);\r
+THE_DIN_1: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(1 downto 1),\r
+ Q => adc_ch_1_mux\r
+);\r
THE_ADC_0_1_CH: adc_twochannels\r
-port map( CLK_IN => adc_lclk_in,\r
- RESET_IN => reset,\r
- CLOCK_IN => adc_adclk,\r
- DATA_0_IN => adc_ch_0_mux,\r
- DATA_1_IN => adc_ch_1_mux,\r
- DATA_0_OUT => last_adc_0_ch,\r
- DATA_1_OUT => last_adc_1_ch,\r
- STORE_OUT => realstore(0),\r
- SWAP_OUT => open,\r
- CLOCK_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_0_mux,\r
+ DATA_1_IN => adc_ch_1_mux,\r
+ DATA_0_OUT => last_adc_0_ch,\r
+ DATA_1_OUT => last_adc_1_ch,\r
+ STORE_OUT => realstore(0),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
-- Second group of channels (2 and 3)\r
-THE_DIN_2: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(2 downto 2), \r
- Q => adc_ch_2_mux \r
- ); \r
-THE_DIN_3: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(3 downto 3), \r
- Q => adc_ch_3_mux \r
- ); \r
+THE_DIN_2: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(2 downto 2),\r
+ Q => adc_ch_2_mux\r
+);\r
+THE_DIN_3: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(3 downto 3),\r
+ Q => adc_ch_3_mux\r
+);\r
THE_ADC_2_3_CH: adc_twochannels\r
-port map( CLK_IN => adc_lclk_in,\r
- RESET_IN => reset,\r
- CLOCK_IN => adc_adclk,\r
- DATA_0_IN => adc_ch_2_mux,\r
- DATA_1_IN => adc_ch_3_mux,\r
- DATA_0_OUT => last_adc_2_ch,\r
- DATA_1_OUT => last_adc_3_ch,\r
- STORE_OUT => realstore(1),\r
- SWAP_OUT => open,\r
- CLOCK_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_2_mux,\r
+ DATA_1_IN => adc_ch_3_mux,\r
+ DATA_0_OUT => last_adc_2_ch,\r
+ DATA_1_OUT => last_adc_3_ch,\r
+ STORE_OUT => realstore(1),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
-- Third group of channels (4 and 5)\r
-THE_DIN_4: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(4 downto 4), \r
- Q => adc_ch_4_mux \r
- ); \r
-THE_DIN_5: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(5 downto 5), \r
- Q => adc_ch_5_mux \r
- ); \r
+THE_DIN_4: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(4 downto 4),\r
+ Q => adc_ch_4_mux\r
+);\r
+THE_DIN_5: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(5 downto 5),\r
+ Q => adc_ch_5_mux\r
+);\r
THE_ADC_4_5_CH: adc_twochannels\r
-port map( CLK_IN => adc_lclk_in,\r
- RESET_IN => reset,\r
- CLOCK_IN => adc_adclk,\r
- DATA_0_IN => adc_ch_4_mux,\r
- DATA_1_IN => adc_ch_5_mux,\r
- DATA_0_OUT => last_adc_4_ch,\r
- DATA_1_OUT => last_adc_5_ch,\r
- STORE_OUT => realstore(2),\r
- SWAP_OUT => open,\r
- CLOCK_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_4_mux,\r
+ DATA_1_IN => adc_ch_5_mux,\r
+ DATA_0_OUT => last_adc_4_ch,\r
+ DATA_1_OUT => last_adc_5_ch,\r
+ STORE_OUT => realstore(2),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
-- Fourth group of channels (6 and 7)\r
-THE_DIN_6: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(6 downto 6), \r
- Q => adc_ch_6_mux \r
- ); \r
-THE_DIN_7: adc_ch_in \r
-port map( DEL => input_delay,\r
- ECLK => adc_lclk_in, \r
- SCLK => adc_lclk_in, \r
- RST => '0', \r
- DATA => adc_chnl_in(7 downto 7), \r
- Q => adc_ch_7_mux \r
- ); \r
+THE_DIN_6: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(6 downto 6),\r
+ Q => adc_ch_6_mux\r
+);\r
+THE_DIN_7: adc_ch_in\r
+port map(\r
+ DEL => input_delay,\r
+ ECLK => adc_lclk_in,\r
+ SCLK => adc_lclk_in,\r
+ RST => '0',\r
+ DATA => adc_chnl_in(7 downto 7),\r
+ Q => adc_ch_7_mux\r
+);\r
THE_ADC_6_7_CH: adc_twochannels\r
-port map( CLK_IN => adc_lclk_in,\r
- RESET_IN => reset,\r
- CLOCK_IN => adc_adclk,\r
- DATA_0_IN => adc_ch_6_mux,\r
- DATA_1_IN => adc_ch_7_mux,\r
- DATA_0_OUT => last_adc_6_ch,\r
- DATA_1_OUT => last_adc_7_ch,\r
- STORE_OUT => realstore(3),\r
- SWAP_OUT => open,\r
- CLOCK_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_6_mux,\r
+ DATA_1_IN => adc_ch_7_mux,\r
+ DATA_0_OUT => last_adc_6_ch,\r
+ DATA_1_OUT => last_adc_7_ch,\r
+ STORE_OUT => realstore(3),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
-- Clock reconstruction (will only work if all four units work in perfect alignment)\r
next_recstore <= '1' when ( realstore = b"1111" ) else '0';\r
\r
\r
-- output signals\r
-adc_data7_out <= buf_adc_7_ch; \r
-adc_data6_out <= buf_adc_6_ch; \r
-adc_data5_out <= buf_adc_5_ch; \r
-adc_data4_out <= buf_adc_4_ch; \r
-adc_data3_out <= buf_adc_3_ch; \r
-adc_data2_out <= buf_adc_2_ch; \r
-adc_data1_out <= buf_adc_1_ch; \r
-adc_data0_out <= buf_adc_0_ch; \r
+adc_data7_out <= buf_adc_7_ch;\r
+adc_data6_out <= buf_adc_6_ch;\r
+adc_data5_out <= buf_adc_5_ch;\r
+adc_data4_out <= buf_adc_4_ch;\r
+adc_data3_out <= buf_adc_3_ch;\r
+adc_data2_out <= buf_adc_2_ch;\r
+adc_data1_out <= buf_adc_1_ch;\r
+adc_data0_out <= buf_adc_0_ch;\r
adc_ce_out <= recstore(3);\r
adc_valid_out <= sync_high;\r
- \r
-debug_out(15 downto 0) <= debug; \r
- \r
-end behavioral; \r
-
\ No newline at end of file
+\r
+debug_out(15 downto 0) <= debug;\r
+\r
+end behavioral;\r
+
\ No newline at end of file
use work.adcmv3_components.all;\r
\r
entity adc_twochannels is\r
- port( CLK_IN : in std_logic; -- DDR bit clock\r
- RESET_IN : in std_logic;\r
- CLOCK_IN : in std_logic_vector(1 downto 0); -- word clock\r
- DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
- DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
- DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
- DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
- STORE_OUT : out std_logic;\r
- SWAP_OUT : out std_logic;\r
- CLOCK_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- DDR bit clock\r
+ RESET_IN : in std_logic;\r
+ CLOCK_IN : in std_logic_vector(1 downto 0); -- word clock\r
+ DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
+ DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
+ DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
+ DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
+ STORE_OUT : out std_logic;\r
+ SWAP_OUT : out std_logic;\r
+ CLOCK_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behaviour of adc_twochannels is\r
\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of behaviour : architecture is "TWOCHANNELS_group";\r
-\r
- type half_data_t is array (0 to 1) of std_logic_vector(5 downto 0);\r
- signal qda : half_data_t; -- serial input data, raising edge\r
- signal qdb : half_data_t; -- serial input data, falling edge\r
- signal parda : half_data_t; -- parallel input data, raising edge\r
- signal pardb : half_data_t; -- parallel input data, falling edge\r
- signal qc : half_data_t; -- serial ADCLK signal, (0) raising edge, (1) falling edge\r
- type full_data_t is array (0 to 1) of std_logic_vector(11 downto 0);\r
- signal muxed : full_data_t;\r
- signal data : full_data_t;\r
-\r
- signal next_store_a : std_logic;\r
- signal store_a : std_logic; -- store serial data A to parallel temp register\r
- signal next_store_b : std_logic;\r
- signal store_b : std_logic; -- store serial data B to parallel temp register\r
- signal check : std_logic; -- auxiliary signal for swapping\r
- signal next_swap : std_logic;\r
- signal swap : std_logic; -- swap half words before assembling\r
- signal store : std_logic; -- assemble full word\r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behaviour : architecture is "TWOCHANNELS_group";\r
+\r
+type half_data_t is array (0 to 1) of std_logic_vector(5 downto 0);\r
+signal qda : half_data_t; -- serial input data, raising edge\r
+signal qdb : half_data_t; -- serial input data, falling edge\r
+signal parda : half_data_t; -- parallel input data, raising edge\r
+signal pardb : half_data_t; -- parallel input data, falling edge\r
+signal qc : half_data_t; -- serial ADCLK signal, (0) raising edge, (1) falling edge\r
+type full_data_t is array (0 to 1) of std_logic_vector(11 downto 0);\r
+signal muxed : full_data_t;\r
+signal data : full_data_t;\r
+\r
+signal next_store_a : std_logic;\r
+signal store_a : std_logic; -- store serial data A to parallel temp register\r
+signal next_store_b : std_logic;\r
+signal store_b : std_logic; -- store serial data B to parallel temp register\r
+signal check : std_logic; -- auxiliary signal for swapping\r
+signal next_swap : std_logic;\r
+signal swap : std_logic; -- swap half words before assembling\r
+signal store : std_logic; -- assemble full word\r
\r
begin\r
\r
if( store_a = '1' ) then\r
parda(0) <= qda(0);\r
parda(1) <= qda(1);\r
- end if;\r
+ end if;\r
if( store_b = '1' ) then\r
pardb(0) <= qdb(0);\r
pardb(1) <= qdb(1);\r
- end if;\r
+ end if;\r
end if;\r
end process THE_PARALLEL_STORE_PROC;\r
\r
THE_SWAP_PROC: process( parda, pardb, swap )\r
begin\r
case swap is\r
- when '1' => -- first channel\r
+ when '1' => -- first channel\r
muxed(0)(0) <= pardb(0)(5);\r
muxed(0)(1) <= parda(0)(5);\r
muxed(0)(2) <= pardb(0)(4);\r
muxed(1)(9) <= parda(1)(1);\r
muxed(1)(10) <= pardb(1)(0);\r
muxed(1)(11) <= parda(1)(0);\r
- when '0' => -- first channel\r
+ when '0' => -- first channel\r
muxed(0)(0) <= parda(0)(5);\r
muxed(0)(1) <= pardb(0)(5);\r
muxed(0)(2) <= parda(0)(4);\r
debug_out(12) <= store_a;\r
debug_out(11 downto 0) <= data(0);\r
\r
---debug_out(15 downto 15) <= (others => '0');\r
---debug_out(14) <= swap;\r
---debug_out(13) <= store_b;\r
---debug_out(12) <= store_a;\r
---debug_out(11 downto 6) <= parda(0);\r
---debug_out(5 downto 0) <= pardb(0);\r
-\r
-\r
end behaviour;\r
\r
use work.adcmv3_components.all;\r
\r
entity adcmv3 is\r
- port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
- -- trigger inputs\r
- EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
- -- APV stuff\r
- APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
- APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
- APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
- APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
- APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
- APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
- APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
- ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
- APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
- APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
- APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
- APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
- APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
- APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
- APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
- ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
- -- ADC0 stuff\r
- ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
- ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
- ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
- ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
- ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
- ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
- ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
- ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
- ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
- -- ADC1 stuff\r
- ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
- ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
- ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
- ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
- ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
- ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
- ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
- ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
- ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
- -- uC connections\r
- UC_RESET : in std_logic; -- OK -- uC reset, high active\r
- UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
- -- SerDes pins \r
- HDINN2 : in std_logic; -- highspeed INPUT\r
- HDINP2 : in std_logic; --\r
- HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
- HDOUTP2 : out std_logic; -- \r
- SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
- SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
- SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
- ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
- -- Backplane sense wires\r
- BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
- BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
- BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
- BP_LED : out std_logic; -- OK -- backplane LED \r
- -- LEDs\r
- FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
- FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
- FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
- FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
- FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
- FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
- -- 1Wire chips on APV FEs\r
- APV0_1W : inout std_logic_vector(7 downto 0);\r
- APV1_1W : inout std_logic_vector(7 downto 0);\r
- -- SPI FlashROM connections\r
- U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
- U_SPI_SCK : out std_logic; -- OK -- clock\r
- U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
- U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM\r
- -- Debug connections\r
- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
- );\r
+port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
+ -- trigger inputs\r
+ EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
+ -- APV stuff\r
+ APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
+ APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
+ APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
+ ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
+ APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
+ APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
+ ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ -- ADC0 stuff\r
+ ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- ADC1 stuff\r
+ ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- uC connections\r
+ UC_RESET : in std_logic; -- OK -- uC reset, high active\r
+ UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
+ -- SerDes pins \r
+ HDINN2 : in std_logic; -- highspeed INPUT\r
+ HDINP2 : in std_logic; --\r
+ HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
+ HDOUTP2 : out std_logic; -- \r
+ SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
+ SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
+ SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
+ ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
+ -- Backplane sense wires\r
+ BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
+ BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
+ BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
+ BP_LED : out std_logic; -- OK -- backplane LED \r
+ -- LEDs\r
+ FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
+ FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
+ FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
+ FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
+ FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
+ FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
+ -- 1Wire chips on APV FEs\r
+ APV0_1W : inout std_logic_vector(7 downto 0);\r
+ APV1_1W : inout std_logic_vector(7 downto 0);\r
+ -- SPI FlashROM connections\r
+ U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
+ U_SPI_SCK : out std_logic; -- OK -- clock\r
+ U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
+ U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM\r
+ -- Debug connections\r
+ DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+);\r
end;\r
\r
architecture adcmv3 of adcmv3 is\r
\r
--- Signals\r
- -- Clock related signals\r
- signal clk100m_locked : std_logic; -- not needed at the moment\r
- signal sysclk : std_logic; -- clean 100MHz for distribution\r
-\r
- signal adc0_ce : std_logic;\r
- signal adc0_valid : std_logic;\r
- signal adc0_reset : std_logic;\r
- signal adc0_powerdown : std_logic;\r
- signal adc1_ce : std_logic;\r
- signal adc1_valid : std_logic;\r
- signal adc1_reset : std_logic;\r
- signal adc1_powerdown : std_logic;\r
-\r
- signal clk_adc : std_logic; -- 40MHz for ADC operation\r
- signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!)\r
- signal clk40m_locked : std_logic;\r
- signal clk40m_reset : std_logic;\r
-\r
- signal async_reset : std_logic;\r
-\r
- -- APV related signals\r
- signal apv_sda_out : std_logic; -- APV SDA\r
- signal apv_sda_in : std_logic;\r
- signal apv_scl_out : std_logic; -- APV SCL\r
- signal apv_scl_in : std_logic;\r
- signal apv_trg : std_logic; -- real APV trigger signal\r
- signal apv_sync : std_logic; -- artificial signal\r
- signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
- signal apv0_reset : std_logic;\r
- signal apv1_reset : std_logic;\r
- signal apv_reset : std_logic;\r
- signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
- signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
-\r
- -- Control signals\r
- signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register\r
- signal status_pll : std_logic_vector(15 downto 0); -- PLL status register\r
- signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register\r
- signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register\r
- \r
- signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header\r
- signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header\r
- signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting\r
- signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting\r
-\r
- signal maximum_trg : std_logic_vector(3 downto 0);\r
-\r
- signal raw_buf_full : std_logic;\r
- signal eds_buf_full : std_logic;\r
- signal eds_buf_level : std_logic_vector(4 downto 0);\r
-\r
- -- regIO data bus\r
- signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
- signal regio_read_enable : std_logic;\r
- signal regio_write_enable : std_logic;\r
- signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
- signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
- signal regio_dataready : std_logic;\r
- signal regio_no_more_data : std_logic;\r
- signal regio_write_ack : std_logic;\r
- signal regio_unknown_addr : std_logic;\r
- signal regio_timeout : std_logic;\r
-\r
- -- common status / control registers from RegIO\r
- signal common_stat_reg : std_logic_vector(63 downto 0);\r
- signal common_ctrl_reg : std_logic_vector(63 downto 0);\r
-\r
- -- user defined "quick'n'dirty" registers\r
- signal simple_status : std_logic_vector(127 downto 0);\r
- signal simple_control : std_logic_vector(63 downto 0);\r
-\r
- -- debug signals\r
- signal test_reg : std_logic_vector(31 downto 0);\r
- signal trbrich_debug : std_logic_vector(63 downto 0);\r
- signal trgctrl_debug : std_logic_vector(63 downto 0);\r
- signal slave_debug : std_logic_vector(63 downto 0);\r
- signal fifo_debug : std_logic_vector(63 downto 0);\r
- signal raw_buf_debug : std_logic_vector(63 downto 0);\r
-\r
- -- EDS / BUFFER signals (raw buf -> ped corr)\r
- signal eds_data : std_logic_vector(39 downto 0);\r
- signal eds_avail : std_logic;\r
- signal eds_done : std_logic;\r
- signal buf_addr : std_logic_vector(6 downto 0);\r
- signal buf_done : std_logic;\r
- signal buf_tick : std_logic_vector(15 downto 0);\r
- signal buf_start : std_logic_vector(15 downto 0);\r
- signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging!\r
-\r
- type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
- signal buf_data : reg_38bit_t;\r
-\r
- signal thr_addr : std_logic_vector(6 downto 0);\r
- type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
- signal thr_data : reg_18bit_t;\r
- signal ped_data : reg_18bit_t;\r
-\r
- -- FIFO / DHDR signals (ped corr -> ipu stage)\r
- signal dhdr_data : std_logic_vector(31 downto 0);\r
- signal dhdr_length : std_logic_vector(15 downto 0);\r
- signal dhdr_store : std_logic;\r
- signal dhdr_buf_full : std_logic;\r
-\r
- signal fifo_start : std_logic;\r
- signal fifo_done : std_logic;\r
- signal fifo_we : std_logic_vector(15 downto 0);\r
- type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
- signal fifo_data : reg_40bit_t;\r
-\r
- -- APV control / status signals\r
- type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
- signal adc_ctrl_reg : reg_16bit_t;\r
- signal adc_stat_reg : reg_16bit_t;\r
-\r
- signal debug : std_logic_vector(42 downto 0);\r
- signal debug_q : std_logic_vector(42 downto 0);\r
- signal debug_qq : std_logic_vector(42 downto 0);\r
- signal debug_clk : std_logic;\r
+-- Signals\r
+-- Clock related signals\r
+signal clk100m_locked : std_logic; -- not needed at the moment\r
+signal sysclk : std_logic; -- clean 100MHz for distribution\r
+\r
+signal adc0_ce : std_logic;\r
+signal adc0_valid : std_logic;\r
+signal adc0_reset : std_logic;\r
+signal adc0_powerdown : std_logic;\r
+signal adc1_ce : std_logic;\r
+signal adc1_valid : std_logic;\r
+signal adc1_reset : std_logic;\r
+signal adc1_powerdown : std_logic;\r
+\r
+signal clk_adc : std_logic; -- 40MHz for ADC operation\r
+signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!)\r
+signal clk40m_locked : std_logic;\r
+signal clk40m_reset : std_logic;\r
+\r
+signal async_reset : std_logic;\r
+\r
+-- APV related signals\r
+signal apv_sda_out : std_logic; -- APV SDA\r
+signal apv_sda_in : std_logic;\r
+signal apv_scl_out : std_logic; -- APV SCL\r
+signal apv_scl_in : std_logic;\r
+signal apv_trg : std_logic; -- real APV trigger signal\r
+signal apv_sync : std_logic; -- artificial signal\r
+signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
+signal apv0_reset : std_logic;\r
+signal apv1_reset : std_logic;\r
+signal apv_reset : std_logic;\r
+signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+\r
+-- Control signals\r
+signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register\r
+signal status_pll : std_logic_vector(15 downto 0); -- PLL status register\r
+signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register\r
+signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register\r
+ \r
+signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header\r
+signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header\r
+signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting\r
+signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting\r
+\r
+signal maximum_trg : std_logic_vector(3 downto 0);\r
+\r
+signal raw_buf_full : std_logic;\r
+signal eds_buf_full : std_logic;\r
+signal eds_buf_level : std_logic_vector(4 downto 0);\r
+\r
+-- regIO data bus\r
+signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+signal regio_read_enable : std_logic;\r
+signal regio_write_enable : std_logic;\r
+signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+signal regio_dataready : std_logic;\r
+signal regio_no_more_data : std_logic;\r
+signal regio_write_ack : std_logic;\r
+signal regio_unknown_addr : std_logic;\r
+signal regio_timeout : std_logic;\r
+\r
+-- common status / control registers from RegIO\r
+signal common_stat_reg : std_logic_vector(63 downto 0);\r
+signal common_ctrl_reg : std_logic_vector(63 downto 0);\r
+\r
+-- user defined "quick'n'dirty" registers\r
+signal simple_status : std_logic_vector(127 downto 0);\r
+signal simple_control : std_logic_vector(63 downto 0);\r
+\r
+-- debug signals\r
+signal test_reg : std_logic_vector(31 downto 0);\r
+signal trbrich_debug : std_logic_vector(63 downto 0);\r
+signal trgctrl_debug : std_logic_vector(63 downto 0);\r
+signal slave_debug : std_logic_vector(63 downto 0);\r
+signal fifo_debug : std_logic_vector(63 downto 0);\r
+signal raw_buf_debug : std_logic_vector(63 downto 0);\r
+\r
+-- EDS / BUFFER signals (raw buf -> ped corr)\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_avail : std_logic;\r
+signal eds_done : std_logic;\r
+signal buf_addr : std_logic_vector(6 downto 0);\r
+signal buf_done : std_logic;\r
+signal buf_tick : std_logic_vector(15 downto 0);\r
+signal buf_start : std_logic_vector(15 downto 0);\r
+signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging!\r
+\r
+type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
+signal buf_data : reg_38bit_t;\r
+\r
+signal thr_addr : std_logic_vector(6 downto 0);\r
+type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal thr_data : reg_18bit_t;\r
+signal ped_data : reg_18bit_t;\r
+\r
+-- FIFO / DHDR signals (ped corr -> ipu stage)\r
+signal dhdr_data : std_logic_vector(31 downto 0);\r
+signal dhdr_length : std_logic_vector(15 downto 0);\r
+signal dhdr_store : std_logic;\r
+signal dhdr_buf_full : std_logic;\r
+\r
+signal fifo_start : std_logic;\r
+signal fifo_done : std_logic;\r
+signal fifo_we : std_logic_vector(15 downto 0);\r
+signal fifo_space_req : std_logic_vector(11 downto 0);\r
+type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
+signal fifo_data : reg_40bit_t;\r
+\r
+-- APV control / status signals\r
+type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+signal adc_ctrl_reg : reg_16bit_t;\r
+signal adc_stat_reg : reg_16bit_t;\r
+\r
+signal debug : std_logic_vector(42 downto 0);\r
+signal debug_q : std_logic_vector(42 downto 0);\r
+signal debug_qq : std_logic_vector(42 downto 0);\r
+signal debug_clk : std_logic;\r
\r
- -- LVL1 application interface\r
- signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
- signal lvl1_trg_received : std_logic;\r
- signal lvl1_trg_number : std_logic_vector(15 downto 0);\r
- signal lvl1_trg_code : std_logic_vector(7 downto 0);\r
- signal lvl1_trg_information : std_logic_vector(23 downto 0);\r
- signal lvl1_error_pattern : std_logic_vector(31 downto 0);\r
- signal lvl1_trg_release : std_logic;\r
- signal lvl1_trg_missing : std_logic;\r
- signal timing_trg_found : std_logic;\r
-\r
- -- IPU application interface\r
- signal ipu_number : std_logic_vector(15 downto 0);\r
- signal ipu_information : std_logic_vector(7 downto 0);\r
- signal ipu_start_readout : std_logic;\r
- signal ipu_data : std_logic_vector(31 downto 0);\r
- signal ipu_dataready : std_logic;\r
- signal ipu_readout_finished : std_logic;\r
- signal ipu_read : std_logic;\r
- signal ipu_length : std_logic_vector(15 downto 0);\r
- signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
-\r
- signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
- signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
-\r
- -- ADC signals\r
- type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
- signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain\r
- signal adc_data : reg_12bit_t; -- common APV clock domain\r
-\r
- signal adc1_testdata : std_logic_vector(11 downto 0);\r
- signal adc0_testdata : std_logic_vector(11 downto 0);\r
- signal adc1_select : std_logic_vector(2 downto 0);\r
- signal adc0_select : std_logic_vector(2 downto 0);\r
-\r
- -- input synchronizing\r
- signal bp_sector_q : std_logic_vector(3 downto 0);\r
- signal bp_sector_qq : std_logic_vector(3 downto 0);\r
- signal bp_module_q : std_logic_vector(3 downto 0);\r
- signal bp_module_qq : std_logic_vector(3 downto 0);\r
-\r
- signal lsm_state_bits : std_logic_vector(3 downto 0);\r
- signal reset_by_trb : std_logic;\r
- signal global_sync_reset : std_logic;\r
-\r
- signal adc0_iodelay : std_logic_vector(3 downto 0);\r
- signal adc1_iodelay : std_logic_vector(3 downto 0);\r
-\r
-\r
-\r
--- Components\r
- -- are now in adcmv2_components.vhd\r
+-- LVL1 application interface\r
+signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
+signal lvl1_trg_received : std_logic;\r
+signal lvl1_trg_number : std_logic_vector(15 downto 0);\r
+signal lvl1_trg_code : std_logic_vector(7 downto 0);\r
+signal lvl1_trg_information : std_logic_vector(23 downto 0);\r
+signal lvl1_error_pattern : std_logic_vector(31 downto 0);\r
+signal lvl1_trg_release : std_logic;\r
+signal lvl1_trg_missing : std_logic;\r
+signal lvl1_int_trg_number : std_logic_vector(15 downto 0);\r
+signal lvl1_int_trg_update : std_logic;\r
+signal timing_trg_found : std_logic;\r
+\r
+-- IPU application interface\r
+signal ipu_number : std_logic_vector(15 downto 0);\r
+signal ipu_information : std_logic_vector(7 downto 0);\r
+signal ipu_start_readout : std_logic;\r
+signal ipu_data : std_logic_vector(31 downto 0);\r
+signal ipu_dataready : std_logic;\r
+signal ipu_readout_finished : std_logic;\r
+signal ipu_read : std_logic;\r
+signal ipu_length : std_logic_vector(15 downto 0);\r
+signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
+\r
+signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
+signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
+\r
+-- ADC signals\r
+type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain\r
+signal adc_data : reg_12bit_t; -- common APV clock domain\r
+\r
+signal adc1_testdata : std_logic_vector(11 downto 0);\r
+signal adc0_testdata : std_logic_vector(11 downto 0);\r
+signal adc1_select : std_logic_vector(2 downto 0);\r
+signal adc0_select : std_logic_vector(2 downto 0);\r
+\r
+-- input synchronizing\r
+signal bp_sector_q : std_logic_vector(3 downto 0);\r
+signal bp_sector_qq : std_logic_vector(3 downto 0);\r
+signal bp_module_q : std_logic_vector(3 downto 0);\r
+signal bp_module_qq : std_logic_vector(3 downto 0);\r
+\r
+signal lsm_state_bits : std_logic_vector(3 downto 0);\r
+signal reset_by_trb : std_logic;\r
+signal global_sync_reset : std_logic;\r
+\r
+signal adc0_iodelay : std_logic_vector(3 downto 0);\r
+signal adc1_iodelay : std_logic_vector(3 downto 0);\r
+\r
\r
begin\r
\r
-- Reset handler / spike surpression --\r
----------------------------------------\r
THE_RESET_HANDLER: reset_handler\r
-port map( CLEAR_IN => async_reset,\r
- RESET_IN => '0',\r
- CLK_IN => sysclk,\r
- TRB_RESET_IN => reset_by_trb,\r
- RESET_OUT => global_sync_reset,\r
- DEBUG_OUT => open\r
- );\r
+port map( \r
+ CLEAR_IN => async_reset,\r
+ RESET_IN => '0',\r
+ CLK_IN => sysclk,\r
+ TRB_RESET_IN => reset_by_trb,\r
+ RESET_OUT => global_sync_reset,\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
----------------------------------------\r
-- 100MHz PLL, generating 40MHz and phase shifted 40MHz\r
THE_40M_PLL: PLL_40M\r
-port map( CLK => clk100m,\r
- RESET => clk40m_reset,\r
- DPAMODE => '1', -- dynamic control \r
- DPHASE0 => ctrl_pll(0),\r
- DPHASE1 => ctrl_pll(1),\r
- DPHASE2 => ctrl_pll(2),\r
- DPHASE3 => ctrl_pll(3),\r
- CLKOP => clk_apv, -- fixed phase, used for logic \r
- CLKOS => clk_adc, -- phase adjustable, for ODDRXC only\r
- LOCK => clk40m_locked\r
- );\r
+port map( \r
+ CLK => clk100m,\r
+ RESET => clk40m_reset,\r
+ DPAMODE => '1', -- dynamic control \r
+ DPHASE0 => ctrl_pll(0),\r
+ DPHASE1 => ctrl_pll(1),\r
+ DPHASE2 => ctrl_pll(2),\r
+ DPHASE3 => ctrl_pll(3),\r
+ CLKOP => clk_apv, -- fixed phase, used for logic \r
+ CLKOS => clk_adc, -- phase adjustable, for ODDRXC only\r
+ LOCK => clk40m_locked\r
+);\r
clk40m_reset <= ctrl_pll(7);\r
\r
-- 100MHz DLL, used for clock injection delay removal\r
THE_100M_DLL: dll_100m\r
-port map( CLK => clk100m,\r
- RESETN => '1',\r
- ALUHOLD => '0',\r
- CLKOP => sysclk,\r
- CLKOS => open,\r
- LOCK => clk100m_locked\r
- );\r
+port map( \r
+ CLK => clk100m,\r
+ RESETN => '1',\r
+ ALUHOLD => '0',\r
+ CLKOP => sysclk,\r
+ CLKOS => open,\r
+ LOCK => clk100m_locked\r
+);\r
\r
\r
----------------------------------------\r
-- TRB endpoint --\r
----------------------------------------\r
THE_RICH_TRB: rich_trb\r
-port map( CLK100M_IN => clk100m, -- SerDes exclusive clock\r
- SYSCLK_IN => sysclk, -- fabric clock\r
- RESET_IN => global_sync_reset,\r
- SD_RXD_P_IN => hdinp2,\r
- SD_RXD_N_IN => hdinn2,\r
- SD_TXD_P_OUT => hdoutp2, \r
- SD_TXD_N_OUT => hdoutn2,\r
- SD_PRESENT_IN => sd_present,\r
- SD_TXDIS_OUT => sd_txdis,\r
- SD_LOS_IN => sd_los,\r
- ONEWIRE_INOUT => adcm_onewire,\r
- -- common regIO status / control registers\r
- COMMON_STAT_REG_IN => common_stat_reg,\r
- COMMON_CTRL_REG_OUT => common_ctrl_reg,\r
- -- status register input to regIO / control register output from regIO\r
- CONTROL_OUT => simple_control,\r
- STATUS_IN => simple_status,\r
- -- LVL1 signals\r
- LVL1_TRG_TYPE_OUT => lvl1_trg_type,\r
- LVL1_TRG_RECEIVED_OUT => lvl1_trg_received,\r
- LVL1_TRG_NUMBER_OUT => lvl1_trg_number,\r
- LVL1_TRG_CODE_OUT => lvl1_trg_code,\r
- LVL1_TRG_INFORMATION_OUT => lvl1_trg_information,\r
- LVL1_ERROR_PATTERN_IN => lvl1_error_pattern,\r
- LVL1_TRG_RELEASE_IN => lvl1_trg_release,\r
- TIMING_TRG_FOUND_IN => timing_trg_found,\r
- -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
- IPU_NUMBER_OUT => ipu_number,\r
- IPU_INFORMATION_OUT => ipu_information,\r
- IPU_START_READOUT_OUT => ipu_start_readout,\r
- IPU_DATA_IN => ipu_data,\r
- IPU_DATAREADY_IN => ipu_dataready,\r
- IPU_READOUT_FINISHED_IN => ipu_readout_finished,\r
- IPU_READ_OUT => ipu_read,\r
- IPU_LENGTH_IN => ipu_length,\r
- IPU_ERROR_PATTERN_IN => ipu_error_pattern,\r
- -- regIO bus\r
- REGIO_ADDR_OUT => regio_addr,\r
- REGIO_READ_ENABLE_OUT => regio_read_enable,\r
- REGIO_WRITE_ENABLE_OUT => regio_write_enable,\r
- REGIO_DATA_OUT => regio_data_wr,\r
- REGIO_DATA_IN => regio_data_rd,\r
- REGIO_DATAREADY_IN => regio_dataready,\r
- REGIO_NO_MORE_DATA_IN => regio_no_more_data,\r
- REGIO_WRITE_ACK_IN => regio_write_ack,\r
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr,\r
- REGIO_TIMEOUT_OUT => regio_timeout,\r
- -- status LEDs\r
- LED_LINK_STAT => fpga_led_link,\r
- LED_LINK_TXD => fpga_led_txd,\r
- LED_LINK_RXD => fpga_led_rxd,\r
- LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits\r
- RESET_OUT => reset_by_trb,\r
- DEBUG => trbrich_debug --open \r
- );\r
+port map( \r
+ CLK100M_IN => clk100m, -- SerDes exclusive clock\r
+ SYSCLK_IN => sysclk, -- fabric clock\r
+ RESET_IN => global_sync_reset,\r
+ SD_RXD_P_IN => hdinp2,\r
+ SD_RXD_N_IN => hdinn2,\r
+ SD_TXD_P_OUT => hdoutp2, \r
+ SD_TXD_N_OUT => hdoutn2,\r
+ SD_PRESENT_IN => sd_present,\r
+ SD_TXDIS_OUT => sd_txdis,\r
+ SD_LOS_IN => sd_los,\r
+ ONEWIRE_INOUT => adcm_onewire,\r
+ -- common regIO status / control registers\r
+ COMMON_STAT_REG_IN => common_stat_reg,\r
+ COMMON_CTRL_REG_OUT => common_ctrl_reg,\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT => simple_control,\r
+ STATUS_IN => simple_status,\r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT => lvl1_trg_type,\r
+ LVL1_TRG_RECEIVED_OUT => lvl1_trg_received,\r
+ LVL1_TRG_NUMBER_OUT => lvl1_trg_number,\r
+ LVL1_TRG_CODE_OUT => lvl1_trg_code,\r
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information,\r
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern,\r
+ LVL1_TRG_RELEASE_IN => lvl1_trg_release,\r
+ LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter\r
+ LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter\r
+ TIMING_TRG_FOUND_IN => timing_trg_found,\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT => ipu_number,\r
+ IPU_INFORMATION_OUT => ipu_information,\r
+ IPU_START_READOUT_OUT => ipu_start_readout,\r
+ IPU_DATA_IN => ipu_data,\r
+ IPU_DATAREADY_IN => ipu_dataready,\r
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished,\r
+ IPU_READ_OUT => ipu_read,\r
+ IPU_LENGTH_IN => ipu_length,\r
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern,\r
+ -- regIO bus\r
+ REGIO_ADDR_OUT => regio_addr,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable,\r
+ REGIO_DATA_OUT => regio_data_wr,\r
+ REGIO_DATA_IN => regio_data_rd,\r
+ REGIO_DATAREADY_IN => regio_dataready,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr,\r
+ REGIO_TIMEOUT_OUT => regio_timeout,\r
+ -- status LEDs\r
+ LED_LINK_STAT => fpga_led_link,\r
+ LED_LINK_TXD => fpga_led_txd,\r
+ LED_LINK_RXD => fpga_led_rxd,\r
+ LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits\r
+ RESET_OUT => reset_by_trb,\r
+ DEBUG => trbrich_debug --open \r
+);\r
+\r
+-- common control register bit definitions\r
+-- [31:24] ---\r
+-- [23:16] fake timing trigger\r
+-- [15] reboot FPGA\r
+-- [14:11] --- \r
+-- [10] reset sequence counter\r
+-- [9:4] ---\r
+-- [3] master reset, reset the whole endpoint\r
+-- [2] empty IPU chain, reset IPU logic\r
+-- [1] reset trigger logic\r
+-- [0] reset frontends\r
\r
-- LVL1 error pattern, to be sent back to CTS with each trigger\r
-lvl1_error_pattern(31 downto 22) <= (others => '0');\r
+lvl1_error_pattern(31 downto 23) <= (others => '0');\r
+lvl1_error_pattern(22) <= '0'; -- not configured\r
lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
lvl1_error_pattern(20) <= '0'; -- buffers half full\r
lvl1_error_pattern(19 downto 18) <= (others => '0');\r
-lvl1_error_pattern(17) <= '0'; -- lvl1_trg_missing; -- missing timing trigger\r
+lvl1_error_pattern(17) <= '0'; -- missing timing trigger (done by Jan)\r
lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
lvl1_error_pattern(15 downto 0) <= (others => '0'); \r
\r
ena_lvds(5) <= adc_on(1) or lvds_on(1);\r
ena_lvds(6) <= adc_on(7) or lvds_on(7);\r
ena_lvds(7) <= adc_on(0) or lvds_on(0);\r
- \r
+ \r
enb_lvds(0) <= adc_on(13) or lvds_on(13);\r
enb_lvds(1) <= adc_on(10) or lvds_on(10);\r
enb_lvds(2) <= adc_on(12) or lvds_on(12);\r
-- internal slave bus -> slow control --\r
----------------------------------------\r
THE_SLAVE_BUS: slave_bus\r
-port map( CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- -- RegIO signals\r
- REGIO_ADDR_IN => regio_addr,\r
- REGIO_DATA_IN => regio_data_wr,\r
- REGIO_DATA_OUT => regio_data_rd,\r
- REGIO_READ_ENABLE_IN => regio_read_enable,\r
- REGIO_WRITE_ENABLE_IN => regio_write_enable,\r
- REGIO_TIMEOUT_IN => regio_timeout,\r
- REGIO_DATAREADY_OUT => regio_dataready,\r
- REGIO_WRITE_ACK_OUT => regio_write_ack,\r
- REGIO_NO_MORE_DATA_OUT => regio_no_more_data,\r
- REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr,\r
- -- I2C connections\r
- SDA_IN => apv_sda_in,\r
- SDA_OUT => apv_sda_out,\r
- SCL_IN => apv_scl_in,\r
- SCL_OUT => apv_scl_out,\r
- -- 1Wire connections\r
- ONEWIRE_START_IN => '0', -- not used yet\r
- ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0),\r
- ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0),\r
- BP_ONEWIRE_INOUT => bp_onewire,\r
- -- SPI connections\r
- SPI_CS_OUT => u_spi_cs,\r
- SPI_SCK_OUT => u_spi_sck,\r
- SPI_SDI_IN => u_spi_sdo,\r
- SPI_SDO_OUT => u_spi_sdi,\r
- -- ADC 0 SPI connections\r
- SPI_ADC0_CS_OUT => adc0_cs,\r
- SPI_ADC0_SCK_OUT => adc0_sck,\r
- SPI_ADC0_SDO_OUT => adc0_sdi,\r
- ADC0_PLL_LOCKED_IN => adc0_valid,\r
- ADC0_PD_OUT => adc0_powerdown,\r
- ADC0_RST_OUT => adc0_reset,\r
- ADC0_DEL_OUT => adc0_iodelay,\r
- ADC0_CLK_IN => clk_apv,\r
- ADC0_DATA_IN => adc0_testdata,\r
- ADC0_SEL_OUT => adc0_select,\r
- APV0_RST_OUT => apv0_reset,\r
- -- ADC 0 SPI connections\r
- SPI_ADC1_CS_OUT => adc1_cs,\r
- SPI_ADC1_SCK_OUT => adc1_sck,\r
- SPI_ADC1_SDO_OUT => adc1_sdi,\r
- ADC1_PLL_LOCKED_IN => adc1_valid,\r
- ADC1_PD_OUT => adc1_powerdown,\r
- ADC1_RST_OUT => adc1_reset,\r
- ADC1_DEL_OUT => adc1_iodelay,\r
- ADC1_CLK_IN => clk_apv,\r
- ADC1_DATA_IN => adc1_testdata,\r
- ADC1_SEL_OUT => adc1_select,\r
- APV1_RST_OUT => apv1_reset,\r
- -- backplane identifier\r
- BACKPLANE_IN => bp_module_qq(2 downto 0),\r
- -- pedestal interface\r
- PED_ADDR_IN => buf_addr,\r
- PED_DATA_0_OUT => ped_data(0),\r
- PED_DATA_1_OUT => ped_data(1),\r
- PED_DATA_2_OUT => ped_data(2),\r
- PED_DATA_3_OUT => ped_data(3),\r
- PED_DATA_4_OUT => ped_data(4),\r
- PED_DATA_5_OUT => ped_data(5),\r
- PED_DATA_6_OUT => ped_data(6),\r
- PED_DATA_7_OUT => ped_data(7),\r
- PED_DATA_8_OUT => ped_data(8),\r
- PED_DATA_9_OUT => ped_data(9),\r
- PED_DATA_10_OUT => ped_data(10),\r
- PED_DATA_11_OUT => ped_data(11),\r
- PED_DATA_12_OUT => ped_data(12),\r
- PED_DATA_13_OUT => ped_data(13),\r
- PED_DATA_14_OUT => ped_data(14),\r
- PED_DATA_15_OUT => ped_data(15),\r
- -- threshold interface\r
- THR_ADDR_IN => thr_addr,\r
- THR_DATA_0_OUT => thr_data(0),\r
- THR_DATA_1_OUT => thr_data(1),\r
- THR_DATA_2_OUT => thr_data(2),\r
- THR_DATA_3_OUT => thr_data(3),\r
- THR_DATA_4_OUT => thr_data(4),\r
- THR_DATA_5_OUT => thr_data(5),\r
- THR_DATA_6_OUT => thr_data(6),\r
- THR_DATA_7_OUT => thr_data(7),\r
- THR_DATA_8_OUT => thr_data(8),\r
- THR_DATA_9_OUT => thr_data(9),\r
- THR_DATA_10_OUT => thr_data(10),\r
- THR_DATA_11_OUT => thr_data(11),\r
- THR_DATA_12_OUT => thr_data(12),\r
- THR_DATA_13_OUT => thr_data(13),\r
- THR_DATA_14_OUT => thr_data(14),\r
- THR_DATA_15_OUT => thr_data(15),\r
- -- APV control / status\r
- CTRL_0_OUT => adc_ctrl_reg(0),\r
- CTRL_1_OUT => adc_ctrl_reg(1),\r
- CTRL_2_OUT => adc_ctrl_reg(2),\r
- CTRL_3_OUT => adc_ctrl_reg(3),\r
- CTRL_4_OUT => adc_ctrl_reg(4),\r
- CTRL_5_OUT => adc_ctrl_reg(5),\r
- CTRL_6_OUT => adc_ctrl_reg(6),\r
- CTRL_7_OUT => adc_ctrl_reg(7),\r
- CTRL_8_OUT => adc_ctrl_reg(8),\r
- CTRL_9_OUT => adc_ctrl_reg(9),\r
- CTRL_10_OUT => adc_ctrl_reg(10),\r
- CTRL_11_OUT => adc_ctrl_reg(11),\r
- CTRL_12_OUT => adc_ctrl_reg(12),\r
- CTRL_13_OUT => adc_ctrl_reg(13),\r
- CTRL_14_OUT => adc_ctrl_reg(14),\r
- CTRL_15_OUT => adc_ctrl_reg(15),\r
- STAT_0_IN => adc_stat_reg(0),\r
- STAT_1_IN => adc_stat_reg(1),\r
- STAT_2_IN => adc_stat_reg(2),\r
- STAT_3_IN => adc_stat_reg(3),\r
- STAT_4_IN => adc_stat_reg(4),\r
- STAT_5_IN => adc_stat_reg(5),\r
- STAT_6_IN => adc_stat_reg(6),\r
- STAT_7_IN => adc_stat_reg(7),\r
- STAT_8_IN => adc_stat_reg(8),\r
- STAT_9_IN => adc_stat_reg(9),\r
- STAT_10_IN => adc_stat_reg(10),\r
- STAT_11_IN => adc_stat_reg(11),\r
- STAT_12_IN => adc_stat_reg(12),\r
- STAT_13_IN => adc_stat_reg(13),\r
- STAT_14_IN => adc_stat_reg(14),\r
- STAT_15_IN => adc_stat_reg(15),\r
- -- some control signals\r
- CTRL_LVL_OUT => ctrl_lvl,\r
- CTRL_TRG_OUT => ctrl_trg,\r
- CTRL_PLL_OUT => ctrl_pll,\r
- STATUS_PLL_IN => status_pll,\r
- -- temporary stuff \r
- TEST_REG_IN => test_reg, -- short cut \r
- TEST_REG_OUT => test_reg,\r
- -- Debug \r
- DEBUG_OUT => slave_debug, --open\r
- STAT => open\r
- ); \r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN => regio_addr,\r
+ REGIO_DATA_IN => regio_data_wr,\r
+ REGIO_DATA_OUT => regio_data_rd,\r
+ REGIO_READ_ENABLE_IN => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_IN => regio_write_enable,\r
+ REGIO_TIMEOUT_IN => regio_timeout,\r
+ REGIO_DATAREADY_OUT => regio_dataready,\r
+ REGIO_WRITE_ACK_OUT => regio_write_ack,\r
+ REGIO_NO_MORE_DATA_OUT => regio_no_more_data,\r
+ REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr,\r
+ -- I2C connections\r
+ SDA_IN => apv_sda_in,\r
+ SDA_OUT => apv_sda_out,\r
+ SCL_IN => apv_scl_in,\r
+ SCL_OUT => apv_scl_out,\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN => '0', -- not used yet\r
+ ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0),\r
+ ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0),\r
+ BP_ONEWIRE_INOUT => bp_onewire,\r
+ -- SPI connections\r
+ SPI_CS_OUT => u_spi_cs,\r
+ SPI_SCK_OUT => u_spi_sck,\r
+ SPI_SDI_IN => u_spi_sdo,\r
+ SPI_SDO_OUT => u_spi_sdi,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT => adc0_cs,\r
+ SPI_ADC0_SCK_OUT => adc0_sck,\r
+ SPI_ADC0_SDO_OUT => adc0_sdi,\r
+ ADC0_PLL_LOCKED_IN => adc0_valid,\r
+ ADC0_PD_OUT => adc0_powerdown,\r
+ ADC0_RST_OUT => adc0_reset,\r
+ ADC0_DEL_OUT => adc0_iodelay,\r
+ ADC0_CLK_IN => clk_apv,\r
+ ADC0_DATA_IN => adc0_testdata,\r
+ ADC0_SEL_OUT => adc0_select,\r
+ APV0_RST_OUT => apv0_reset,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT => adc1_cs,\r
+ SPI_ADC1_SCK_OUT => adc1_sck,\r
+ SPI_ADC1_SDO_OUT => adc1_sdi,\r
+ ADC1_PLL_LOCKED_IN => adc1_valid,\r
+ ADC1_PD_OUT => adc1_powerdown,\r
+ ADC1_RST_OUT => adc1_reset,\r
+ ADC1_DEL_OUT => adc1_iodelay,\r
+ ADC1_CLK_IN => clk_apv,\r
+ ADC1_DATA_IN => adc1_testdata,\r
+ ADC1_SEL_OUT => adc1_select,\r
+ APV1_RST_OUT => apv1_reset,\r
+ -- backplane identifier\r
+ BACKPLANE_IN => bp_module_qq(2 downto 0),\r
+ -- pedestal interface\r
+ PED_ADDR_IN => buf_addr,\r
+ PED_DATA_0_OUT => ped_data(0),\r
+ PED_DATA_1_OUT => ped_data(1),\r
+ PED_DATA_2_OUT => ped_data(2),\r
+ PED_DATA_3_OUT => ped_data(3),\r
+ PED_DATA_4_OUT => ped_data(4),\r
+ PED_DATA_5_OUT => ped_data(5),\r
+ PED_DATA_6_OUT => ped_data(6),\r
+ PED_DATA_7_OUT => ped_data(7),\r
+ PED_DATA_8_OUT => ped_data(8),\r
+ PED_DATA_9_OUT => ped_data(9),\r
+ PED_DATA_10_OUT => ped_data(10),\r
+ PED_DATA_11_OUT => ped_data(11),\r
+ PED_DATA_12_OUT => ped_data(12),\r
+ PED_DATA_13_OUT => ped_data(13),\r
+ PED_DATA_14_OUT => ped_data(14),\r
+ PED_DATA_15_OUT => ped_data(15),\r
+ -- threshold interface\r
+ THR_ADDR_IN => thr_addr,\r
+ THR_DATA_0_OUT => thr_data(0),\r
+ THR_DATA_1_OUT => thr_data(1),\r
+ THR_DATA_2_OUT => thr_data(2),\r
+ THR_DATA_3_OUT => thr_data(3),\r
+ THR_DATA_4_OUT => thr_data(4),\r
+ THR_DATA_5_OUT => thr_data(5),\r
+ THR_DATA_6_OUT => thr_data(6),\r
+ THR_DATA_7_OUT => thr_data(7),\r
+ THR_DATA_8_OUT => thr_data(8),\r
+ THR_DATA_9_OUT => thr_data(9),\r
+ THR_DATA_10_OUT => thr_data(10),\r
+ THR_DATA_11_OUT => thr_data(11),\r
+ THR_DATA_12_OUT => thr_data(12),\r
+ THR_DATA_13_OUT => thr_data(13),\r
+ THR_DATA_14_OUT => thr_data(14),\r
+ THR_DATA_15_OUT => thr_data(15),\r
+ -- APV control / status\r
+ CTRL_0_OUT => adc_ctrl_reg(0),\r
+ CTRL_1_OUT => adc_ctrl_reg(1),\r
+ CTRL_2_OUT => adc_ctrl_reg(2),\r
+ CTRL_3_OUT => adc_ctrl_reg(3),\r
+ CTRL_4_OUT => adc_ctrl_reg(4),\r
+ CTRL_5_OUT => adc_ctrl_reg(5),\r
+ CTRL_6_OUT => adc_ctrl_reg(6),\r
+ CTRL_7_OUT => adc_ctrl_reg(7),\r
+ CTRL_8_OUT => adc_ctrl_reg(8),\r
+ CTRL_9_OUT => adc_ctrl_reg(9),\r
+ CTRL_10_OUT => adc_ctrl_reg(10),\r
+ CTRL_11_OUT => adc_ctrl_reg(11),\r
+ CTRL_12_OUT => adc_ctrl_reg(12),\r
+ CTRL_13_OUT => adc_ctrl_reg(13),\r
+ CTRL_14_OUT => adc_ctrl_reg(14),\r
+ CTRL_15_OUT => adc_ctrl_reg(15),\r
+ STAT_0_IN => adc_stat_reg(0),\r
+ STAT_1_IN => adc_stat_reg(1),\r
+ STAT_2_IN => adc_stat_reg(2),\r
+ STAT_3_IN => adc_stat_reg(3),\r
+ STAT_4_IN => adc_stat_reg(4),\r
+ STAT_5_IN => adc_stat_reg(5),\r
+ STAT_6_IN => adc_stat_reg(6),\r
+ STAT_7_IN => adc_stat_reg(7),\r
+ STAT_8_IN => adc_stat_reg(8),\r
+ STAT_9_IN => adc_stat_reg(9),\r
+ STAT_10_IN => adc_stat_reg(10),\r
+ STAT_11_IN => adc_stat_reg(11),\r
+ STAT_12_IN => adc_stat_reg(12),\r
+ STAT_13_IN => adc_stat_reg(13),\r
+ STAT_14_IN => adc_stat_reg(14),\r
+ STAT_15_IN => adc_stat_reg(15),\r
+ -- some control signals\r
+ CTRL_LVL_OUT => ctrl_lvl,\r
+ CTRL_TRG_OUT => ctrl_trg,\r
+ CTRL_PLL_OUT => ctrl_pll,\r
+ STATUS_PLL_IN => status_pll,\r
+ -- temporary stuff \r
+ TEST_REG_IN => test_reg, -- short cut \r
+ TEST_REG_OUT => test_reg,\r
+ -- Debug \r
+ DEBUG_OUT => slave_debug, --open\r
+ STAT => open\r
+); \r
\r
-- PLL status register \r
status_pll(15) <= clk100m_locked;\r
-- IPU endpoint for data transport --\r
----------------------------------------\r
THE_IPU_STAGE: ipu_fifo_stage \r
-port map( CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- -- Slow control signals \r
- SECTOR_IN => bp_sector_qq(2 downto 0), \r
- MODULE_IN => bp_module_qq(2 downto 0), \r
- -- IPU channel connections \r
- IPU_NUMBER_IN => ipu_number,\r
- IPU_INFORMATION_IN => ipu_information,\r
- IPU_START_READOUT_IN => ipu_start_readout,\r
- IPU_DATA_OUT => ipu_data,\r
- IPU_DATAREADY_OUT => ipu_dataready,\r
- IPU_READOUT_FINISHED_OUT => ipu_readout_finished,\r
- IPU_READ_IN => ipu_read,\r
- IPU_LENGTH_OUT => ipu_length,\r
- IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
- LVL2_COUNTER_OUT => local_lvl2_counter,\r
- -- DHDR buffer input \r
- DHDR_DATA_IN => dhdr_data,\r
- DHDR_LENGTH_IN => dhdr_length,\r
- DHDR_STORE_IN => dhdr_store,\r
- DHDR_BUF_FULL_OUT => dhdr_buf_full,\r
- -- processed data input\r
- FIFO_START_IN => fifo_start,\r
- FIFO_0_DATA_IN => fifo_data(0),\r
- FIFO_1_DATA_IN => fifo_data(1),\r
- FIFO_2_DATA_IN => fifo_data(2),\r
- FIFO_3_DATA_IN => fifo_data(3),\r
- FIFO_4_DATA_IN => fifo_data(4),\r
- FIFO_5_DATA_IN => fifo_data(5),\r
- FIFO_6_DATA_IN => fifo_data(6),\r
- FIFO_7_DATA_IN => fifo_data(7),\r
- FIFO_8_DATA_IN => fifo_data(8),\r
- FIFO_9_DATA_IN => fifo_data(9),\r
- FIFO_10_DATA_IN => fifo_data(10),\r
- FIFO_11_DATA_IN => fifo_data(11),\r
- FIFO_12_DATA_IN => fifo_data(12),\r
- FIFO_13_DATA_IN => fifo_data(13),\r
- FIFO_14_DATA_IN => fifo_data(14),\r
- FIFO_15_DATA_IN => fifo_data(15),\r
- FIFO_WE_IN => fifo_we,\r
- FIFO_DONE_IN => fifo_done,\r
- -- Debug signals\r
- DBG_BSM_OUT => open,\r
- DBG_OUT => fifo_debug --open\r
- );\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ -- Slow control signals \r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ MODULE_IN => bp_module_qq(2 downto 0), \r
+ -- IPU channel connections \r
+ IPU_NUMBER_IN => ipu_number,\r
+ IPU_INFORMATION_IN => ipu_information,\r
+ IPU_START_READOUT_IN => ipu_start_readout,\r
+ IPU_DATA_OUT => ipu_data,\r
+ IPU_DATAREADY_OUT => ipu_dataready,\r
+ IPU_READOUT_FINISHED_OUT => ipu_readout_finished,\r
+ IPU_READ_IN => ipu_read,\r
+ IPU_LENGTH_OUT => ipu_length,\r
+ IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
+ LVL2_COUNTER_OUT => local_lvl2_counter,\r
+ -- DHDR buffer input \r
+ DHDR_DATA_IN => dhdr_data,\r
+ DHDR_LENGTH_IN => dhdr_length,\r
+ DHDR_STORE_IN => dhdr_store,\r
+ DHDR_BUF_FULL_OUT => dhdr_buf_full,\r
+ -- processed data input\r
+ FIFO_SPACE_REQ_IN => fifo_space_req,\r
+ FIFO_START_IN => fifo_start,\r
+ FIFO_0_DATA_IN => fifo_data(0),\r
+ FIFO_1_DATA_IN => fifo_data(1),\r
+ FIFO_2_DATA_IN => fifo_data(2),\r
+ FIFO_3_DATA_IN => fifo_data(3),\r
+ FIFO_4_DATA_IN => fifo_data(4),\r
+ FIFO_5_DATA_IN => fifo_data(5),\r
+ FIFO_6_DATA_IN => fifo_data(6),\r
+ FIFO_7_DATA_IN => fifo_data(7),\r
+ FIFO_8_DATA_IN => fifo_data(8),\r
+ FIFO_9_DATA_IN => fifo_data(9),\r
+ FIFO_10_DATA_IN => fifo_data(10),\r
+ FIFO_11_DATA_IN => fifo_data(11),\r
+ FIFO_12_DATA_IN => fifo_data(12),\r
+ FIFO_13_DATA_IN => fifo_data(13),\r
+ FIFO_14_DATA_IN => fifo_data(14),\r
+ FIFO_15_DATA_IN => fifo_data(15),\r
+ FIFO_WE_IN => fifo_we,\r
+ FIFO_DONE_IN => fifo_done,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => fifo_debug --open\r
+);\r
\r
\r
----------------------------------------\r
-- Data processing unit --\r
----------------------------------------\r
THE_PED_CORR_STAGE: ped_corr_ctrl\r
-port map( CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- EDS_DATA_IN => eds_data,\r
- EDS_AVAIL_IN => eds_avail,\r
- EDS_DONE_OUT => eds_done,\r
- EVT_TYPE_IN => b"000", -- BUG\r
- -- DHDR information -- to next stage\r
- DHDR_DATA_OUT => dhdr_data,\r
- DHDR_LENGTH_OUT => dhdr_length,\r
- DHDR_STORE_OUT => dhdr_store,\r
- DHDR_BUF_FULL_IN => dhdr_buf_full,\r
- -- data buffers -- from raw_buf_stage\r
- BUF_ADDR_OUT => buf_addr,\r
- BUF_DONE_OUT => buf_done,\r
- BUF_TICK_IN => buf_tick,\r
- BUF_START_IN => buf_start,\r
- -- raw data\r
- BUF_0_DATA_IN => buf_data(0),\r
- BUF_1_DATA_IN => buf_data(1),\r
- BUF_2_DATA_IN => buf_data(2),\r
- BUF_3_DATA_IN => buf_data(3),\r
- BUF_4_DATA_IN => buf_data(4),\r
- BUF_5_DATA_IN => buf_data(5),\r
- BUF_6_DATA_IN => buf_data(6),\r
- BUF_7_DATA_IN => buf_data(7),\r
- BUF_8_DATA_IN => buf_data(8),\r
- BUF_9_DATA_IN => buf_data(9),\r
- BUF_10_DATA_IN => buf_data(10),\r
- BUF_11_DATA_IN => buf_data(11),\r
- BUF_12_DATA_IN => buf_data(12),\r
- BUF_13_DATA_IN => buf_data(13),\r
- BUF_14_DATA_IN => buf_data(14),\r
- BUF_15_DATA_IN => buf_data(15),\r
- -- Pedestal data \r
- PED_ADDR_OUT => open, -- BUGBUGBUG\r
- PED_0_DATA_IN => ped_data(0),\r
- PED_1_DATA_IN => ped_data(1),\r
- PED_2_DATA_IN => ped_data(2),\r
- PED_3_DATA_IN => ped_data(3),\r
- PED_4_DATA_IN => ped_data(4),\r
- PED_5_DATA_IN => ped_data(5),\r
- PED_6_DATA_IN => ped_data(6),\r
- PED_7_DATA_IN => ped_data(7),\r
- PED_8_DATA_IN => ped_data(8),\r
- PED_9_DATA_IN => ped_data(9),\r
- PED_10_DATA_IN => ped_data(10),\r
- PED_11_DATA_IN => ped_data(11),\r
- PED_12_DATA_IN => ped_data(12),\r
- PED_13_DATA_IN => ped_data(13),\r
- PED_14_DATA_IN => ped_data(14),\r
- PED_15_DATA_IN => ped_data(15),\r
- -- Threshold data\r
- THR_ADDR_OUT => thr_addr,\r
- THR_0_DATA_IN => thr_data(0),\r
- THR_1_DATA_IN => thr_data(1),\r
- THR_2_DATA_IN => thr_data(2),\r
- THR_3_DATA_IN => thr_data(3),\r
- THR_4_DATA_IN => thr_data(4),\r
- THR_5_DATA_IN => thr_data(5),\r
- THR_6_DATA_IN => thr_data(6),\r
- THR_7_DATA_IN => thr_data(7),\r
- THR_8_DATA_IN => thr_data(8),\r
- THR_9_DATA_IN => thr_data(9),\r
- THR_10_DATA_IN => thr_data(10),\r
- THR_11_DATA_IN => thr_data(11),\r
- THR_12_DATA_IN => thr_data(12),\r
- THR_13_DATA_IN => thr_data(13),\r
- THR_14_DATA_IN => thr_data(14),\r
- THR_15_DATA_IN => thr_data(15),\r
- -- processed data\r
- FIFO_START_OUT => fifo_start,\r
- FIFO_0_DATA_OUT => fifo_data(0),\r
- FIFO_1_DATA_OUT => fifo_data(1),\r
- FIFO_2_DATA_OUT => fifo_data(2),\r
- FIFO_3_DATA_OUT => fifo_data(3),\r
- FIFO_4_DATA_OUT => fifo_data(4),\r
- FIFO_5_DATA_OUT => fifo_data(5),\r
- FIFO_6_DATA_OUT => fifo_data(6),\r
- FIFO_7_DATA_OUT => fifo_data(7),\r
- FIFO_8_DATA_OUT => fifo_data(8),\r
- FIFO_9_DATA_OUT => fifo_data(9),\r
- FIFO_10_DATA_OUT => fifo_data(10),\r
- FIFO_11_DATA_OUT => fifo_data(11),\r
- FIFO_12_DATA_OUT => fifo_data(12),\r
- FIFO_13_DATA_OUT => fifo_data(13),\r
- FIFO_14_DATA_OUT => fifo_data(14),\r
- FIFO_15_DATA_OUT => fifo_data(15),\r
- FIFO_WE_OUT => fifo_we,\r
- FIFO_DONE_OUT => fifo_done,\r
- -- Debug signals\r
- DBG_BSM_OUT => open,\r
- DBG_OUT => open\r
- );\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ EDS_DATA_IN => eds_data,\r
+ EDS_AVAIL_IN => eds_avail,\r
+ EDS_DONE_OUT => eds_done,\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT => dhdr_data,\r
+ DHDR_LENGTH_OUT => dhdr_length,\r
+ DHDR_STORE_OUT => dhdr_store,\r
+ DHDR_BUF_FULL_IN => dhdr_buf_full,\r
+ FIFO_SPACE_REQ_OUT => fifo_space_req, \r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT => buf_addr,\r
+ BUF_DONE_OUT => buf_done,\r
+ BUF_TICK_IN => buf_tick,\r
+ BUF_START_IN => buf_start,\r
+ -- raw data\r
+ BUF_0_DATA_IN => buf_data(0),\r
+ BUF_1_DATA_IN => buf_data(1),\r
+ BUF_2_DATA_IN => buf_data(2),\r
+ BUF_3_DATA_IN => buf_data(3),\r
+ BUF_4_DATA_IN => buf_data(4),\r
+ BUF_5_DATA_IN => buf_data(5),\r
+ BUF_6_DATA_IN => buf_data(6),\r
+ BUF_7_DATA_IN => buf_data(7),\r
+ BUF_8_DATA_IN => buf_data(8),\r
+ BUF_9_DATA_IN => buf_data(9),\r
+ BUF_10_DATA_IN => buf_data(10),\r
+ BUF_11_DATA_IN => buf_data(11),\r
+ BUF_12_DATA_IN => buf_data(12),\r
+ BUF_13_DATA_IN => buf_data(13),\r
+ BUF_14_DATA_IN => buf_data(14),\r
+ BUF_15_DATA_IN => buf_data(15),\r
+ -- Pedestal data \r
+ PED_ADDR_OUT => open, -- BUGBUGBUG\r
+ PED_0_DATA_IN => ped_data(0),\r
+ PED_1_DATA_IN => ped_data(1),\r
+ PED_2_DATA_IN => ped_data(2),\r
+ PED_3_DATA_IN => ped_data(3),\r
+ PED_4_DATA_IN => ped_data(4),\r
+ PED_5_DATA_IN => ped_data(5),\r
+ PED_6_DATA_IN => ped_data(6),\r
+ PED_7_DATA_IN => ped_data(7),\r
+ PED_8_DATA_IN => ped_data(8),\r
+ PED_9_DATA_IN => ped_data(9),\r
+ PED_10_DATA_IN => ped_data(10),\r
+ PED_11_DATA_IN => ped_data(11),\r
+ PED_12_DATA_IN => ped_data(12),\r
+ PED_13_DATA_IN => ped_data(13),\r
+ PED_14_DATA_IN => ped_data(14),\r
+ PED_15_DATA_IN => ped_data(15),\r
+ -- Threshold data\r
+ THR_ADDR_OUT => thr_addr,\r
+ THR_0_DATA_IN => thr_data(0),\r
+ THR_1_DATA_IN => thr_data(1),\r
+ THR_2_DATA_IN => thr_data(2),\r
+ THR_3_DATA_IN => thr_data(3),\r
+ THR_4_DATA_IN => thr_data(4),\r
+ THR_5_DATA_IN => thr_data(5),\r
+ THR_6_DATA_IN => thr_data(6),\r
+ THR_7_DATA_IN => thr_data(7),\r
+ THR_8_DATA_IN => thr_data(8),\r
+ THR_9_DATA_IN => thr_data(9),\r
+ THR_10_DATA_IN => thr_data(10),\r
+ THR_11_DATA_IN => thr_data(11),\r
+ THR_12_DATA_IN => thr_data(12),\r
+ THR_13_DATA_IN => thr_data(13),\r
+ THR_14_DATA_IN => thr_data(14),\r
+ THR_15_DATA_IN => thr_data(15),\r
+ -- processed data\r
+ FIFO_START_OUT => fifo_start,\r
+ FIFO_0_DATA_OUT => fifo_data(0),\r
+ FIFO_1_DATA_OUT => fifo_data(1),\r
+ FIFO_2_DATA_OUT => fifo_data(2),\r
+ FIFO_3_DATA_OUT => fifo_data(3),\r
+ FIFO_4_DATA_OUT => fifo_data(4),\r
+ FIFO_5_DATA_OUT => fifo_data(5),\r
+ FIFO_6_DATA_OUT => fifo_data(6),\r
+ FIFO_7_DATA_OUT => fifo_data(7),\r
+ FIFO_8_DATA_OUT => fifo_data(8),\r
+ FIFO_9_DATA_OUT => fifo_data(9),\r
+ FIFO_10_DATA_OUT => fifo_data(10),\r
+ FIFO_11_DATA_OUT => fifo_data(11),\r
+ FIFO_12_DATA_OUT => fifo_data(12),\r
+ FIFO_13_DATA_OUT => fifo_data(13),\r
+ FIFO_14_DATA_OUT => fifo_data(14),\r
+ FIFO_15_DATA_OUT => fifo_data(15),\r
+ FIFO_WE_OUT => fifo_we,\r
+ FIFO_DONE_OUT => fifo_done,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => open\r
+);\r
\r
\r
------------------------------------------\r
-- Raw data processing and storage unit --\r
------------------------------------------\r
THE_RAW_BUF_STAGE: raw_buf_stage_new\r
-port map( CLK_IN => sysclk,\r
- CLK_APV_IN => clk_apv,\r
- RESET_IN => reset_by_trb,\r
- -- trigger related signals\r
- APV_RESET_IN => apv_reset, -- (100MHz clock)\r
- APV_SYNC_IN => apv_sync, -- (40MHz APV clock)\r
- APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock)\r
- -- ADC0 signals\r
- ADC0_VALID_IN => adc0_valid,\r
- ADC0_0_DATA_IN => adc_data(0),\r
- ADC0_1_DATA_IN => adc_data(1),\r
- ADC0_2_DATA_IN => adc_data(2),\r
- ADC0_3_DATA_IN => adc_data(3),\r
- ADC0_4_DATA_IN => adc_data(4),\r
- ADC0_5_DATA_IN => adc_data(5),\r
- ADC0_6_DATA_IN => adc_data(6),\r
- ADC0_7_DATA_IN => adc_data(7),\r
- -- ADC1 signals\r
- ADC1_VALID_IN => adc1_valid,\r
- ADC1_0_DATA_IN => adc_data(8),\r
- ADC1_1_DATA_IN => adc_data(9),\r
- ADC1_2_DATA_IN => adc_data(10),\r
- ADC1_3_DATA_IN => adc_data(11),\r
- ADC1_4_DATA_IN => adc_data(12),\r
- ADC1_5_DATA_IN => adc_data(13),\r
- ADC1_6_DATA_IN => adc_data(14),\r
- ADC1_7_DATA_IN => adc_data(15),\r
- -- Slow control registers\r
- MAX_TRG_NUM_IN => maximum_trg, -- automatically determined\r
- BIT_LOW_IN => ctrl_bitlow, -- from slow control\r
- BIT_HIGH_IN => ctrl_bithigh, -- from slow control\r
- FL_LOW_IN => ctrl_flatlow, -- from slow control\r
- FL_HIGH_IN => ctrl_flathigh, -- from slow control\r
- APV_ON_IN => adc_on,\r
- -- 100MHZ synchronous interface\r
- -- APV raw buffers\r
- BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW\r
- BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl\r
- BUF_DONE_IN => buf_done, -- from ped_corr_ctrl\r
- BUF_TICK_OUT => buf_tick,\r
- BUF_START_OUT => buf_start,\r
- BUF_READY_OUT => buf_ready,\r
- BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl \r
- BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl\r
- BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl\r
- BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl\r
- BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl\r
- BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl\r
- BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl\r
- BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl\r
- BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl\r
- BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl\r
- BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl\r
- BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl\r
- BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl\r
- BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl\r
- BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl\r
- BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl\r
- -- Debug signals\r
- DEBUG_OUT => raw_buf_debug --open\r
- );\r
+port map( \r
+ CLK_IN => sysclk,\r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => reset_by_trb,\r
+ -- trigger related signals\r
+ APV_RESET_IN => apv_reset, -- (100MHz clock)\r
+ APV_SYNC_IN => apv_sync, -- (40MHz APV clock)\r
+ APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN => adc0_valid,\r
+ ADC0_0_DATA_IN => adc_data(0),\r
+ ADC0_1_DATA_IN => adc_data(1),\r
+ ADC0_2_DATA_IN => adc_data(2),\r
+ ADC0_3_DATA_IN => adc_data(3),\r
+ ADC0_4_DATA_IN => adc_data(4),\r
+ ADC0_5_DATA_IN => adc_data(5),\r
+ ADC0_6_DATA_IN => adc_data(6),\r
+ ADC0_7_DATA_IN => adc_data(7),\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN => adc1_valid,\r
+ ADC1_0_DATA_IN => adc_data(8),\r
+ ADC1_1_DATA_IN => adc_data(9),\r
+ ADC1_2_DATA_IN => adc_data(10),\r
+ ADC1_3_DATA_IN => adc_data(11),\r
+ ADC1_4_DATA_IN => adc_data(12),\r
+ ADC1_5_DATA_IN => adc_data(13),\r
+ ADC1_6_DATA_IN => adc_data(14),\r
+ ADC1_7_DATA_IN => adc_data(15),\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN => maximum_trg, -- automatically determined\r
+ BIT_LOW_IN => ctrl_bitlow, -- from slow control\r
+ BIT_HIGH_IN => ctrl_bithigh, -- from slow control\r
+ FL_LOW_IN => ctrl_flatlow, -- from slow control\r
+ FL_HIGH_IN => ctrl_flathigh, -- from slow control\r
+ APV_ON_IN => adc_on,\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW\r
+ BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl\r
+ BUF_DONE_IN => buf_done, -- from ped_corr_ctrl\r
+ BUF_TICK_OUT => buf_tick,\r
+ BUF_START_OUT => buf_start,\r
+ BUF_READY_OUT => buf_ready,\r
+ BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl \r
+ BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl\r
+ BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl\r
+ BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl\r
+ BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl\r
+ BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl\r
+ BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl\r
+ BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl\r
+ BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl\r
+ BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl\r
+ BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl\r
+ BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl\r
+ BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl\r
+ BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl\r
+ BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl\r
+ BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl\r
+ -- Debug signals\r
+ DEBUG_OUT => raw_buf_debug --open\r
+);\r
\r
\r
----------------------------------------\r
-- ADC1 data handler --\r
----------------------------------------\r
THE_ADC1_HANDLER: adc_data_handler_new \r
-port map( RESET_IN => reset_by_trb,\r
- ADC_LCLK_IN => adc1_lclk,\r
- ADC_ADCLK_IN => adc1_adclk,\r
- ADC_CHNL_IN => adc1_out,\r
- PLL_CTRL_IN => adc1_iodelay,\r
- ADC_DATA7_OUT => adc_raw_data(15),\r
- ADC_DATA6_OUT => adc_raw_data(14),\r
- ADC_DATA5_OUT => adc_raw_data(13),\r
- ADC_DATA4_OUT => adc_raw_data(12),\r
- ADC_DATA3_OUT => adc_raw_data(11),\r
- ADC_DATA2_OUT => adc_raw_data(10),\r
- ADC_DATA1_OUT => adc_raw_data(9),\r
- ADC_DATA0_OUT => adc_raw_data(8),\r
- ADC_CE_OUT => adc1_ce,\r
- ADC_VALID_OUT => adc1_valid,\r
- DEBUG_OUT => open\r
- );\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc1_lclk,\r
+ ADC_ADCLK_IN => adc1_adclk,\r
+ ADC_CHNL_IN => adc1_out,\r
+ PLL_CTRL_IN => adc1_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(15),\r
+ ADC_DATA6_OUT => adc_raw_data(14),\r
+ ADC_DATA5_OUT => adc_raw_data(13),\r
+ ADC_DATA4_OUT => adc_raw_data(12),\r
+ ADC_DATA3_OUT => adc_raw_data(11),\r
+ ADC_DATA2_OUT => adc_raw_data(10),\r
+ ADC_DATA1_OUT => adc_raw_data(9),\r
+ ADC_DATA0_OUT => adc_raw_data(8),\r
+ ADC_CE_OUT => adc1_ce,\r
+ ADC_VALID_OUT => adc1_valid,\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- ADC1 clock domain crossover --\r
----------------------------------------\r
-THE_ADC1_CROSSOVER: adc_crossover\r
-port map( CLK_APV_IN => clk_apv,\r
- RESET_IN => global_sync_reset,\r
- -- ADC clock domain signals\r
- ADC_CLK_IN => adc1_lclk,\r
- ADC_CE_IN => adc1_ce,\r
- ADC_DATA_VALID_IN => adc1_valid,\r
- ADC_DATA_7_IN => adc_raw_data(15),\r
- ADC_DATA_6_IN => adc_raw_data(14),\r
- ADC_DATA_5_IN => adc_raw_data(13),\r
- ADC_DATA_4_IN => adc_raw_data(12),\r
- ADC_DATA_3_IN => adc_raw_data(11),\r
- ADC_DATA_2_IN => adc_raw_data(10),\r
- ADC_DATA_1_IN => adc_raw_data(9),\r
- ADC_DATA_0_IN => adc_raw_data(8),\r
- LEVEL_WR_OUT => open,\r
- -- APV clock domain signals\r
- APV_DATA_7_OUT => adc_data(15),\r
- APV_DATA_6_OUT => adc_data(14),\r
- APV_DATA_5_OUT => adc_data(13),\r
- APV_DATA_4_OUT => adc_data(12),\r
- APV_DATA_3_OUT => adc_data(11),\r
- APV_DATA_2_OUT => adc_data(10),\r
- APV_DATA_1_OUT => adc_data(9),\r
- APV_DATA_0_OUT => adc_data(8),\r
- APV_DATA_VALID_OUT => open,\r
- LEVEL_RD_OUT => open,\r
- -- Debug signals\r
- DEBUG_OUT => open\r
- );\r
+THE_ADC1_CROSSOVER: adc_crossover\r
+port map( \r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc1_lclk,\r
+ ADC_CE_IN => adc1_ce,\r
+ ADC_DATA_VALID_IN => adc1_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(15),\r
+ ADC_DATA_6_IN => adc_raw_data(14),\r
+ ADC_DATA_5_IN => adc_raw_data(13),\r
+ ADC_DATA_4_IN => adc_raw_data(12),\r
+ ADC_DATA_3_IN => adc_raw_data(11),\r
+ ADC_DATA_2_IN => adc_raw_data(10),\r
+ ADC_DATA_1_IN => adc_raw_data(9),\r
+ ADC_DATA_0_IN => adc_raw_data(8),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(15),\r
+ APV_DATA_6_OUT => adc_data(14),\r
+ APV_DATA_5_OUT => adc_data(13),\r
+ APV_DATA_4_OUT => adc_data(12),\r
+ APV_DATA_3_OUT => adc_data(11),\r
+ APV_DATA_2_OUT => adc_data(10),\r
+ APV_DATA_1_OUT => adc_data(9),\r
+ APV_DATA_0_OUT => adc_data(8),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- ADC1 test data multiplexer --\r
----------------------------------------\r
THE_ADC_1_SELECT: adc_channel_select\r
-port map( RESET_IN => reset_by_trb,\r
- ADC_CLK_IN => clk_apv,\r
- ADC_SEL_IN => adc1_select,\r
- ADC_7_IN => adc_data(15),\r
- ADC_6_IN => adc_data(14),\r
- ADC_5_IN => adc_data(13),\r
- ADC_4_IN => adc_data(12),\r
- ADC_3_IN => adc_data(11),\r
- ADC_2_IN => adc_data(10),\r
- ADC_1_IN => adc_data(9),\r
- ADC_0_IN => adc_data(8),\r
- ADC_CH_OUT => adc1_testdata,\r
- DEBUG_OUT => open\r
- );\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc1_select,\r
+ ADC_7_IN => adc_data(15),\r
+ ADC_6_IN => adc_data(14),\r
+ ADC_5_IN => adc_data(13),\r
+ ADC_4_IN => adc_data(12),\r
+ ADC_3_IN => adc_data(11),\r
+ ADC_2_IN => adc_data(10),\r
+ ADC_1_IN => adc_data(9),\r
+ ADC_0_IN => adc_data(8),\r
+ ADC_CH_OUT => adc1_testdata,\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- ADC0 data handler --\r
----------------------------------------\r
THE_ADC0_HANDLER: adc_data_handler_new \r
-port map( RESET_IN => reset_by_trb,\r
- ADC_LCLK_IN => adc0_lclk,\r
- ADC_ADCLK_IN => adc0_adclk,\r
- ADC_CHNL_IN => adc0_out,\r
- PLL_CTRL_IN => adc0_iodelay,\r
- ADC_DATA7_OUT => adc_raw_data(7),\r
- ADC_DATA6_OUT => adc_raw_data(6),\r
- ADC_DATA5_OUT => adc_raw_data(5),\r
- ADC_DATA4_OUT => adc_raw_data(4),\r
- ADC_DATA3_OUT => adc_raw_data(3),\r
- ADC_DATA2_OUT => adc_raw_data(2),\r
- ADC_DATA1_OUT => adc_raw_data(1),\r
- ADC_DATA0_OUT => adc_raw_data(0),\r
- ADC_CE_OUT => adc0_ce,\r
- ADC_VALID_OUT => adc0_valid,\r
- DEBUG_OUT => open\r
- );\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc0_lclk,\r
+ ADC_ADCLK_IN => adc0_adclk,\r
+ ADC_CHNL_IN => adc0_out,\r
+ PLL_CTRL_IN => adc0_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(7),\r
+ ADC_DATA6_OUT => adc_raw_data(6),\r
+ ADC_DATA5_OUT => adc_raw_data(5),\r
+ ADC_DATA4_OUT => adc_raw_data(4),\r
+ ADC_DATA3_OUT => adc_raw_data(3),\r
+ ADC_DATA2_OUT => adc_raw_data(2),\r
+ ADC_DATA1_OUT => adc_raw_data(1),\r
+ ADC_DATA0_OUT => adc_raw_data(0),\r
+ ADC_CE_OUT => adc0_ce,\r
+ ADC_VALID_OUT => adc0_valid,\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- ADC0 clock domain crossover --\r
----------------------------------------\r
-THE_ADC0_CROSSOVER: adc_crossover\r
-port map( CLK_APV_IN => clk_apv,\r
- RESET_IN => global_sync_reset,\r
- -- ADC clock domain signals\r
- ADC_CLK_IN => adc0_lclk,\r
- ADC_CE_IN => adc0_ce,\r
- ADC_DATA_VALID_IN => adc0_valid,\r
- ADC_DATA_7_IN => adc_raw_data(7),\r
- ADC_DATA_6_IN => adc_raw_data(6),\r
- ADC_DATA_5_IN => adc_raw_data(5),\r
- ADC_DATA_4_IN => adc_raw_data(4),\r
- ADC_DATA_3_IN => adc_raw_data(3),\r
- ADC_DATA_2_IN => adc_raw_data(2),\r
- ADC_DATA_1_IN => adc_raw_data(1),\r
- ADC_DATA_0_IN => adc_raw_data(0),\r
- LEVEL_WR_OUT => open,\r
- -- APV clock domain signals\r
- APV_DATA_7_OUT => adc_data(7),\r
- APV_DATA_6_OUT => adc_data(6),\r
- APV_DATA_5_OUT => adc_data(5),\r
- APV_DATA_4_OUT => adc_data(4),\r
- APV_DATA_3_OUT => adc_data(3),\r
- APV_DATA_2_OUT => adc_data(2),\r
- APV_DATA_1_OUT => adc_data(1),\r
- APV_DATA_0_OUT => adc_data(0),\r
- APV_DATA_VALID_OUT => open,\r
- LEVEL_RD_OUT => open,\r
- -- Debug signals\r
- DEBUG_OUT => open\r
- );\r
+THE_ADC0_CROSSOVER: adc_crossover\r
+port map( \r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc0_lclk,\r
+ ADC_CE_IN => adc0_ce,\r
+ ADC_DATA_VALID_IN => adc0_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(7),\r
+ ADC_DATA_6_IN => adc_raw_data(6),\r
+ ADC_DATA_5_IN => adc_raw_data(5),\r
+ ADC_DATA_4_IN => adc_raw_data(4),\r
+ ADC_DATA_3_IN => adc_raw_data(3),\r
+ ADC_DATA_2_IN => adc_raw_data(2),\r
+ ADC_DATA_1_IN => adc_raw_data(1),\r
+ ADC_DATA_0_IN => adc_raw_data(0),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(7),\r
+ APV_DATA_6_OUT => adc_data(6),\r
+ APV_DATA_5_OUT => adc_data(5),\r
+ APV_DATA_4_OUT => adc_data(4),\r
+ APV_DATA_3_OUT => adc_data(3),\r
+ APV_DATA_2_OUT => adc_data(2),\r
+ APV_DATA_1_OUT => adc_data(1),\r
+ APV_DATA_0_OUT => adc_data(0),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- ADC0 test data multiplexer --\r
----------------------------------------\r
THE_ADC_0_SELECT: adc_channel_select\r
-port map( RESET_IN => reset_by_trb,\r
- ADC_CLK_IN => clk_apv,\r
- ADC_SEL_IN => adc0_select,\r
- ADC_7_IN => adc_data(7),\r
- ADC_6_IN => adc_data(6),\r
- ADC_5_IN => adc_data(5),\r
- ADC_4_IN => adc_data(4),\r
- ADC_3_IN => adc_data(3),\r
- ADC_2_IN => adc_data(2),\r
- ADC_1_IN => adc_data(1),\r
- ADC_0_IN => adc_data(0),\r
- ADC_CH_OUT => adc0_testdata,\r
- DEBUG_OUT => open\r
- );\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc0_select,\r
+ ADC_7_IN => adc_data(7),\r
+ ADC_6_IN => adc_data(6),\r
+ ADC_5_IN => adc_data(5),\r
+ ADC_4_IN => adc_data(4),\r
+ ADC_3_IN => adc_data(3),\r
+ ADC_2_IN => adc_data(2),\r
+ ADC_1_IN => adc_data(1),\r
+ ADC_0_IN => adc_data(0),\r
+ ADC_CH_OUT => adc0_testdata,\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- Trigger handler (APV specific) --\r
----------------------------------------\r
THE_APV_TRGCTRL: apv_trgctrl\r
-port map( CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- CLK_APV_IN => clk_apv,\r
- -- Triggers\r
- SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse\r
- TIME_TRG_IN => ext_in, -- external trigger inputs\r
- TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers\r
- STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers.\r
- TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint\r
- -- slow control settings\r
- TRG_MAX_OUT => maximum_trg,\r
- TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control\r
- TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control\r
- TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control\r
- TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control\r
- TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control\r
- TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control\r
- TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control\r
- TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control\r
- TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control\r
- -- TRB LVL1 signals\r
- TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint\r
- TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint\r
- TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
- TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
- TRB_MISSING_OUT => lvl1_trg_missing,\r
- TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
- TRB_RST_COUNTER_IN => common_ctrl_reg(30), -- depreciated!\r
- TRB_COUNTER_OUT => local_lvl1_counter,\r
- -- EDS signals\r
- EDS_DATA_OUT => eds_data, -- to ped_corr_stage\r
- EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage\r
- EDS_DONE_IN => eds_done, -- from ped_corr_stage\r
- EDS_FULL_OUT => eds_buf_full,\r
- EDS_LEVEL_OUT => eds_buf_level,\r
- FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock)\r
- -- APV signals \r
- APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock)\r
- APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock)\r
- DEBUG_OUT => trgctrl_debug\r
- );\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ CLK_APV_IN => clk_apv,\r
+ -- Triggers\r
+ SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse\r
+ TIME_TRG_IN => ext_in, -- external trigger inputs\r
+ TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers\r
+ STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers.\r
+ TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint\r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ -- slow control settings\r
+ TRG_MAX_OUT => maximum_trg,\r
+ TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control\r
+ TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control\r
+ TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control\r
+ TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control\r
+ TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control\r
+ TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control\r
+ TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control\r
+ TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control\r
+ TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint\r
+ TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint\r
+ TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
+ TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint\r
+ TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
+ TRB_MISSING_OUT => lvl1_trg_missing,\r
+ TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
+ TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter\r
+ TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter\r
+ TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value\r
+ -- EDS signals\r
+ EDS_DATA_OUT => eds_data, -- to ped_corr_stage\r
+ EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage\r
+ EDS_DONE_IN => eds_done, -- from ped_corr_stage\r
+ EDS_FULL_OUT => eds_buf_full,\r
+ EDS_LEVEL_OUT => eds_buf_level,\r
+ FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock)\r
+ -- APV signals \r
+ APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock)\r
+ APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock)\r
+ DEBUG_OUT => trgctrl_debug\r
+);\r
\r
\r
----------------------------------------\r
adc1_pd <= adc1_powerdown;\r
\r
THE_ADC1CLK_OUT: ODDRXC\r
-port map( DA => '1',\r
- DB => '0',\r
- CLK => clk_adc,\r
- RST => '0',\r
- Q => adc1_clk\r
- );\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc1_clk\r
+);\r
\r
adc0_rst <= adc0_reset;\r
adc0_pd <= adc0_powerdown;\r
\r
THE_ADC0CLK_OUT: ODDRXC\r
-port map( DA => '1',\r
- DB => '0',\r
- CLK => clk_adc,\r
- RST => '0',\r
- Q => adc0_clk\r
- );\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc0_clk\r
+);\r
\r
\r
----------------------------------------\r
-- CLK and TRG signal\r
-- CLK is shifted to meet timing constraints of APV\r
THE_APV0ACLK_OUT: ODDRXC\r
-port map( DA => '0', \r
- DB => '1', \r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0a_clk\r
- );\r
+port map( \r
+ DA => '0', \r
+ DB => '1', \r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_clk\r
+);\r
\r
THE_APV0BCLK_OUT: ODDRXC\r
-port map( DA => '0',\r
- DB => '1',\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0b_clk\r
- );\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_clk\r
+);\r
\r
THE_APV1ACLK_OUT: ODDRXC\r
-port map( DA => '0',\r
- DB => '1',\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1a_clk\r
- );\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_clk\r
+);\r
\r
THE_APV1BCLK_OUT: ODDRXC\r
-port map( DA => '0',\r
- DB => '1',\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1b_clk\r
- );\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_clk\r
+);\r
\r
THE_APV0ATRG_OUT: ODDRXC\r
-port map( DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0a_trg\r
- );\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_trg\r
+);\r
THE_APV0BTRG_OUT: ODDRXC\r
-port map( DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0b_trg\r
- );\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_trg\r
+);\r
THE_APV1ATRG_OUT: ODDRXC\r
-port map( DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1a_trg\r
- );\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_trg\r
+);\r
THE_APV1BTRG_OUT: ODDRXC\r
-port map( DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1b_trg\r
- );\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_trg\r
+);\r
\r
\r
----------------------------------------\r
-- Reboot handler (pulse triggered) --\r
----------------------------------------\r
THE_REBOOT_HANDLER: reboot_handler\r
-port map( RESET_IN => reset_by_trb,\r
- CLK_IN => sysclk,\r
- START_IN => common_ctrl_reg(15),\r
- REBOOT_OUT => uc_reboot,\r
- DEBUG_OUT => open\r
- );\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ CLK_IN => sysclk,\r
+ START_IN => common_ctrl_reg(15),\r
+ REBOOT_OUT => uc_reboot,\r
+ DEBUG_OUT => open\r
+);\r
\r
\r
----------------------------------------\r
-- FPGA debug header driver --\r
----------------------------------------\r
THE_DBG_CLK_OUT: ODDRXC\r
-port map( DA => '1',\r
- DB => '0',\r
- CLK => debug_clk,\r
- RST => '0',\r
- Q => dbg_exp(43)\r
- );\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => debug_clk,\r
+ RST => '0',\r
+ Q => dbg_exp(43)\r
+);\r
\r
THE_DEBUG_REG_PROC: process( debug_clk )\r
begin\r
\r
package adcmv3_components is\r
\r
- component raw_buf_stage_new is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
- RESET_IN : in std_logic; -- general reset (100MHz)\r
- -- trigger related signals\r
- APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
- APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
- APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
- -- ADC0 signals\r
- ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
- ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
- ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
- ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
- ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
- ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
- ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
- ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
- ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
- -- ADC1 signals\r
- ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
- ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
- ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
- ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
- ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
- ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
- ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
- ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
- ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
- -- Slow control registers\r
- MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
- BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
- BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
- FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
- FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
- APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
- -- 100MHZ synchronous interface\r
- -- APV raw buffers\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
- BUF_DONE_IN : in std_logic;\r
- BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
- BUF_START_OUT : out std_logic_vector(15 downto 0);\r
- BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
- BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
- end component raw_buf_stage_new;\r
- \r
- component adc_data_handler_new is\r
- port( RESET_IN : in std_logic;\r
- ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
- ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
- ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
- PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
- ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
- ADC_CE_OUT : out std_logic;\r
- ADC_VALID_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component adc_data_handler_new;\r
-\r
- component adc_crossover is\r
- port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
- RESET_IN : in std_logic; -- general reset (100MHz)\r
- -- ADC clock domain signals\r
- ADC_CLK_IN : in std_logic;\r
- ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
- ADC_DATA_VALID_IN : in std_logic;\r
- ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
- ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
- LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
- -- APV clock domain signals\r
- APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
- APV_DATA_VALID_OUT : out std_logic;\r
- LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
- end component adc_crossover;\r
- \r
- component crossover is\r
- port( DATA : in std_logic_vector(95 downto 0);\r
- WRCLOCK : in std_logic;\r
- RDCLOCK : in std_logic;\r
- WREN : in std_logic;\r
- RDEN : in std_logic;\r
- RESET : in std_logic; -- asynchronous reset! \r
- RPRESET : in std_logic;\r
- Q : out std_logic_vector(95 downto 0);\r
- WCNT : out std_logic_vector(4 downto 0);\r
- RCNT : out std_logic_vector(4 downto 0);\r
- EMPTY : out std_logic;\r
- FULL : out std_logic\r
- );\r
- end component crossover;\r
-\r
- component slv_adc_la is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
- ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
- ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component slv_adc_la;\r
+component raw_buf_stage_new is\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- trigger related signals\r
+ APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
+ APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
+ APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
+ ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
+ ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
+ ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
+ ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
+ ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
+ ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
+ ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
+ ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
+ ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
+ ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
+ ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
+ ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
+ ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
+ ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
+ APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : in std_logic;\r
+ BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component raw_buf_stage_new;\r
+\r
+component adc_data_handler_new is\r
+port(\r
+ RESET_IN : in std_logic;\r
+ ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
+ ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
+ ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
+ ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : out std_logic;\r
+ ADC_VALID_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_data_handler_new;\r
+\r
+component adc_crossover is\r
+port(\r
+ CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
+ ADC_DATA_VALID_IN : in std_logic;\r
+ ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
+ LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : out std_logic;\r
+ LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+);\r
+end component adc_crossover;\r
+\r
+component crossover is\r
+port(\r
+ DATA : in std_logic_vector(95 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ WREN : in std_logic;\r
+ RDEN : in std_logic;\r
+ RESET : in std_logic; -- asynchronous reset!\r
+ RPRESET : in std_logic;\r
+ Q : out std_logic_vector(95 downto 0);\r
+ WCNT : out std_logic_vector(4 downto 0);\r
+ RCNT : out std_logic_vector(4 downto 0);\r
+ EMPTY : out std_logic;\r
+ FULL : out std_logic\r
+);\r
+end component crossover;\r
+\r
+component slv_adc_la is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_adc_la;\r
\r
-- NOT USED YET\r
- component logic_analyzer is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- control signals\r
- ARM_IN : in std_logic; -- arm the machine\r
- TRG_IN : in std_logic; -- trigger the data acquisition\r
- MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); \r
- -- status signals\r
- SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
- SM_CE_OUT : out std_logic;\r
- SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
- CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
- RUN_OUT : out std_logic; -- ready for trigger\r
- SAMPLE_OUT : out std_logic; -- data acquisition running\r
- READY_OUT : out std_logic; -- data acquisition is finished\r
- LAST_OUT : out std_logic; -- last data word of sampling\r
- -- Status lines\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component logic_analyzer;\r
-\r
- component onewire_spare_one is\r
- port( ADDRESS : in std_logic_vector(2 downto 0); \r
- Q : out std_logic_vector(3 downto 0)\r
- );\r
- end component onewire_spare_one;\r
-\r
- component adc_onewire_map_mem is\r
- port( ADDRESS : in std_logic_vector(6 downto 0); \r
- Q : out std_logic_vector(3 downto 0)\r
- );\r
- end component adc_onewire_map_mem;\r
-\r
- component adc_channel_select is\r
- port( RESET_IN : in std_logic;\r
- ADC_CLK_IN : in std_logic;\r
- ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
- ADC_7_IN : in std_logic_vector(11 downto 0);\r
- ADC_6_IN : in std_logic_vector(11 downto 0);\r
- ADC_5_IN : in std_logic_vector(11 downto 0);\r
- ADC_4_IN : in std_logic_vector(11 downto 0);\r
- ADC_3_IN : in std_logic_vector(11 downto 0);\r
- ADC_2_IN : in std_logic_vector(11 downto 0);\r
- ADC_1_IN : in std_logic_vector(11 downto 0);\r
- ADC_0_IN : in std_logic_vector(11 downto 0);\r
- ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component slv_adc_snoop is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
- ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
- ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component adc_snoop_mem is\r
- port( WRADDRESS : in std_logic_vector(9 downto 0); \r
- RDADDRESS : in std_logic_vector(9 downto 0); \r
- DATA : in std_logic_vector(15 downto 0); \r
- WE : in std_logic; \r
- RDCLOCK : in std_logic; \r
- RDCLOCKEN : in std_logic; \r
- RESET : in std_logic; \r
- WRCLOCK : in std_logic; \r
- WRCLOCKEN : in std_logic; \r
- Q : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
-\r
- component max_data is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- TODO_3_IN : in std_logic_vector(3 downto 0);\r
- TODO_2_IN : in std_logic_vector(3 downto 0);\r
- TODO_1_IN : in std_logic_vector(3 downto 0);\r
- TODO_0_IN : in std_logic_vector(3 downto 0);\r
- TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component comp4bit is\r
- port( DATAA : in std_logic_vector(3 downto 0); \r
- DATAB : in std_logic_vector(3 downto 0); \r
- AGTB : out std_logic\r
- );\r
- end component;\r
-\r
- component slv_register_bank is\r
- generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" );\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
- STAT_0_IN : in std_logic_vector(15 downto 0);\r
- STAT_1_IN : in std_logic_vector(15 downto 0);\r
- STAT_2_IN : in std_logic_vector(15 downto 0);\r
- STAT_3_IN : in std_logic_vector(15 downto 0);\r
- STAT_4_IN : in std_logic_vector(15 downto 0);\r
- STAT_5_IN : in std_logic_vector(15 downto 0);\r
- STAT_6_IN : in std_logic_vector(15 downto 0);\r
- STAT_7_IN : in std_logic_vector(15 downto 0);\r
- STAT_8_IN : in std_logic_vector(15 downto 0);\r
- STAT_9_IN : in std_logic_vector(15 downto 0);\r
- STAT_10_IN : in std_logic_vector(15 downto 0);\r
- STAT_11_IN : in std_logic_vector(15 downto 0);\r
- STAT_12_IN : in std_logic_vector(15 downto 0);\r
- STAT_13_IN : in std_logic_vector(15 downto 0);\r
- STAT_14_IN : in std_logic_vector(15 downto 0);\r
- STAT_15_IN : in std_logic_vector(15 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component pulse_stretch is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- START_IN : in std_logic;\r
- PULSE_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_adc_map_mem is\r
- port( ADDRESS : in std_logic_vector(6 downto 0); \r
- Q : out std_logic_vector(3 downto 0)\r
- );\r
- end component;\r
-\r
- component adc_apv_map_mem is\r
- port( ADDRESS : in std_logic_vector(6 downto 0); \r
- Q : out std_logic_vector(3 downto 0)\r
- );\r
- end component;\r
-\r
-\r
- component ped_thr_true is\r
- port( DATAINA : in std_logic_vector(17 downto 0); \r
- DATAINB : in std_logic_vector(17 downto 0); \r
- ADDRESSA : in std_logic_vector(6 downto 0); \r
- ADDRESSB : in std_logic_vector(6 downto 0); \r
- CLOCKA : in std_logic; \r
- CLOCKB : in std_logic; \r
- CLOCKENA : in std_logic; \r
- CLOCKENB : in std_logic; \r
- WRA : in std_logic; \r
- WRB : in std_logic; \r
- RESETA : in std_logic; \r
- RESETB : in std_logic; \r
- QA : out std_logic_vector(17 downto 0); \r
- QB : out std_logic_vector(17 downto 0)\r
- );\r
- end component;\r
-\r
- component slv_ped_thr_mem is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- backplane identifier\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- -- I/O to the backend\r
- MEM_CLK_IN : in std_logic;\r
- MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
- MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component reset_handler is\r
- port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
- RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
- CLK_IN : in std_logic;\r
- TRB_RESET_IN : in std_logic;\r
- RESET_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component pll_40m is\r
- port( CLK : in std_logic;\r
- RESET : in std_logic; \r
- DPAMODE : in std_logic;\r
- DPHASE0 : in std_logic;\r
- DPHASE1 : in std_logic;\r
- DPHASE2 : in std_logic;\r
- DPHASE3 : in std_logic;\r
- CLKOP : out std_logic;\r
- CLKOS : out std_logic;\r
- LOCK : out std_logic\r
- );\r
- end component;\r
-\r
- component dll_100m is\r
- port( CLK : in std_logic; \r
- RESETN : in std_logic; \r
- ALUHOLD : in std_logic; \r
- CLKOP : out std_logic; \r
- CLKOS : out std_logic; \r
- LOCK : out std_logic\r
- );\r
- end component;\r
-\r
- component state_sync is\r
- port( STATE_A_IN : in std_logic;\r
- CLK_B_IN : in std_logic;\r
- RESET_B_IN : in std_logic;\r
- STATE_B_OUT : out std_logic\r
- );\r
- end component;\r
-\r
- component pulse_sync is\r
- port( CLK_A_IN : in std_logic;\r
- RESET_A_IN : in std_logic;\r
- PULSE_A_IN : in std_logic;\r
- CLK_B_IN : in std_logic;\r
- RESET_B_IN : in std_logic;\r
- PULSE_B_OUT : out std_logic\r
- );\r
- end component; \r
-\r
- component rich_trb is\r
- port( CLK100M_IN : in std_logic;\r
- SYSCLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic; \r
- SD_TXD_N_OUT : out std_logic;\r
- SD_PRESENT_IN : in std_logic;\r
- SD_TXDIS_OUT : out std_logic;\r
- SD_LOS_IN : in std_logic;\r
- ONEWIRE_INOUT : inout std_logic;\r
- -- common regIO status / control registers\r
--- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI\r
- COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI\r
--- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI\r
- COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI\r
- -- status register input to regIO / control register output from regIO\r
- CONTROL_OUT : out std_logic_vector(63 downto 0);\r
- STATUS_IN : in std_logic_vector(127 downto 0); \r
- -- LVL1 signals\r
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
- LVL1_TRG_RECEIVED_OUT : out std_logic;\r
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);\r
- LVL1_TRG_RELEASE_IN : in std_logic;\r
- TIMING_TRG_FOUND_IN : in std_logic;\r
- -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
- IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag\r
- IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information\r
- IPU_START_READOUT_OUT : out std_logic; -- gimme data!\r
- IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
- IPU_DATAREADY_IN : in std_logic; -- data is valid\r
- IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM\r
- IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle \r
- IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
- IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern\r
- -- regIO bus\r
--- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- REGIO_READ_ENABLE_OUT : out std_logic;\r
- REGIO_WRITE_ENABLE_OUT : out std_logic;\r
--- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
--- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0);\r
- REGIO_DATAREADY_IN : in std_logic;\r
- REGIO_NO_MORE_DATA_IN : in std_logic;\r
- REGIO_WRITE_ACK_IN : in std_logic;\r
- REGIO_UNKNOWN_ADDR_IN : in std_logic;\r
- REGIO_TIMEOUT_OUT : out std_logic;\r
- -- status LEDs\r
- LED_LINK_STAT : out std_logic;\r
- LED_LINK_TXD : out std_logic;\r
- LED_LINK_RXD : out std_logic;\r
- LINK_BSM_OUT : out std_logic_vector(3 downto 0);\r
- RESET_OUT : out std_logic;\r
- -- Debug\r
- DEBUG : out std_logic_vector(63 downto 0)\r
- );\r
- end component;\r
-\r
- component slave_bus is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- RegIO signals\r
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus \r
- REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
- REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
- REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
- REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
- REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
- REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
- REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
- REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- -- 1Wire connections\r
- ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
- ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs\r
- BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- ADC 0 SPI connections\r
- SPI_ADC0_CS_OUT : out std_logic;\r
- SPI_ADC0_SCK_OUT : out std_logic;\r
- SPI_ADC0_SDO_OUT : out std_logic;\r
- ADC0_PLL_LOCKED_IN : in std_logic;\r
- ADC0_PD_OUT : out std_logic;\r
- ADC0_RST_OUT : out std_logic;\r
- ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
- ADC0_CLK_IN : in std_logic;\r
- ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
- ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
- APV0_RST_OUT : out std_logic;\r
- -- ADC 0 SPI connections\r
- SPI_ADC1_CS_OUT : out std_logic;\r
- SPI_ADC1_SCK_OUT : out std_logic;\r
- SPI_ADC1_SDO_OUT : out std_logic;\r
- ADC1_PLL_LOCKED_IN : in std_logic;\r
- ADC1_PD_OUT : out std_logic;\r
- ADC1_RST_OUT : out std_logic;\r
- ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
- ADC1_CLK_IN : in std_logic;\r
- ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
- ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
- APV1_RST_OUT : out std_logic;\r
- -- User specific inputs / outputs\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- -- pedestal interface\r
- PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
- PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
- -- threshold interface\r
- THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
- THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
- -- APV control / status\r
- CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
- STAT_0_IN : in std_logic_vector(15 downto 0);\r
- STAT_1_IN : in std_logic_vector(15 downto 0);\r
- STAT_2_IN : in std_logic_vector(15 downto 0);\r
- STAT_3_IN : in std_logic_vector(15 downto 0);\r
- STAT_4_IN : in std_logic_vector(15 downto 0);\r
- STAT_5_IN : in std_logic_vector(15 downto 0);\r
- STAT_6_IN : in std_logic_vector(15 downto 0);\r
- STAT_7_IN : in std_logic_vector(15 downto 0);\r
- STAT_8_IN : in std_logic_vector(15 downto 0);\r
- STAT_9_IN : in std_logic_vector(15 downto 0);\r
- STAT_10_IN : in std_logic_vector(15 downto 0);\r
- STAT_11_IN : in std_logic_vector(15 downto 0);\r
- STAT_12_IN : in std_logic_vector(15 downto 0);\r
- STAT_13_IN : in std_logic_vector(15 downto 0);\r
- STAT_14_IN : in std_logic_vector(15 downto 0);\r
- STAT_15_IN : in std_logic_vector(15 downto 0);\r
- -- some control signals\r
- CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
- CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
- CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
- STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
- -- temporary stuff\r
- TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
- TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
- -- Debug\r
- DEBUG_OUT : out std_logic_vector(63 downto 0);\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
- end component;\r
-\r
- component oddrxc is\r
- port( DA : in std_logic;\r
- DB : in std_logic;\r
- CLK : in std_logic;\r
- RST : in std_logic;\r
- Q : out std_logic\r
- );\r
- end component;\r
-\r
- component apv_trgctrl is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
- -- Triggers\r
- SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
- TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
- TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
- STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
- TRG_FOUND_OUT : out std_logic; -- trigger found\r
- -- slow control settings\r
- TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
- TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
- TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
- TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
- TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
- TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
- -- TRB LVL1 signals\r
- TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
- TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
- TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
- TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
- TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
- TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
- TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter\r
- TRB_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
- -- EDS signals\r
- EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
- EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
- EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
- EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
- EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
- -- APV signals \r
- APV_TRG_OUT : out std_logic;\r
- APV_SYNC_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
- end component;\r
-\r
- component ped_corr_ctrl is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- RESET_IN : in std_logic; -- synchronous reset\r
- -- Slow control registers\r
- -- EDS buffer -- back to previous source stage\r
- EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
- EDS_AVAIL_IN : in std_logic;\r
- EDS_DONE_OUT : out std_logic;\r
- EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
- -- DHDR information -- to next stage\r
- DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
- DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
- DHDR_STORE_OUT : out std_logic;\r
- DHDR_BUF_FULL_IN : in std_logic;\r
- -- data buffers -- from raw_buf_stage\r
- BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
- BUF_DONE_OUT : out std_logic;\r
- BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
- BUF_START_IN : in std_logic_vector(15 downto 0);\r
- -- raw data\r
- BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
- -- Pedestal data \r
- PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
- PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
- -- Threshold data\r
- THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
- THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
- -- processed data\r
- FIFO_START_OUT : out std_logic;\r
- FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
- FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
- -- Debug signals\r
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component ipu_fifo_stage is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- RESET_IN : in std_logic; -- synchronous reset\r
- -- Slow control signals \r
- SECTOR_IN : in std_logic_vector(2 downto 0);\r
- MODULE_IN : in std_logic_vector(2 downto 0);\r
- -- IPU channel connections\r
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
- IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
- IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
- IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
- IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
- IPU_READ_IN : in std_logic; -- read strobe, low every second cycle \r
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
- LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
- -- DHDR buffer input\r
- DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
- DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
- DHDR_STORE_IN : in std_logic;\r
- DHDR_BUF_FULL_OUT : out std_logic;\r
- -- processed data input\r
- FIFO_START_IN : in std_logic;\r
- FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
- FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
- -- Debug signals\r
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
- end component;\r
-\r
- component ipu_dummy is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- RESET_IN : in std_logic; -- synchronous reset\r
- -- Slow control signals \r
- MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
- MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
- CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
- -- IPU channel connections\r
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
- IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
- IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
- IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
- IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
- IPU_READ_IN : in std_logic; -- read strobe, low every second cycle \r
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
- -- DHDR buffer\r
- LVL1_FIFO_RD_OUT : out std_logic;\r
- LVL1_FIFO_EMPTY_IN : in std_logic;\r
- LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
- LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
- -- Debug signals\r
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
- end component;\r
-\r
- component reboot_handler is\r
- port( RESET_IN : in std_logic;\r
- CLK_IN : in std_logic;\r
- START_IN : in std_logic;\r
- REBOOT_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component real_trg_handler is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
- TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
- APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
- TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
- TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
- TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
- TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
- TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
- TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
- TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag \r
- TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number \r
- TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type\r
- TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
- TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
- RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter\r
- LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter\r
- BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
- APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
- APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine\r
- EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
- EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
- EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
- EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger\r
- DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_trg_handler is\r
- port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
- RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
- CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
- APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
- APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
- APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
- APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
- APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
- APV_TRG_OUT : out std_logic;\r
- APV_TRGSENT_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_sync_handler is\r
- port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
- RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
- CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
- APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
- APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
- APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
- APV_TRG_OUT : out std_logic;\r
- APV_SYNC_OUT : out std_logic; -- signal for statemachines\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component eds_buf is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- -- EDS input, all synced to CLK_IN\r
- EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
- EDS_WE_IN : in std_logic; -- EDS write enable\r
- EDS_DONE_IN : in std_logic; -- release EDS \r
- EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
- EDS_AVAILABLE_OUT : out std_logic;\r
- -- trigger busy information\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component adc_pll is\r
- port( CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLKOP : out std_logic; \r
- LOCK : out std_logic\r
- );\r
- end component;\r
- \r
- component adc_ch_in is \r
- port( DEL : in std_logic_vector(3 downto 0);\r
- ECLK : in std_logic; \r
- SCLK : in std_logic; \r
- RST : in std_logic; \r
- DATA : in std_logic_vector(0 downto 0); \r
- Q : out std_logic_vector(1 downto 0)\r
- ); \r
- end component; \r
-\r
- component adc_twochannels is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock\r
- DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
- DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
- DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
- DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
- STORE_OUT : out std_logic;\r
- SWAP_OUT : out std_logic;\r
- CLOCK_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_locker is\r
- port( CLK_APV_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN\r
- ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
- SYNC_IN : in std_logic; -- sync trigger input \r
- APV_ON_IN : in std_logic; -- this APV channel is switched on\r
- BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
- BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
- FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
- FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
- STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
- STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
- STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
- STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
- STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
- STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
- STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
- STATUS_TICKMARK_OUT : out std_logic;\r
- FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
- FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
- FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
- FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
- FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
- FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
- APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
- APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
- APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
- APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
- APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
- APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer \r
- APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_raw_buffer is\r
- port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
- RESET_IN : in std_logic;\r
- FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
- MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
- ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
- ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
- ADC_LAST_IN : in std_logic; -- last channel signal\r
- ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
- ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
- ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
- ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
- BUF_CLK_IN : in std_logic; -- read clock\r
- BUF_RESET_IN : in std_logic; -- 100MHz reset\r
- BUF_START_OUT : out std_logic; -- one block starts writing\r
- BUF_READY_OUT : out std_logic; -- one block has been written\r
- BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
- BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
- BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
- BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
- BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
- BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
- BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
- BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
- BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler\r
- BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component slv_register is\r
- generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- BUSY_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- REG_DATA_IN : in std_logic_vector(31 downto 0);\r
- REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component slv_half_register is\r
- generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" );\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
- CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component i2c_master is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component slv_onewire_memory is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- backplane identifier\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- -- 1Wire lines\r
- ONEWIRE_START_IN : in std_logic;\r
- ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
- BP_ONEWIRE_INOUT : inout std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component spi_real_slim is\r
- port( SYSCLK : in std_logic; -- 100MHz sysclock\r
- RESET : in std_logic; -- synchronous reset\r
- -- Command interface\r
- START_IN : in std_logic; -- one start pulse\r
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
- CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
- -- SPI interface\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- DEBUG\r
- CLK_EN_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
- end component;\r
-\r
- component spi_adc_master is\r
- generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" );\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- -- ADC connections\r
- ADC_LOCKED_IN : in std_logic;\r
- ADC_PD_OUT : out std_logic;\r
- ADC_RST_OUT : out std_logic;\r
- ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
- -- APV connections\r
- APV_RST_OUT : out std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
-\r
- component i2c_slim is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic; \r
- -- I2C command / setup\r
- I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
- ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
- I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
- I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
- I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
- I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
- I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
- STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
- I2C_BUSY_OUT : out std_logic;\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- -- Debug\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
- end component;\r
- \r
- component i2c_gstart is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- START_IN : in std_logic; \r
- DOSTART_IN : in std_logic; \r
- I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
- SDONE_OUT : out std_logic;\r
- SOK_OUT : out std_logic;\r
- SDA_IN : in std_logic;\r
- SCL_IN : in std_logic;\r
- R_SCL_OUT : out std_logic;\r
- S_SCL_OUT : out std_logic;\r
- R_SDA_OUT : out std_logic;\r
- S_SDA_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(3 downto 0)\r
- );\r
- end component;\r
-\r
- component i2c_sendb is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- DOBYTE_IN : in std_logic; \r
- I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
- I2C_BYTE_IN : in std_logic_vector(8 downto 0); \r
- I2C_BACK_OUT : out std_logic_vector(8 downto 0);\r
- SDA_IN : in std_logic;\r
- R_SDA_OUT : out std_logic;\r
- S_SDA_OUT : out std_logic;\r
--- SCL_IN : in std_logic;\r
- R_SCL_OUT : out std_logic;\r
- S_SCL_OUT : out std_logic;\r
- BDONE_OUT : out std_logic;\r
- BOK_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(3 downto 0)\r
- );\r
- end component;\r
-\r
- component onewire_master is\r
- generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds\r
- port( CLK : in std_logic;\r
- RESET : in std_logic;\r
- READOUT_ENABLE_IN : in std_logic;\r
- -- connection to 1-wire interface (16 APV FEs)\r
- ONEWIRE : inout std_logic_vector(15 downto 0);\r
- BP_ONEWIRE : inout std_logic;\r
- -- connection to external DPRAM for slow control readout\r
- BP_DATA_OUT : out std_logic_vector(15 downto 0);\r
- DATA_OUT : out std_logic_vector(15 downto 0);\r
- ADDR_OUT : out std_logic_vector(6 downto 0);\r
- WRITE_OUT : out std_logic;\r
- BUSY_OUT : out std_logic;\r
- -- debug\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- STAT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component slv_onewire_dpram\r
- port( WRADDRESS : in std_logic_vector(6 downto 0); \r
- RDADDRESS : in std_logic_vector(5 downto 0); \r
- DATA : in std_logic_vector(15 downto 0);\r
- WE : in std_logic; \r
- RDCLOCK : in std_logic;\r
- RDCLOCKEN : in std_logic; \r
- RESET : in std_logic;\r
- WRCLOCK : in std_logic; \r
- WRCLOCKEN : in std_logic;\r
- Q : out std_logic_vector(31 downto 0)\r
- );\r
- end component;\r
-\r
- component dhdr_buf is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- -- DHDR information block\r
- DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
- DHDR_WE_IN : in std_logic; -- EDS write enable\r
- DHDR_DONE_IN : in std_logic; -- release EDS \r
- DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
- DHDR_AVAILABLE_OUT : out std_logic;\r
- -- trigger busy information\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component fifo_2kx27 is\r
- port( DATA : in std_logic_vector(26 downto 0); \r
- CLOCK : in std_logic; \r
- WREN : in std_logic; \r
- RDEN : in std_logic; \r
- RESET : in std_logic; \r
- Q : out std_logic_vector(26 downto 0); \r
- WCNT : out std_logic_vector(11 downto 0); \r
- EMPTY : out std_logic; \r
- FULL : out std_logic\r
- );\r
- end component fifo_2kx27;\r
-\r
- component fifo_16x11 is\r
- port( DATA : in std_logic_vector(10 downto 0); \r
- CLOCK : in std_logic; \r
- WREN : in std_logic; \r
- RDEN : in std_logic; \r
- RESET : in std_logic; \r
- Q : out std_logic_vector(10 downto 0); \r
- WCNT : out std_logic_vector(4 downto 0); \r
- EMPTY : out std_logic; \r
- FULL : out std_logic\r
- );\r
- end component fifo_16x11;\r
-\r
- component dhdr_buffer_dpram is\r
- port( WRADDRESS : in std_logic_vector(3 downto 0); \r
- DATA : in std_logic_vector(47 downto 0); \r
- WRCLOCK : in std_logic; \r
- WE : in std_logic; \r
- WRCLOCKEN : in std_logic; \r
- RDADDRESS : in std_logic_vector(3 downto 0); \r
- RDCLOCK : in std_logic; \r
- RDCLOCKEN : in std_logic; \r
- RESET : in std_logic; \r
- Q : out std_logic_vector(47 downto 0)\r
- );\r
- end component;\r
-\r
- component decoder_8bit is\r
- port( ADDRESS : in std_logic_vector(7 downto 0); \r
- Q : out std_logic_vector(3 downto 0)\r
- );\r
- end component decoder_8bit;\r
-\r
- component adder_5bit is\r
- port( DATAA : in std_logic_vector(4 downto 0); \r
- DATAB : in std_logic_vector(4 downto 0); \r
- CLOCK : in std_logic; \r
- RESET : in std_logic; \r
- CLOCKEN : in std_logic; \r
- RESULT : out std_logic_vector(4 downto 0)\r
- );\r
- end component adder_5bit;\r
-\r
- component adder_16bit is\r
- port( DATAA : in std_logic_vector(15 downto 0); \r
- DATAB : in std_logic_vector(15 downto 0); \r
- CLOCK : in std_logic; \r
- RESET : in std_logic; \r
- CLOCKEN : in std_logic; \r
- RESULT : out std_logic_vector(15 downto 0)\r
- );\r
- end component adder_16bit;\r
-\r
- component suber_12bit is\r
- port( DATAA : in std_logic_vector(11 downto 0); \r
- DATAB : in std_logic_vector(11 downto 0); \r
- CLOCK : in std_logic; \r
- RESET : in std_logic; \r
- CLOCKEN : in std_logic; \r
- RESULT : out std_logic_vector(11 downto 0)\r
- );\r
- end component suber_12bit;\r
-\r
-\r
- component buf_toc is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
- BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
- WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
- FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
- BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
- GOODDATA_OUT : out std_logic;\r
- BADDATA_OUT : out std_logic;\r
- NODATA_OUT : out std_logic;\r
- READY_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component buf_toc;\r
-\r
- component ref_row_sel is\r
- port( CLK_IN : in std_logic;\r
- READY_IN : in std_logic_vector(15 downto 0);\r
- GOODDATA_IN : in std_logic_vector(15 downto 0);\r
- FRAME_0_IN : in std_logic_vector(11 downto 0);\r
- FRAME_1_IN : in std_logic_vector(11 downto 0);\r
- FRAME_2_IN : in std_logic_vector(11 downto 0);\r
- FRAME_3_IN : in std_logic_vector(11 downto 0);\r
- FRAME_4_IN : in std_logic_vector(11 downto 0);\r
- FRAME_5_IN : in std_logic_vector(11 downto 0);\r
- FRAME_6_IN : in std_logic_vector(11 downto 0);\r
- FRAME_7_IN : in std_logic_vector(11 downto 0);\r
- FRAME_8_IN : in std_logic_vector(11 downto 0);\r
- FRAME_9_IN : in std_logic_vector(11 downto 0);\r
- FRAME_10_IN : in std_logic_vector(11 downto 0);\r
- FRAME_11_IN : in std_logic_vector(11 downto 0);\r
- FRAME_12_IN : in std_logic_vector(11 downto 0);\r
- FRAME_13_IN : in std_logic_vector(11 downto 0);\r
- FRAME_14_IN : in std_logic_vector(11 downto 0);\r
- FRAME_15_IN : in std_logic_vector(11 downto 0);\r
- VALID_BUFS_OUT : out std_logic;\r
- READY_OUT : out std_logic;\r
- ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
- APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
- APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
- REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component ref_row_sel;\r
-\r
- component frmctr_check is\r
- port( CLK_IN : in std_logic;\r
- GOODDATA_IN : in std_logic_vector(15 downto 0);\r
- FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
- FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component frmctr_check;\r
-\r
- component apv_pc_nc_alu is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic;\r
- START_IN : in std_logic;\r
- MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
- CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
- LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
- EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
- BUF_GOOD_IN : in std_logic;\r
- BUF_BAD_IN : in std_logic;\r
- BUF_IGNORE_IN : in std_logic;\r
- ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
- DO_HEADER_IN : in std_logic;\r
- DO_ERROR_IN : in std_logic;\r
- EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
- RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
- RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
- PED_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_DATA_IN : in std_logic_vector(17 downto 0);\r
- FRAME_IN : in std_logic;\r
- FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
- WE_OUT : out std_logic;\r
- COUNT_OUT : out std_logic_vector(9 downto 0);\r
- ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component apv_pc_nc_alu;\r
-\r
- component comp14bit is\r
- port( DATAA : in std_logic_vector(13 downto 0); \r
- DATAB : in std_logic_vector(13 downto 0); \r
- CLOCK : in std_logic; \r
- CLOCKEN : in std_logic; \r
- ACLR : in std_logic; \r
- AGEB : out std_logic\r
- );\r
- end component;\r
-\r
- component input_bram is\r
- port( WRADDRESS : in std_logic_vector(10 downto 0); \r
- RDADDRESS : in std_logic_vector(10 downto 0); \r
- DATA : in std_logic_vector(17 downto 0); \r
- WE : in std_logic;\r
- RDCLOCK : in std_logic; \r
- RDCLOCKEN : in std_logic; \r
- RESET : in std_logic; \r
- WRCLOCK : in std_logic; \r
- WRCLOCKEN : in std_logic; \r
- Q : out std_logic_vector(17 downto 0)\r
- );\r
- end component;\r
-\r
- component frame_status_mem is\r
- port( WRADDRESS : in std_logic_vector(3 downto 0); \r
- DATA : in std_logic_vector(11 downto 0);\r
- WRCLOCK : in std_logic;\r
- WE : in std_logic;\r
- WRCLOCKEN : in std_logic;\r
- RDADDRESS : in std_logic_vector(3 downto 0);\r
- RDCLOCK : in std_logic;\r
- RDCLOCKEN : in std_logic;\r
- RESET : in std_logic;\r
- Q : out std_logic_vector(11 downto 0)\r
- );\r
- end component;\r
-\r
- component adder_6bit is\r
- port( DATAA : in std_logic_vector(5 downto 0); \r
- DATAB : in std_logic_vector(5 downto 0); \r
- CLOCK : in std_logic; \r
- RESET : in std_logic; \r
- CLOCKEN : in std_logic; \r
- RESULT : out std_logic_vector(5 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_lock_sm is\r
- port( CLK_APV_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- SYNC_IN : in std_logic; -- start APV synchronisation\r
- ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
- TIMED_IN : in std_logic; -- synchronisation timeout\r
- MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
- LOCKED_IN : in std_logic; -- enough good tickmarks\r
- TICK_IN : in std_logic; -- tickmark from digital parser\r
- HEADER_IN : in std_logic; -- header from digital parser\r
- FLATLINE_IN : in std_logic; -- flatline from digital parser\r
- RST_PC_OUT : out std_logic; -- reset period counter\r
- RST_TC_OUT : out std_logic; -- reset timeout counter\r
- INC_TC_OUT : out std_logic;\r
- RST_LC_OUT : out std_logic; -- reset lock counter\r
- INC_LC_OUT : out std_logic;\r
- UNKNOWN_OUT : out std_logic;\r
- BADADC_OUT : out std_logic; -- ADC data invalid\r
- LOCKED_OUT : out std_logic;\r
- LOST_OUT : out std_logic;\r
- NOSYNC_OUT : out std_logic;\r
- NOAPV_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
- end component;\r
-\r
- component apv_digital is\r
- port( CLK_APV_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
- BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
- BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
- FL_LOW_IN : in std_logic_vector(11 downto 0);\r
- FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
- BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
- BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
- BIT_HIGH_OUT : out std_logic;\r
- BIT_LOW_OUT : out std_logic;\r
- TICKMARK_OUT : out std_logic;\r
- HEADER_OUT : out std_logic;\r
- FLAT_LINE_OUT : out std_logic\r
- );\r
- end component;\r
-\r
- component eds_buffer_dpram is\r
- port( WRADDRESS : in std_logic_vector(3 downto 0); \r
- DATA : in std_logic_vector(39 downto 0); \r
- WRCLOCK : in std_logic; \r
- WE : in std_logic; \r
- WRCLOCKEN : in std_logic; \r
- RDADDRESS : in std_logic_vector(3 downto 0); \r
- RDCLOCK : in std_logic; \r
- RDCLOCKEN : in std_logic; \r
- RESET : in std_logic; \r
- Q : out std_logic_vector(39 downto 0)\r
- );\r
- end component;\r
+component logic_analyzer is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- control signals\r
+ ARM_IN : in std_logic; -- arm the machine\r
+ TRG_IN : in std_logic; -- trigger the data acquisition\r
+ MAX_SAMPLE_IN : in std_logic_vector(9 downto 0);\r
+ -- status signals\r
+ SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
+ SM_CE_OUT : out std_logic;\r
+ SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
+ CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
+ RUN_OUT : out std_logic; -- ready for trigger\r
+ SAMPLE_OUT : out std_logic; -- data acquisition running\r
+ READY_OUT : out std_logic; -- data acquisition is finished\r
+ LAST_OUT : out std_logic; -- last data word of sampling\r
+ -- Status lines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component logic_analyzer;\r
+\r
+component onewire_spare_one is\r
+port(\r
+ ADDRESS : in std_logic_vector(2 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component onewire_spare_one;\r
+\r
+component adc_onewire_map_mem is\r
+port(\r
+ ADDRESS : in std_logic_vector(6 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component adc_onewire_map_mem;\r
+\r
+component adc_channel_select is\r
+port(\r
+ RESET_IN : in std_logic;\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
+ ADC_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_0_IN : in std_logic_vector(11 downto 0);\r
+ ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_channel_select;\r
+\r
+component slv_adc_snoop is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_adc_snoop;\r
+\r
+component adc_snoop_mem is\r
+port(\r
+ WRADDRESS : in std_logic_vector(9 downto 0);\r
+ RDADDRESS : in std_logic_vector(9 downto 0);\r
+ DATA : in std_logic_vector(15 downto 0);\r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_snoop_mem;\r
+\r
+component max_data is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ TODO_3_IN : in std_logic_vector(3 downto 0);\r
+ TODO_2_IN : in std_logic_vector(3 downto 0);\r
+ TODO_1_IN : in std_logic_vector(3 downto 0);\r
+ TODO_0_IN : in std_logic_vector(3 downto 0);\r
+ TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component max_data;\r
+\r
+component comp4bit is\r
+port(\r
+ DATAA : in std_logic_vector(3 downto 0);\r
+ DATAB : in std_logic_vector(3 downto 0);\r
+ AGTB : out std_logic\r
+);\r
+end component comp4bit;\r
+\r
+component slv_register_bank is\r
+generic(\r
+ RESET_VALUE : std_logic_vector(15 downto 0) := x"0001"\r
+);\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_register_bank;\r
+\r
+component pulse_stretch is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ PULSE_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component pulse_stretch;\r
+\r
+component apv_adc_map_mem is\r
+port(\r
+ ADDRESS : in std_logic_vector(6 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component apv_adc_map_mem;\r
+\r
+component adc_apv_map_mem is\r
+port(\r
+ ADDRESS : in std_logic_vector(6 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component adc_apv_map_mem;\r
+\r
+component ped_thr_true is\r
+port(\r
+ DATAINA : in std_logic_vector(17 downto 0);\r
+ DATAINB : in std_logic_vector(17 downto 0);\r
+ ADDRESSA : in std_logic_vector(6 downto 0);\r
+ ADDRESSB : in std_logic_vector(6 downto 0);\r
+ CLOCKA : in std_logic;\r
+ CLOCKB : in std_logic;\r
+ CLOCKENA : in std_logic;\r
+ CLOCKENB : in std_logic;\r
+ WRA : in std_logic;\r
+ WRB : in std_logic;\r
+ RESETA : in std_logic;\r
+ RESETB : in std_logic;\r
+ QA : out std_logic_vector(17 downto 0);\r
+ QB : out std_logic_vector(17 downto 0)\r
+);\r
+end component ped_thr_true;\r
+\r
+component slv_ped_thr_mem is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_ped_thr_mem;\r
+\r
+component reset_handler is\r
+port( \r
+ CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
+ RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
+ CLK_IN : in std_logic;\r
+ TRB_RESET_IN : in std_logic;\r
+ RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component reset_handler;\r
+\r
+component pll_40m is\r
+port( \r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ DPAMODE : in std_logic;\r
+ DPHASE0 : in std_logic;\r
+ DPHASE1 : in std_logic;\r
+ DPHASE2 : in std_logic;\r
+ DPHASE3 : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+);\r
+end component pll_40m;\r
+\r
+component dll_100m is\r
+port( \r
+ CLK : in std_logic;\r
+ RESETN : in std_logic;\r
+ ALUHOLD : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+);\r
+end component dll_100m;\r
+\r
+component state_sync is\r
+port( \r
+ STATE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ STATE_B_OUT : out std_logic\r
+ );\r
+end component state_sync;\r
+\r
+component pulse_sync is\r
+port( \r
+ CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+);\r
+end component pulse_sync;\r
+\r
+component rich_trb is\r
+port( \r
+ CLK100M_IN : in std_logic;\r
+ SYSCLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_PRESENT_IN : in std_logic;\r
+ SD_TXDIS_OUT : out std_logic;\r
+ SD_LOS_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic;\r
+ -- common regIO status / control registers\r
+-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI\r
+ COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI\r
+-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT : out std_logic_vector(63 downto 0);\r
+ STATUS_IN : in std_logic_vector(127 downto 0);\r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_RECEIVED_OUT : out std_logic;\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_IN : in std_logic;\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_INT_TRG_UPDATE_OUT : out std_logic;\r
+ TIMING_TRG_FOUND_IN : in std_logic;\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_OUT : out std_logic; -- gimme data!\r
+ IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_IN : in std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern\r
+ -- regIO bus\r
+-- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+-- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+-- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0);\r
+ REGIO_DATAREADY_IN : in std_logic;\r
+ REGIO_NO_MORE_DATA_IN : in std_logic;\r
+ REGIO_WRITE_ACK_IN : in std_logic;\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic;\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ -- status LEDs\r
+ LED_LINK_STAT : out std_logic;\r
+ LED_LINK_TXD : out std_logic;\r
+ LED_LINK_RXD : out std_logic;\r
+ LINK_BSM_OUT : out std_logic_vector(3 downto 0);\r
+ RESET_OUT : out std_logic;\r
+ -- Debug\r
+ DEBUG : out std_logic_vector(63 downto 0)\r
+);\r
+end component rich_trb;\r
+\r
+component slave_bus is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs\r
+ BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT : out std_logic;\r
+ SPI_ADC0_SCK_OUT : out std_logic;\r
+ SPI_ADC0_SDO_OUT : out std_logic;\r
+ ADC0_PLL_LOCKED_IN : in std_logic;\r
+ ADC0_PD_OUT : out std_logic;\r
+ ADC0_RST_OUT : out std_logic;\r
+ ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC0_CLK_IN : in std_logic;\r
+ ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV0_RST_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT : out std_logic;\r
+ SPI_ADC1_SCK_OUT : out std_logic;\r
+ SPI_ADC1_SDO_OUT : out std_logic;\r
+ ADC1_PLL_LOCKED_IN : in std_logic;\r
+ ADC1_PD_OUT : out std_logic;\r
+ ADC1_RST_OUT : out std_logic;\r
+ ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC1_CLK_IN : in std_logic;\r
+ ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV1_RST_OUT : out std_logic;\r
+ -- User specific inputs / outputs\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- pedestal interface\r
+ PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
+ PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- threshold interface\r
+ THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
+ THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- APV control / status\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- some control signals\r
+ CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
+ STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
+ -- temporary stuff\r
+ TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
+ TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
+ -- Debug\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+);\r
+end component slave_bus;\r
+\r
+component oddrxc is\r
+port( \r
+ DA : in std_logic;\r
+ DB : in std_logic;\r
+ CLK : in std_logic;\r
+ RST : in std_logic;\r
+ Q : out std_logic\r
+);\r
+end component oddrxc;\r
+\r
+component apv_trgctrl is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ -- Triggers\r
+ SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
+ TRG_FOUND_OUT : out std_logic; -- trigger found\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ -- slow control settings\r
+ TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- TRB LVL1 trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
+ TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
+ TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
+ TRB_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ TRB_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ TRB_LD_COUNTER_IN : in std_logic;\r
+ -- EDS signals\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
+ EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
+ EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
+ EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
+ EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
+ -- APV signals\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component apv_trgctrl;\r
+\r
+component ped_corr_ctrl is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control registers\r
+ -- EDS buffer -- back to previous source stage\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : in std_logic;\r
+ EDS_DONE_OUT : out std_logic;\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ DHDR_STORE_OUT : out std_logic;\r
+ DHDR_BUF_FULL_IN : in std_logic;\r
+ FIFO_SPACE_REQ_OUT : out std_logic_vector(11 downto 0);\r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : out std_logic;\r
+ BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
+ BUF_START_IN : in std_logic_vector(15 downto 0);\r
+ -- raw data\r
+ BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
+ -- Pedestal data\r
+ PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- Threshold data\r
+ THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- processed data\r
+ FIFO_START_OUT : out std_logic;\r
+ FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component ped_corr_ctrl;\r
+\r
+component ipu_fifo_stage is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals\r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0);\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component ipu_fifo_stage;\r
+\r
+component ipu_dummy is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals\r
+ MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
+ MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
+ CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ -- DHDR buffer\r
+ LVL1_FIFO_RD_OUT : out std_logic;\r
+ LVL1_FIFO_EMPTY_IN : in std_logic;\r
+ LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component ipu_dummy;\r
+\r
+component reboot_handler is\r
+port( \r
+ RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ REBOOT_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component reboot_handler;\r
+\r
+component real_trg_handler is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter\r
+ LVL1_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_LD_COUNTER_IN : in std_logic;\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component real_trg_handler;\r
+\r
+component apv_trg_handler is\r
+port( \r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
+ APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_TRGSENT_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_trg_handler;\r
+\r
+component apv_sync_handler is\r
+port( \r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic; -- signal for statemachines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_sync_handler;\r
+\r
+component eds_buf is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ -- EDS input, all synced to CLK_IN\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
+ EDS_WE_IN : in std_logic; -- EDS write enable\r
+ EDS_DONE_IN : in std_logic; -- release EDS\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ EDS_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component eds_buf;\r
+\r
+component adc_pll is\r
+port( \r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLKOP : out std_logic;\r
+ LOCK : out std_logic\r
+);\r
+end component adc_pll;\r
+\r
+component adc_ch_in is\r
+port( \r
+ DEL : in std_logic_vector(3 downto 0);\r
+ ECLK : in std_logic;\r
+ SCLK : in std_logic;\r
+ RST : in std_logic;\r
+ DATA : in std_logic_vector(0 downto 0);\r
+ Q : out std_logic_vector(1 downto 0)\r
+);\r
+End component adc_ch_in;\r
+\r
+component adc_twochannels is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock\r
+ DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
+ DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
+ DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
+ DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
+ STORE_OUT : out std_logic;\r
+ SWAP_OUT : out std_logic;\r
+ CLOCK_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_twochannels;\r
+\r
+component apv_locker is\r
+port( \r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN\r
+ ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
+ SYNC_IN : in std_logic; -- sync trigger input\r
+ APV_ON_IN : in std_logic; -- this APV channel is switched on\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
+ STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
+ STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
+ STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
+ STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
+ STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
+ STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
+ STATUS_TICKMARK_OUT : out std_logic;\r
+ FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
+ FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
+ FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
+ FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
+ FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
+ FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
+ APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
+ APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
+ APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
+ APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
+ APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
+ APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer\r
+ APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_locker;\r
+\r
+component apv_raw_buffer is\r
+port( \r
+ CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
+ RESET_IN : in std_logic;\r
+ FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
+ ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
+ ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
+ ADC_LAST_IN : in std_logic; -- last channel signal\r
+ ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
+ ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
+ ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
+ ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
+ BUF_CLK_IN : in std_logic; -- read clock\r
+ BUF_RESET_IN : in std_logic; -- 100MHz reset\r
+ BUF_START_OUT : out std_logic; -- one block starts writing\r
+ BUF_READY_OUT : out std_logic; -- one block has been written\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
+ BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
+ BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
+ BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
+ BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
+ BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
+ BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
+ BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
+ BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler\r
+ BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_raw_buffer;\r
+\r
+-- moved to trb_net_components.vhd\r
+--\r
+--component slv_register is\r
+--generic(\r
+-- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" \r
+--);\r
+--port( \r
+-- CLK_IN : in std_logic;\r
+-- RESET_IN : in std_logic;\r
+-- BUSY_IN : in std_logic;\r
+-- -- Slave bus\r
+-- SLV_READ_IN : in std_logic;\r
+-- SLV_WRITE_IN : in std_logic;\r
+-- SLV_BUSY_OUT : out std_logic;\r
+-- SLV_ACK_OUT : out std_logic;\r
+-- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+-- -- I/O to the backend\r
+-- REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+-- -- Status lines\r
+-- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+--);\r
+--end component slv_register;\r
+\r
+component slv_half_register is\r
+generic( \r
+ RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" \r
+);\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
+ CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component slv_half_register;\r
+\r
+component i2c_master is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component i2c_master;\r
+\r
+component slv_onewire_memory is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+);\r
+end component slv_onewire_memory;\r
+\r
+component spi_real_slim is\r
+port( \r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+);\r
+end component spi_real_slim;\r
+\r
+component spi_adc_master is\r
+generic( \r
+ RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" \r
+);\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- ADC connections\r
+ ADC_LOCKED_IN : in std_logic;\r
+ ADC_PD_OUT : out std_logic;\r
+ ADC_RST_OUT : out std_logic;\r
+ ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ -- APV connections\r
+ APV_RST_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component spi_adc_master;\r
+\r
+component i2c_slim is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- I2C command / setup\r
+ I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
+ ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
+ I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
+ I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
+ STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
+ I2C_BUSY_OUT : out std_logic;\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Debug\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component i2c_slim;\r
+\r
+component i2c_gstart is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ DOSTART_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ SDONE_OUT : out std_logic;\r
+ SOK_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+);\r
+end component i2c_gstart;\r
+\r
+component i2c_sendb is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ DOBYTE_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ I2C_BYTE_IN : in std_logic_vector(8 downto 0);\r
+ I2C_BACK_OUT : out std_logic_vector(8 downto 0);\r
+ SDA_IN : in std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+-- SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ BDONE_OUT : out std_logic;\r
+ BOK_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+);\r
+end component i2c_sendb;\r
+\r
+component onewire_master is\r
+generic( \r
+ CLK_PERIOD : integer := 10 -- clock perion in nanoseconds\r
+);\r
+port( \r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ READOUT_ENABLE_IN : in std_logic;\r
+ -- connection to 1-wire interface (16 APV FEs)\r
+ ONEWIRE : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE : inout std_logic;\r
+ -- connection to external DPRAM for slow control readout\r
+ BP_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ WRITE_OUT : out std_logic;\r
+ BUSY_OUT : out std_logic;\r
+ -- debug\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ STAT : out std_logic_vector(15 downto 0)\r
+);\r
+end component onewire_master;\r
+\r
+component slv_onewire_dpram\r
+port( \r
+ WRADDRESS : in std_logic_vector(6 downto 0);\r
+ RDADDRESS : in std_logic_vector(5 downto 0);\r
+ DATA : in std_logic_vector(15 downto 0);\r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(31 downto 0)\r
+);\r
+end component slv_onewire_dpram;\r
+\r
+component fifo_2kx27 is\r
+port( \r
+ DATA : in std_logic_vector(26 downto 0);\r
+ CLOCK : in std_logic;\r
+ WREN : in std_logic;\r
+ RDEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(26 downto 0);\r
+ WCNT : out std_logic_vector(11 downto 0);\r
+ EMPTY : out std_logic;\r
+ FULL : out std_logic\r
+);\r
+end component fifo_2kx27;\r
+\r
+component fifo_1kx18 is\r
+port(\r
+ DATA : in std_logic_vector(17 downto 0); \r
+ CLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(17 downto 0); \r
+ WCNT : out std_logic_vector(10 downto 0); \r
+ EMPTY : out std_logic; \r
+ FULL : out std_logic\r
+);\r
+end component fifo_1kx18;\r
+\r
+component decoder_8bit is\r
+port( \r
+ ADDRESS : in std_logic_vector(7 downto 0);\r
+ Q : out std_logic_vector(3 downto 0)\r
+);\r
+end component decoder_8bit;\r
+\r
+component adder_5bit is\r
+port( \r
+ DATAA : in std_logic_vector(4 downto 0);\r
+ DATAB : in std_logic_vector(4 downto 0);\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLOCKEN : in std_logic;\r
+ RESULT : out std_logic_vector(4 downto 0)\r
+);\r
+end component adder_5bit;\r
+\r
+component adder_16bit is\r
+port( \r
+ DATAA : in std_logic_vector(15 downto 0);\r
+ DATAB : in std_logic_vector(15 downto 0);\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLOCKEN : in std_logic;\r
+ RESULT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adder_16bit;\r
+\r
+component suber_12bit is\r
+port( \r
+ DATAA : in std_logic_vector(11 downto 0);\r
+ DATAB : in std_logic_vector(11 downto 0);\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLOCKEN : in std_logic;\r
+ RESULT : out std_logic_vector(11 downto 0)\r
+);\r
+end component suber_12bit;\r
+\r
+component comp_12bit is\r
+port(\r
+ DATAA : in std_logic_vector(11 downto 0); \r
+ DATAB : in std_logic_vector(11 downto 0); \r
+ CLOCK : in std_logic; \r
+ CLOCKEN : in std_logic; \r
+ ACLR : in std_logic; \r
+ AGTB : out std_logic\r
+);\r
+end component comp_12bit;\r
+\r
+component buf_toc is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
+ BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
+ WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
+ FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
+ BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
+ GOODDATA_OUT : out std_logic;\r
+ BADDATA_OUT : out std_logic;\r
+ NODATA_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component buf_toc;\r
+\r
+component ref_row_sel is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ READY_IN : in std_logic_vector(15 downto 0);\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAME_0_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_1_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_2_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_3_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_4_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_5_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_6_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_7_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_8_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_9_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_10_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_11_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_12_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_13_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_14_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_15_IN : in std_logic_vector(11 downto 0);\r
+ VALID_BUFS_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
+ APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
+ APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
+ REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component ref_row_sel;\r
+\r
+component frmctr_check is\r
+port( \r
+ CLK_IN : in std_logic;\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
+ FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component frmctr_check;\r
+\r
+component apv_pc_nc_alu is\r
+port( \r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
+ CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
+ LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ BUF_GOOD_IN : in std_logic;\r
+ BUF_BAD_IN : in std_logic;\r
+ BUF_IGNORE_IN : in std_logic;\r
+ ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
+ DO_HEADER_IN : in std_logic;\r
+ DO_ERROR_IN : in std_logic;\r
+ SUPPRESS_IN : in std_logic;\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
+ RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
+ PED_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_DATA_IN : in std_logic_vector(17 downto 0);\r
+ FRAME_IN : in std_logic;\r
+ FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
+ WE_OUT : out std_logic;\r
+ COUNT_OUT : out std_logic_vector(9 downto 0);\r
+ ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_pc_nc_alu;\r
+\r
+component comp14bit is\r
+port( \r
+ DATAA : in std_logic_vector(13 downto 0);\r
+ DATAB : in std_logic_vector(13 downto 0);\r
+ CLOCK : in std_logic;\r
+ CLOCKEN : in std_logic;\r
+ ACLR : in std_logic;\r
+ AGEB : out std_logic\r
+); \r
+end component comp14bit;\r
+\r
+component input_bram is\r
+port( \r
+ WRADDRESS : in std_logic_vector(10 downto 0);\r
+ RDADDRESS : in std_logic_vector(10 downto 0);\r
+ DATA : in std_logic_vector(17 downto 0);\r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(17 downto 0)\r
+);\r
+end component input_bram;\r
+\r
+component frame_status_mem is\r
+port( \r
+ WRADDRESS : in std_logic_vector(3 downto 0);\r
+ DATA : in std_logic_vector(11 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ WE : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ RDADDRESS : in std_logic_vector(3 downto 0);\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(11 downto 0)\r
+);\r
+end component frame_status_mem;\r
+\r
+component adder_6bit is\r
+port( \r
+ DATAA : in std_logic_vector(5 downto 0);\r
+ DATAB : in std_logic_vector(5 downto 0);\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLOCKEN : in std_logic;\r
+ RESULT : out std_logic_vector(5 downto 0)\r
+);\r
+end component adder_6bit;\r
+\r
+component apv_lock_sm is\r
+port( \r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SYNC_IN : in std_logic; -- start APV synchronisation\r
+ ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
+ TIMED_IN : in std_logic; -- synchronisation timeout\r
+ MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
+ LOCKED_IN : in std_logic; -- enough good tickmarks\r
+ TICK_IN : in std_logic; -- tickmark from digital parser\r
+ HEADER_IN : in std_logic; -- header from digital parser\r
+ FLATLINE_IN : in std_logic; -- flatline from digital parser\r
+ RST_PC_OUT : out std_logic; -- reset period counter\r
+ RST_TC_OUT : out std_logic; -- reset timeout counter\r
+ INC_TC_OUT : out std_logic;\r
+ RST_LC_OUT : out std_logic; -- reset lock counter\r
+ INC_LC_OUT : out std_logic;\r
+ UNKNOWN_OUT : out std_logic;\r
+ BADADC_OUT : out std_logic; -- ADC data invalid\r
+ LOCKED_OUT : out std_logic;\r
+ LOST_OUT : out std_logic;\r
+ NOSYNC_OUT : out std_logic;\r
+ NOAPV_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component apv_lock_sm;\r
+\r
+component apv_digital is\r
+port( \r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_HIGH_OUT : out std_logic;\r
+ BIT_LOW_OUT : out std_logic;\r
+ TICKMARK_OUT : out std_logic;\r
+ HEADER_OUT : out std_logic;\r
+ FLAT_LINE_OUT : out std_logic\r
+);\r
+end component apv_digital;\r
+\r
+component eds_buffer_dpram is\r
+port( \r
+ WRADDRESS : in std_logic_vector(3 downto 0);\r
+ DATA : in std_logic_vector(39 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ WE : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ RDADDRESS : in std_logic_vector(3 downto 0);\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(39 downto 0)\r
+);\r
+end component eds_buffer_dpram;\r
\r
end package;\r
\r
-- Down in the Dumps...\r
\r
+--component fifo_16x11 is\r
+--port( \r
+-- DATA : in std_logic_vector(10 downto 0);\r
+-- CLOCK : in std_logic;\r
+-- WREN : in std_logic;\r
+-- RDEN : in std_logic;\r
+-- RESET : in std_logic;\r
+-- Q : out std_logic_vector(10 downto 0);\r
+-- WCNT : out std_logic_vector(4 downto 0);\r
+-- EMPTY : out std_logic;\r
+-- FULL : out std_logic\r
+--);\r
+--end component fifo_16x11;\r
+\r
+--component dhdr_buf is\r
+--port( \r
+-- CLK_IN : in std_logic; -- 100MHz master clock\r
+-- RESET_IN : in std_logic;\r
+-- -- DHDR information block\r
+-- DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
+-- DHDR_WE_IN : in std_logic; -- EDS write enable\r
+-- DHDR_DONE_IN : in std_logic; -- release EDS\r
+-- DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
+-- DHDR_AVAILABLE_OUT : out std_logic;\r
+-- -- trigger busy information\r
+-- BUF_FULL_OUT : out std_logic;\r
+-- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+-- -- Debug signals\r
+-- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+--);\r
+--end component dhdr_buf;\r
+\r
+--component dhdr_buffer_dpram is\r
+--port( \r
+-- WRADDRESS : in std_logic_vector(3 downto 0);\r
+-- DATA : in std_logic_vector(47 downto 0);\r
+-- WRCLOCK : in std_logic;\r
+-- WE : in std_logic;\r
+-- WRCLOCKEN : in std_logic;\r
+-- RDADDRESS : in std_logic_vector(3 downto 0);\r
+-- RDCLOCK : in std_logic;\r
+-- RDCLOCKEN : in std_logic;\r
+-- RESET : in std_logic;\r
+-- Q : out std_logic_vector(47 downto 0)\r
+--);\r
+--end component;\r
use work.adcmv3_components.all;\r
\r
entity apv_digital is\r
- port( CLK_APV_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
- BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
- BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
- FL_LOW_IN : in std_logic_vector(11 downto 0);\r
- FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
- BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
- BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
- BIT_HIGH_OUT : out std_logic;\r
- BIT_LOW_OUT : out std_logic;\r
- TICKMARK_OUT : out std_logic;\r
- HEADER_OUT : out std_logic;\r
- FLAT_LINE_OUT : out std_logic\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_HIGH_OUT : out std_logic;\r
+ BIT_LOW_OUT : out std_logic;\r
+ TICKMARK_OUT : out std_logic;\r
+ HEADER_OUT : out std_logic;\r
+ FLAT_LINE_OUT : out std_logic\r
+ );\r
end;\r
\r
architecture behavioral of apv_digital is\r
\r
- signal next_bit_low : std_logic;\r
- signal bit_low : std_logic;\r
- signal next_bit_high : std_logic;\r
- signal bit_high : std_logic;\r
- signal next_bit_data : std_logic;\r
- signal bit_data : std_logic_vector(11 downto 0);\r
- signal next_bit_valid : std_logic;\r
- signal bit_valid : std_logic_vector(11 downto 0);\r
- signal next_fl_low : std_logic;\r
- signal fl_low : std_logic;\r
- signal next_fl_high : std_logic;\r
- signal fl_high : std_logic;\r
- signal next_fl_found : std_logic;\r
- signal fl_found : std_logic_vector(2 downto 0);\r
- signal next_flat_line : std_logic;\r
- signal flat_line : std_logic;\r
- signal next_tickmark : std_logic;\r
- signal tickmark : std_logic;\r
- signal next_header : std_logic;\r
- signal header : std_logic;\r
- \r
+signal next_bit_low : std_logic;\r
+signal bit_low : std_logic;\r
+signal next_bit_high : std_logic;\r
+signal bit_high : std_logic;\r
+signal next_bit_data : std_logic;\r
+signal bit_data : std_logic_vector(11 downto 0);\r
+signal next_bit_valid : std_logic;\r
+signal bit_valid : std_logic_vector(11 downto 0);\r
+signal next_fl_low : std_logic;\r
+signal fl_low : std_logic;\r
+signal next_fl_high : std_logic;\r
+signal fl_high : std_logic;\r
+signal next_fl_found : std_logic;\r
+signal fl_found : std_logic_vector(2 downto 0);\r
+signal next_flat_line : std_logic;\r
+signal flat_line : std_logic;\r
+signal next_tickmark : std_logic;\r
+signal tickmark : std_logic;\r
+signal next_header : std_logic;\r
+signal header : std_logic;\r
+\r
begin\r
\r
-- ADC data is registered already, so we can operate on the inputs directly.\r
\r
--------------------------------------------------------------------------------------\r
--- compare ADC raw data against "bit low" threshold, \r
+-- compare ADC raw data against "bit low" threshold,\r
-- generate combinatorial "low" bit\r
THE_BL_COMP: process( adc_raw_in, bit_low_in )\r
begin\r
end if;\r
end process THE_BL_COMP;\r
\r
--- compare ADC raw data against "bit high" threshold, \r
+-- compare ADC raw data against "bit high" threshold,\r
--generate combinatorial "high" bit\r
THE_BH_COMP: process( adc_raw_in, bit_high_in )\r
begin\r
use work.adcmv3_components.all;\r
\r
entity apv_lock_sm is\r
- port( CLK_APV_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- SYNC_IN : in std_logic; -- start APV synchronisation\r
- ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
- TIMED_IN : in std_logic; -- synchronisation timeout\r
- MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
- LOCKED_IN : in std_logic; -- enough good tickmarks\r
- TICK_IN : in std_logic; -- tickmark from digital parser\r
- HEADER_IN : in std_logic; -- header from digital parser\r
- FLATLINE_IN : in std_logic; -- flatline from digital parser\r
- RST_PC_OUT : out std_logic; -- reset period counter\r
- RST_TC_OUT : out std_logic; -- reset timeout counter\r
- INC_TC_OUT : out std_logic;\r
- RST_LC_OUT : out std_logic; -- reset lock counter\r
- INC_LC_OUT : out std_logic;\r
- UNKNOWN_OUT : out std_logic; -- status unknown\r
- BADADC_OUT : out std_logic; -- ADC data invalid\r
- LOCKED_OUT : out std_logic; -- APV locked successfully\r
- LOST_OUT : out std_logic; -- APV sync is lost\r
- NOSYNC_OUT : out std_logic; -- APV sync failed\r
- NOAPV_OUT : out std_logic; -- no APV connected\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SYNC_IN : in std_logic; -- start APV synchronisation\r
+ ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
+ TIMED_IN : in std_logic; -- synchronisation timeout\r
+ MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
+ LOCKED_IN : in std_logic; -- enough good tickmarks\r
+ TICK_IN : in std_logic; -- tickmark from digital parser\r
+ HEADER_IN : in std_logic; -- header from digital parser\r
+ FLATLINE_IN : in std_logic; -- flatline from digital parser\r
+ RST_PC_OUT : out std_logic; -- reset period counter\r
+ RST_TC_OUT : out std_logic; -- reset timeout counter\r
+ INC_TC_OUT : out std_logic;\r
+ RST_LC_OUT : out std_logic; -- reset lock counter\r
+ INC_LC_OUT : out std_logic;\r
+ UNKNOWN_OUT : out std_logic; -- status unknown\r
+ BADADC_OUT : out std_logic; -- ADC data invalid\r
+ LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ LOST_OUT : out std_logic; -- APV sync is lost\r
+ NOSYNC_OUT : out std_logic; -- APV sync failed\r
+ NOAPV_OUT : out std_logic; -- no APV connected\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
end;\r
\r
architecture behavioral of apv_lock_sm is\r
\r
- -- State definition\r
- -- SLEEP : initial reset state\r
- -- CLEAR : clear counters and registers\r
- -- UWSYNC : wait for SYNC_IN to deassert\r
- -- USYNC : teaching phase, not synchronized yet\r
- -- U_BADM : tickmark found, but local counter mismatch\r
- -- U_BADP : local counter match, but no tickmark found\r
- -- U_GOOD : local counter and tickmark match\r
- -- U_TIME : locking timed out\r
- -- U_FLAT : no APV connected (open input)\r
- -- U_ADC : ADC data is marked invaled (ser2par failed)\r
- -- SYNCED : APV is locked, normal operation state\r
- -- S_BADM : spurious tickmark found => fatal\r
- -- S_BADM : missing tickmark => fatal\r
- -- S_BADD : spurious data frame found, or bad tickmark after dataframe => fatal\r
- -- S_GOOD : local counter and tickmark match\r
- -- S_DATA : data frame header found at correct position\r
- -- S_FR0 : first tickmark period of data frame\r
- -- S_FR1 : second tickmark period of data frame\r
- -- S_FR2 : third tickmark period of data frame\r
- -- S_FR3 : fourth tickmark period of data frame\r
- -- S_ADC : ADC data is marked invalid (ser2par failed)\r
- -- S_LOST : lock lost in normal operation => fatal\r
+-- State definition\r
+-- SLEEP : initial reset state\r
+-- CLEAR : clear counters and registers\r
+-- UWSYNC : wait for SYNC_IN to deassert\r
+-- USYNC : teaching phase, not synchronized yet\r
+-- U_BADM : tickmark found, but local counter mismatch\r
+-- U_BADP : local counter match, but no tickmark found\r
+-- U_GOOD : local counter and tickmark match\r
+-- U_TIME : locking timed out\r
+-- U_FLAT : no APV connected (open input)\r
+-- U_ADC : ADC data is marked invaled (ser2par failed)\r
+-- SYNCED : APV is locked, normal operation state\r
+-- S_BADM : spurious tickmark found => fatal\r
+-- S_BADM : missing tickmark => fatal\r
+-- S_BADD : spurious data frame found, or bad tickmark after dataframe => fatal\r
+-- S_GOOD : local counter and tickmark match\r
+-- S_DATA : data frame header found at correct position\r
+-- S_FR0 : first tickmark period of data frame\r
+-- S_FR1 : second tickmark period of data frame\r
+-- S_FR2 : third tickmark period of data frame\r
+-- S_FR3 : fourth tickmark period of data frame\r
+-- S_ADC : ADC data is marked invalid (ser2par failed)\r
+-- S_LOST : lock lost in normal operation => fatal\r
\r
- -- state machine signals\r
- type STATES is (SLEEP, CLEAR, USYNC, UWSYNC, U_BADM, U_BADP, U_GOOD, U_TIME, U_FLAT, U_ADC,\r
- SYNCED, S_BADP, S_BADM, S_GOOD, S_DATA, S_FR0, S_FR1, S_FR2, S_FR3,\r
- S_BADD, S_LOST, S_ADC);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+-- state machine signals\r
+type STATES is (SLEEP, CLEAR, USYNC, UWSYNC, U_BADM, U_BADP, U_GOOD, U_TIME, U_FLAT, U_ADC,\r
+ SYNCED, S_BADP, S_BADM, S_GOOD, S_DATA, S_FR0, S_FR1, S_FR2, S_FR3,\r
+ S_BADD, S_LOST, S_ADC);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- normal signals\r
+signal bsm : std_logic_vector(7 downto 0);\r
+signal debug : std_logic_vector(15 downto 0);\r
+signal next_rst_tc : std_logic;\r
+signal rst_tc : std_logic;\r
+signal next_inc_tc : std_logic;\r
+signal inc_tc : std_logic;\r
+signal next_rst_lc : std_logic;\r
+signal rst_lc : std_logic;\r
+signal next_inc_lc : std_logic;\r
+signal inc_lc : std_logic;\r
+signal next_rst_pc : std_logic;\r
+signal rst_pc : std_logic;\r
+signal next_unknown : std_logic;\r
+signal unknown : std_logic;\r
+signal next_badadc : std_logic;\r
+signal badadc : std_logic;\r
+signal next_locked : std_logic;\r
+signal locked : std_logic;\r
+signal next_lost : std_logic;\r
+signal lost : std_logic;\r
+signal next_nosync : std_logic;\r
+signal nosync : std_logic;\r
+signal next_noapv : std_logic;\r
+signal noapv : std_logic;\r
+signal next_dataframe : std_logic;\r
+signal dataframe : std_logic;\r
\r
- -- normal signals\r
- signal bsm : std_logic_vector(7 downto 0);\r
- signal debug : std_logic_vector(15 downto 0);\r
- signal next_rst_tc : std_logic;\r
- signal rst_tc : std_logic;\r
- signal next_inc_tc : std_logic;\r
- signal inc_tc : std_logic;\r
- signal next_rst_lc : std_logic;\r
- signal rst_lc : std_logic;\r
- signal next_inc_lc : std_logic;\r
- signal inc_lc : std_logic;\r
- signal next_rst_pc : std_logic;\r
- signal rst_pc : std_logic;\r
- signal next_unknown : std_logic;\r
- signal unknown : std_logic;\r
- signal next_badadc : std_logic;\r
- signal badadc : std_logic;\r
- signal next_locked : std_logic;\r
- signal locked : std_logic;\r
- signal next_lost : std_logic;\r
- signal lost : std_logic;\r
- signal next_nosync : std_logic;\r
- signal nosync : std_logic;\r
- signal next_noapv : std_logic;\r
- signal noapv : std_logic; \r
- signal next_dataframe : std_logic;\r
- signal dataframe : std_logic;\r
- \r
begin\r
\r
debug <= (others => '0');\r
\r
-- state machine for handling synchronisation\r
-- state registers\r
-STATE_MEM: process( clk_apv_in ) \r
+STATE_MEM: process( clk_apv_in )\r
begin\r
if( rising_edge(clk_apv_in) ) then\r
if( reset_in = '1' ) then\r
STATE_TRANSFORM: process( CURRENT_STATE, sync_in, match_in, tick_in, header_in, timed_in, locked_in, flatline_in, adc_valid_in )\r
begin\r
NEXT_STATE <= SLEEP; -- avoid latches\r
- next_rst_pc <= '0'; \r
- next_rst_lc <= '0'; \r
+ next_rst_pc <= '0';\r
+ next_rst_lc <= '0';\r
next_inc_lc <= '0';\r
- next_rst_tc <= '0'; \r
+ next_rst_tc <= '0';\r
next_inc_tc <= '0';\r
next_unknown <= '0';\r
next_badadc <= '0';\r
next_noapv <= '0';\r
next_dataframe <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( sync_in = '1' ) then\r
+ when SLEEP => if( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR; -- start synchronisation\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
NEXT_STATE <= SLEEP;\r
next_unknown <= '1';\r
end if;\r
- when CLEAR => NEXT_STATE <= UWSYNC;\r
+ when CLEAR => NEXT_STATE <= UWSYNC;\r
next_unknown <= '1';\r
- when UWSYNC => if ( (sync_in = '0') and (adc_valid_in = '1') ) then\r
+ when UWSYNC => if ( (sync_in = '0') and (adc_valid_in = '1') ) then\r
NEXT_STATE <= USYNC;\r
next_unknown <= '1';\r
elsif( (sync_in = '0') and (adc_valid_in = '0') ) then\r
NEXT_STATE <= UWSYNC;\r
next_unknown <= '1';\r
end if;\r
- when USYNC => if ( (timed_in = '0') and (tick_in = '1') and (match_in = '0') ) then\r
+ when USYNC => if ( (timed_in = '0') and (tick_in = '1') and (match_in = '0') ) then\r
NEXT_STATE <= U_BADM; -- local timer not correct\r
next_rst_pc <= '1';\r
next_inc_tc <= '1';\r
NEXT_STATE <= USYNC; -- wait for events\r
next_unknown <= '1';\r
end if;\r
- when U_BADM => NEXT_STATE <= USYNC;\r
+ when U_BADM => NEXT_STATE <= USYNC;\r
next_unknown <= '1';\r
- when U_BADP => NEXT_STATE <= USYNC;\r
+ when U_BADP => NEXT_STATE <= USYNC;\r
next_unknown <= '1';\r
- when U_GOOD => NEXT_STATE <= USYNC;\r
+ when U_GOOD => NEXT_STATE <= USYNC;\r
next_unknown <= '1';\r
- when U_FLAT => if( sync_in = '1' ) then\r
+ when U_FLAT => if( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR; -- next try\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
NEXT_STATE <= U_FLAT;\r
next_noapv <= '1';\r
end if;\r
- when U_TIME => if( sync_in = '1' ) then\r
+ when U_TIME => if( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR; -- next try\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
NEXT_STATE <= U_TIME;\r
next_nosync <= '1';\r
end if;\r
- when U_ADC => if( sync_in = '1' ) then\r
+ when U_ADC => if( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR; -- next try\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
NEXT_STATE <= U_ADC;\r
next_badadc <= '1';\r
end if;\r
- when SYNCED => if ( sync_in = '1' ) then\r
+ when SYNCED => if ( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
NEXT_STATE <= SYNCED;\r
next_locked <= '1';\r
end if;\r
- when S_GOOD => NEXT_STATE <= SYNCED;\r
+ when S_GOOD => NEXT_STATE <= SYNCED;\r
next_locked <= '1';\r
- when S_DATA => if( sync_in = '1' ) then\r
+ when S_DATA => if( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
next_dataframe <= '1';\r
next_locked <= '1';\r
end if;\r
- when S_FR0 => if ( sync_in = '1' ) then\r
+ when S_FR0 => if ( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
next_dataframe <= '1';\r
next_locked <= '1';\r
end if;\r
- when S_FR1 => if ( sync_in = '1' ) then\r
+ when S_FR1 => if ( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
next_dataframe <= '1';\r
next_locked <= '1';\r
end if;\r
- when S_FR2 => if ( sync_in = '1' ) then\r
+ when S_FR2 => if ( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
next_dataframe <= '1';\r
next_locked <= '1';\r
end if;\r
- when S_FR3 => if ( sync_in = '1' ) then\r
+ when S_FR3 => if ( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
next_dataframe <= '1';\r
next_locked <= '1';\r
end if;\r
- when S_BADD => NEXT_STATE <= S_LOST;\r
+ when S_BADD => NEXT_STATE <= S_LOST;\r
next_lost <= '1';\r
- when S_BADM => NEXT_STATE <= S_LOST;\r
+ when S_BADM => NEXT_STATE <= S_LOST;\r
next_lost <= '1';\r
- when S_BADP => NEXT_STATE <= S_LOST;\r
+ when S_BADP => NEXT_STATE <= S_LOST;\r
next_lost <= '1';\r
- when S_ADC => NEXT_STATE <= S_LOST;\r
+ when S_ADC => NEXT_STATE <= S_LOST;\r
next_lost <= '1';\r
- when S_LOST => if( sync_in = '1' ) then\r
+ when S_LOST => if( sync_in = '1' ) then\r
NEXT_STATE <= CLEAR; -- next try\r
next_rst_pc <= '1';\r
next_rst_lc <= '1';\r
NEXT_STATE <= S_LOST;\r
next_lost <= '1';\r
end if;\r
- when others => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
next_unknown <= '1';\r
end case;\r
end process STATE_TRANSFORM;\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm <= x"00";\r
- when CLEAR => bsm <= x"01";\r
- when UWSYNC => bsm <= x"20"; \r
- when USYNC => bsm <= x"02";\r
- when U_BADM => bsm <= x"03";\r
- when U_BADP => bsm <= x"04";\r
- when U_FLAT => bsm <= x"05";\r
- when U_GOOD => bsm <= x"06";\r
- when U_TIME => bsm <= x"07";\r
- when U_ADC => bsm <= x"08";\r
- when SYNCED => bsm <= x"09";\r
- when S_BADP => bsm <= x"0a";\r
- when S_BADM => bsm <= x"0b";\r
- when S_GOOD => bsm <= x"0c";\r
- when S_DATA => bsm <= x"0d";\r
- when S_FR0 => bsm <= x"0e";\r
- when S_FR1 => bsm <= x"0f";\r
- when S_FR2 => bsm <= x"10";\r
- when S_FR3 => bsm <= x"11";\r
- when S_BADD => bsm <= x"12";\r
- when S_ADC => bsm <= x"13";\r
- when S_LOST => bsm <= x"14";\r
- when others => bsm <= x"ff";\r
+ when SLEEP => bsm <= x"00";\r
+ when CLEAR => bsm <= x"01";\r
+ when UWSYNC => bsm <= x"20";\r
+ when USYNC => bsm <= x"02";\r
+ when U_BADM => bsm <= x"03";\r
+ when U_BADP => bsm <= x"04";\r
+ when U_FLAT => bsm <= x"05";\r
+ when U_GOOD => bsm <= x"06";\r
+ when U_TIME => bsm <= x"07";\r
+ when U_ADC => bsm <= x"08";\r
+ when SYNCED => bsm <= x"09";\r
+ when S_BADP => bsm <= x"0a";\r
+ when S_BADM => bsm <= x"0b";\r
+ when S_GOOD => bsm <= x"0c";\r
+ when S_DATA => bsm <= x"0d";\r
+ when S_FR0 => bsm <= x"0e";\r
+ when S_FR1 => bsm <= x"0f";\r
+ when S_FR2 => bsm <= x"10";\r
+ when S_FR3 => bsm <= x"11";\r
+ when S_BADD => bsm <= x"12";\r
+ when S_ADC => bsm <= x"13";\r
+ when S_LOST => bsm <= x"14";\r
+ when others => bsm <= x"ff";\r
end case;\r
end process STATE_DECODE;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
--- This block takes care of syncing in the APVs. Only "synced" APVs are allowed to deliver data streams \r
--- to the processing units. \r
+-- This block takes care of syncing in the APVs. Only "synced" APVs are allowed to deliver data streams\r
+-- to the processing units.\r
\r
entity apv_locker is\r
- port( CLK_APV_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to CLK_APV_IN\r
- ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
- -- Slow control input, mainly digital thresholds here\r
- SYNC_IN : in std_logic; -- sync pulse input \r
- APV_ON_IN : in std_logic; -- this APV channel is switched on\r
- BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
- BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
- FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
- FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
- -- Generic APV status outputs (valid only if ADC_CLK_IN is working!)\r
- STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
- STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
- STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
- STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
- STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
- STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
- STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
- STATUS_TICKMARK_OUT : out std_logic;\r
- -- Frame related status, to be stored in the raw status buffer\r
- -- Information is valid with APV_LAST_OUT, except FRAME_ERROR_OUT, FRAME_ROW_OUT and \r
- -- FRAME_CTR_OUT which are valid with beginning of APV_ANALOG_OUT.\r
- FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
- FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
- FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
- FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
- FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
- FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
- -- Channel related information, to be stored in the raw data buffer\r
- APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
- APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
- APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
- APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
- APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
- APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer \r
- APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
- -- Debug information\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to CLK_APV_IN\r
+ ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
+ -- Slow control input, mainly digital thresholds here\r
+ SYNC_IN : in std_logic; -- sync pulse input\r
+ APV_ON_IN : in std_logic; -- this APV channel is switched on\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
+ -- Generic APV status outputs (valid only if ADC_CLK_IN is working!)\r
+ STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
+ STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
+ STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
+ STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
+ STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
+ STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
+ STATUS_TICKMARK_OUT : out std_logic;\r
+ -- Frame related status, to be stored in the raw status buffer\r
+ -- Information is valid with APV_LAST_OUT, except FRAME_ERROR_OUT, FRAME_ROW_OUT and\r
+ -- FRAME_CTR_OUT which are valid with beginning of APV_ANALOG_OUT.\r
+ FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
+ FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
+ FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
+ FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
+ FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
+ FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
+ -- Channel related information, to be stored in the raw data buffer\r
+ APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
+ APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
+ APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
+ APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
+ APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
+ APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer\r
+ APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
+ -- Debug information\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of apv_locker is\r
\r
- -- normal signals\r
- signal lock_bsm : std_logic_vector(7 downto 0);\r
- signal tickmark_found : std_logic;\r
- signal header_found : std_logic;\r
- signal flatline_found : std_logic;\r
- signal status_unknown : std_logic;\r
- signal status_badadc : std_logic;\r
- signal status_locked : std_logic;\r
- signal status_lost : std_logic;\r
- signal status_nosync : std_logic;\r
- signal status_missing : std_logic;\r
- signal next_status_ignore : std_logic;\r
- signal status_ignore : std_logic;\r
- signal frame_flat : std_logic;\r
- signal next_frame_ovf : std_logic;\r
- signal frame_ovf : std_logic;\r
- signal next_frame_udf : std_logic;\r
- signal frame_udf : std_logic;\r
- signal frame_row : std_logic_vector(7 downto 0);\r
- signal frame_error : std_logic;\r
- signal bit_data : std_logic_vector(11 downto 0);\r
- signal bit_valid : std_logic_vector(11 downto 0);\r
-\r
- signal rst_pc_sm : std_logic;\r
- signal rst_pc_ctr : std_logic;\r
- signal pc_ctr : std_logic_vector(5 downto 0);\r
- signal next_pc_match : std_logic;\r
- signal pc_match : std_logic;\r
-\r
- signal rst_tc_sm : std_logic;\r
- signal inc_tc_sm : std_logic;\r
- signal tc_ctr : std_logic_vector(3 downto 0);\r
- signal next_sync_timeout : std_logic;\r
- signal sync_timeout : std_logic;\r
-\r
- signal rst_lc_sm : std_logic;\r
- signal inc_lc_sm : std_logic;\r
- signal lc_ctr : std_logic_vector(3 downto 0);\r
- signal next_sync_success : std_logic;\r
- signal sync_success : std_logic;\r
- \r
- signal delay_store : std_logic_vector(7 downto 0);\r
- signal store_header : std_logic;\r
- \r
- signal apv_channel : std_logic_vector(6 downto 0);\r
- signal ce_chnl_ctr : std_logic;\r
- signal frame_analog : std_logic;\r
- signal set_frame_analog : std_logic;\r
- signal rst_frame_analog : std_logic;\r
- signal next_apv_last : std_logic;\r
- signal apv_last : std_logic;\r
- signal apv_start : std_logic;\r
- \r
- signal adc_raw_one : std_logic_vector(11 downto 0);\r
- signal adc_raw_two : std_logic_vector(11 downto 0);\r
- \r
- signal bit_high : std_logic;\r
- signal bit_low : std_logic;\r
- signal apv_overflow : std_logic;\r
- signal apv_underflow : std_logic;\r
- \r
- signal next_ce_underflow : std_logic;\r
- signal next_ce_overflow : std_logic;\r
-\r
- signal sum_ovf : std_logic_vector(7 downto 0);\r
- signal sum_udf : std_logic_vector(7 downto 0);\r
-\r
- signal frame_ctr : std_logic_vector(3 downto 0);\r
- signal comb_ce_frame_ctr : std_logic;\r
- \r
- signal debug : std_logic_vector(15 downto 0);\r
- \r
- signal apv_on : std_logic; -- 40MHz clock domain register\r
- \r
+-- normal signals\r
+signal lock_bsm : std_logic_vector(7 downto 0);\r
+signal tickmark_found : std_logic;\r
+signal header_found : std_logic;\r
+signal flatline_found : std_logic;\r
+signal status_unknown : std_logic;\r
+signal status_badadc : std_logic;\r
+signal status_locked : std_logic;\r
+signal status_lost : std_logic;\r
+signal status_nosync : std_logic;\r
+signal status_missing : std_logic;\r
+signal next_status_ignore : std_logic;\r
+signal status_ignore : std_logic;\r
+signal frame_flat : std_logic;\r
+signal next_frame_ovf : std_logic;\r
+signal frame_ovf : std_logic;\r
+signal next_frame_udf : std_logic;\r
+signal frame_udf : std_logic;\r
+signal frame_row : std_logic_vector(7 downto 0);\r
+signal frame_error : std_logic;\r
+signal bit_data : std_logic_vector(11 downto 0);\r
+signal bit_valid : std_logic_vector(11 downto 0);\r
+\r
+signal rst_pc_sm : std_logic;\r
+signal rst_pc_ctr : std_logic;\r
+signal pc_ctr : std_logic_vector(5 downto 0);\r
+signal next_pc_match : std_logic;\r
+signal pc_match : std_logic;\r
+\r
+signal rst_tc_sm : std_logic;\r
+signal inc_tc_sm : std_logic;\r
+signal tc_ctr : std_logic_vector(3 downto 0);\r
+signal next_sync_timeout : std_logic;\r
+signal sync_timeout : std_logic;\r
+\r
+signal rst_lc_sm : std_logic;\r
+signal inc_lc_sm : std_logic;\r
+signal lc_ctr : std_logic_vector(3 downto 0);\r
+signal next_sync_success : std_logic;\r
+signal sync_success : std_logic;\r
+\r
+signal delay_store : std_logic_vector(7 downto 0);\r
+signal store_header : std_logic;\r
+\r
+signal apv_channel : std_logic_vector(6 downto 0);\r
+signal ce_chnl_ctr : std_logic;\r
+signal frame_analog : std_logic;\r
+signal set_frame_analog : std_logic;\r
+signal rst_frame_analog : std_logic;\r
+signal next_apv_last : std_logic;\r
+signal apv_last : std_logic;\r
+signal apv_start : std_logic;\r
+\r
+signal adc_raw_one : std_logic_vector(11 downto 0);\r
+signal adc_raw_two : std_logic_vector(11 downto 0);\r
+\r
+signal bit_high : std_logic;\r
+signal bit_low : std_logic;\r
+signal apv_overflow : std_logic;\r
+signal apv_underflow : std_logic;\r
+\r
+signal next_ce_underflow : std_logic;\r
+signal next_ce_overflow : std_logic;\r
+\r
+signal sum_ovf : std_logic_vector(7 downto 0);\r
+signal sum_udf : std_logic_vector(7 downto 0);\r
+\r
+signal frame_ctr : std_logic_vector(3 downto 0);\r
+signal comb_ce_frame_ctr : std_logic;\r
+\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
+signal apv_on : std_logic; -- 40MHz clock domain register\r
+\r
begin\r
\r
-- Debug signals\r
\r
-- Clock domain crossing\r
THE_APVON_SYNCER: state_sync\r
-port map( STATE_A_IN => apv_on_in,\r
- CLK_B_IN => clk_apv_in,\r
- RESET_B_IN => reset_in,\r
- STATE_B_OUT => apv_on\r
- );\r
+port map(\r
+ STATE_A_IN => apv_on_in,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => apv_on\r
+);\r
\r
-- Input stage, for tickmark and header recognition, and bit decoding.\r
-- Also detects missing APVs by flatline.\r
THE_APV_DIGITAL: apv_digital\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_IN => reset_in,\r
- ADC_RAW_IN => adc_raw_in,\r
- BIT_LOW_IN => bit_low_in,\r
- BIT_HIGH_IN => bit_high_in,\r
- FL_LOW_IN => fl_low_in,\r
- FL_HIGH_IN => fl_high_in,\r
- BIT_DATA_OUT => bit_data,\r
- BIT_VALID_OUT => bit_valid, -- for testing!\r
- BIT_HIGH_OUT => bit_high, -- for analog off recognition, one cycle earlier\r
- BIT_LOW_OUT => bit_low, -- for analog off recognition, one cycle earlier\r
- TICKMARK_OUT => tickmark_found,\r
- HEADER_OUT => header_found,\r
- FLAT_LINE_OUT => flatline_found\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_in,\r
+ ADC_RAW_IN => adc_raw_in,\r
+ BIT_LOW_IN => bit_low_in,\r
+ BIT_HIGH_IN => bit_high_in,\r
+ FL_LOW_IN => fl_low_in,\r
+ FL_HIGH_IN => fl_high_in,\r
+ BIT_DATA_OUT => bit_data,\r
+ BIT_VALID_OUT => bit_valid, -- for testing!\r
+ BIT_HIGH_OUT => bit_high, -- for analog off recognition, one cycle earlier\r
+ BIT_LOW_OUT => bit_low, -- for analog off recognition, one cycle earlier\r
+ TICKMARK_OUT => tickmark_found,\r
+ HEADER_OUT => header_found,\r
+ FLAT_LINE_OUT => flatline_found\r
+);\r
\r
-- Count enables for the underflow / overflow counters\r
next_ce_underflow <= '1' when (bit_high = '0' and bit_low = '1' and frame_analog = '1') else '0';\r
\r
-- Counter for underflow channels\r
THE_UNDERFLOW_CTR_PROC: process( clk_apv_in )\r
-begin \r
+begin\r
if( rising_edge(clk_apv_in) ) then\r
if( (reset_in = '1') or (delay_store(1) = '1') ) then\r
sum_udf <= (others => '0');\r
elsif( next_ce_underflow = '1' ) then\r
- sum_udf <= sum_udf + 1; \r
+ sum_udf <= sum_udf + 1;\r
end if;\r
end if;\r
end process THE_UNDERFLOW_CTR_PROC;\r
\r
-- Counter for Overflow channels\r
THE_OVERFLOW_CTR_PROC: process( clk_apv_in )\r
-begin \r
+begin\r
if( rising_edge(clk_apv_in) ) then\r
if( (reset_in = '1') or (delay_store(1) = '1') ) then\r
sum_ovf <= (others => '0');\r
elsif( next_ce_overflow = '1' ) then\r
- sum_ovf <= sum_ovf + 1; \r
+ sum_ovf <= sum_ovf + 1;\r
end if;\r
end if;\r
end process THE_OVERFLOW_CTR_PROC;\r
\r
-- locking state machine\r
THE_APV_LOCK_SM: apv_lock_sm\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_IN => reset_in,\r
- SYNC_IN => sync_in, -- 40 MHz signal!\r
- ADC_VALID_IN => adc_valid_in,\r
- TIMED_IN => sync_timeout,\r
- MATCH_IN => pc_match,\r
- LOCKED_IN => sync_success,\r
- TICK_IN => tickmark_found,\r
- HEADER_IN => header_found,\r
- FLATLINE_IN => flatline_found,\r
- RST_PC_OUT => rst_pc_sm,\r
- RST_TC_OUT => rst_tc_sm,\r
- INC_TC_OUT => inc_tc_sm,\r
- RST_LC_OUT => rst_lc_sm,\r
- INC_LC_OUT => inc_lc_sm,\r
- UNKNOWN_OUT => status_unknown,\r
- BADADC_OUT => status_badadc,\r
- LOCKED_OUT => status_locked,\r
- LOST_OUT => status_lost,\r
- NOSYNC_OUT => status_nosync,\r
- NOAPV_OUT => status_missing,\r
- BSM_OUT => lock_bsm,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_in,\r
+ SYNC_IN => sync_in, -- 40 MHz signal!\r
+ ADC_VALID_IN => adc_valid_in,\r
+ TIMED_IN => sync_timeout,\r
+ MATCH_IN => pc_match,\r
+ LOCKED_IN => sync_success,\r
+ TICK_IN => tickmark_found,\r
+ HEADER_IN => header_found,\r
+ FLATLINE_IN => flatline_found,\r
+ RST_PC_OUT => rst_pc_sm,\r
+ RST_TC_OUT => rst_tc_sm,\r
+ INC_TC_OUT => inc_tc_sm,\r
+ RST_LC_OUT => rst_lc_sm,\r
+ INC_LC_OUT => inc_lc_sm,\r
+ UNKNOWN_OUT => status_unknown,\r
+ BADADC_OUT => status_badadc,\r
+ LOCKED_OUT => status_locked,\r
+ LOST_OUT => status_lost,\r
+ NOSYNC_OUT => status_nosync,\r
+ NOAPV_OUT => status_missing,\r
+ BSM_OUT => lock_bsm,\r
+ DEBUG_OUT => open\r
+);\r
\r
next_status_ignore <= not apv_on;\r
\r
pc_ctr <= pc_ctr + 1;\r
pc_match <= next_pc_match;\r
rst_pc_ctr <= pc_match;\r
- end if; \r
+ end if;\r
end if;\r
end process THE_PERIOD_COUNTER;\r
\r
end if;\r
end process THE_TIMEOUT_COUNTER;\r
\r
--- watermark for the successful synchronisation \r
+-- watermark for the successful synchronisation\r
next_sync_success <= '1' when ( lc_ctr = x"8" ) else '0';\r
\r
-- lock counter for the lock process\r
delay_store <= (others => '0');\r
else\r
delay_store(7 downto 1) <= delay_store(6 downto 0);\r
- -- we only accept data frames when they arrive at a well defined tickmark place, \r
+ -- we only accept data frames when they arrive at a well defined tickmark place,\r
-- when the APV is really switched on, and it is in locked state.\r
delay_store(0) <= header_found and pc_match and apv_on and status_locked;\r
end if;\r
if( rising_edge(clk_apv_in) ) then\r
if ( reset_in = '1' ) then\r
frame_error <= '0'; -- bit is inverted!\r
- frame_row <= (others => '0'); \r
+ frame_row <= (others => '0');\r
elsif( store_header = '1' ) then\r
frame_error <= not bit_data(0); -- bit is inverted!\r
frame_row <= bit_data(8 downto 1);\r
apv_overflow_out <= apv_overflow;\r
apv_underflow_out <= apv_underflow;\r
apv_analog_out <= ce_chnl_ctr;\r
-apv_start_out <= apv_start;\r
+apv_start_out <= apv_start;\r
apv_last_out <= apv_last;\r
\r
frame_flat_out <= frame_flat;\r
-- Data is piped out directly.\r
\r
entity apv_pc_nc_alu is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic;\r
- START_IN : in std_logic; -- start signal, used for initialisation of counters\r
- MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
- CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
- LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
- EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
- BUF_GOOD_IN : in std_logic; -- process buffer\r
- BUF_BAD_IN : in std_logic; -- write only error header\r
- BUF_IGNORE_IN : in std_logic; -- do not write anything\r
- ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
- DO_HEADER_IN : in std_logic;\r
- DO_ERROR_IN : in std_logic;\r
- EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
- RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
- RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
- PED_DATA_IN : in std_logic_vector(17 downto 0); \r
- THR_DATA_IN : in std_logic_vector(17 downto 0);\r
- FRAME_IN : in std_logic;\r
- FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
- WE_OUT : out std_logic;\r
- COUNT_OUT : out std_logic_vector(9 downto 0);\r
- ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic; -- start signal, used for initialisation of counters\r
+ MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
+ CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
+ LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ BUF_GOOD_IN : in std_logic; -- process buffer\r
+ BUF_BAD_IN : in std_logic; -- write only error header\r
+ BUF_IGNORE_IN : in std_logic; -- do not write anything\r
+ ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
+ DO_HEADER_IN : in std_logic;\r
+ DO_ERROR_IN : in std_logic;\r
+ SUPPRESS_IN : in std_logic; -- suppress bit\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0); -- RICH data configuration bits\r
+ RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
+ PED_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_DATA_IN : in std_logic_vector(17 downto 0);\r
+ FRAME_IN : in std_logic;\r
+ FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
+ WE_OUT : out std_logic;\r
+ COUNT_OUT : out std_logic_vector(9 downto 0);\r
+ ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
----------------------------------------------------------------------\r
\r
architecture behavioral of apv_pc_nc_alu is\r
\r
- -- normal signals\r
- signal raw_data_q : std_logic_vector(12 downto 0); -- input register\r
- signal ped_data_q : std_logic_vector(12 downto 0); -- input register\r
- signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
- signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
- signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
- signal loc_baseline_q : std_logic_vector(13 downto 0);\r
- signal nc_corr_data_q : std_logic_vector(13 downto 0);\r
- signal nc_corr_data_qq : std_logic_vector(13 downto 0);\r
- signal nc_corr_data_qqq : std_logic_vector(21 downto 0);\r
- signal thr_data_q : std_logic_vector(13 downto 0);\r
- signal udf_int : std_logic_vector(6 downto 0);\r
- signal ovf_int : std_logic_vector(6 downto 0); \r
- signal frame_int : std_logic_vector(6 downto 0);\r
- signal off_int : std_logic_vector(6 downto 0);\r
- signal next_data_we : std_logic;\r
- signal data_we : std_logic;\r
-\r
- signal thr_pass : std_logic;\r
-\r
- -- data steering signals\r
- signal next_ped_off : std_logic;\r
- signal ped_off : std_logic; -- switch off pedestals\r
- signal next_lcb_off : std_logic;\r
- signal lcb_off : std_logic; -- switch off local baseline correction\r
- signal next_clip_max : std_logic;\r
- signal clip_max : std_logic; -- clip OVF values to maximum \r
- signal next_clip_min : std_logic;\r
- signal clip_min : std_logic; -- clip UDF values to minimum\r
- signal next_bad_corr : std_logic_vector(6 downto 2);\r
- signal bad_corr : std_logic_vector(6 downto 2);\r
- signal toggle : std_logic_vector(6 downto 0);\r
- \r
- -- Channel counter\r
- signal channel : std_logic_vector(6 downto 0);\r
-\r
- signal count : std_logic_vector(9 downto 0);\r
-\r
- signal anydata : std_logic;\r
-\r
- -- Debug signals\r
- signal debug : std_logic_vector(15 downto 0);\r
- \r
+-- normal signals\r
+signal raw_data_q : std_logic_vector(12 downto 0); -- input register\r
+signal ped_data_q : std_logic_vector(12 downto 0); -- input register\r
+signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
+signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
+signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
+signal loc_baseline_q : std_logic_vector(13 downto 0);\r
+signal nc_corr_data_q : std_logic_vector(13 downto 0);\r
+signal nc_corr_data_qq : std_logic_vector(13 downto 0);\r
+signal nc_corr_data_qqq : std_logic_vector(21 downto 0);\r
+signal thr_data_q : std_logic_vector(13 downto 0);\r
+signal udf_int : std_logic_vector(6 downto 0);\r
+signal ovf_int : std_logic_vector(6 downto 0);\r
+signal frame_int : std_logic_vector(6 downto 0);\r
+signal off_int : std_logic_vector(6 downto 0);\r
+signal next_data_we : std_logic;\r
+signal data_we : std_logic;\r
+signal adjust_data : std_logic_vector(13 downto 0);\r
+\r
+signal thr_pass : std_logic;\r
+\r
+-- data steering signals\r
+signal next_ped_off : std_logic;\r
+signal ped_off : std_logic; -- switch off pedestals\r
+signal next_lcb_off : std_logic;\r
+signal lcb_off : std_logic; -- switch off local baseline correction\r
+signal next_clip_max : std_logic;\r
+signal clip_max : std_logic; -- clip OVF values to maximum\r
+signal next_clip_min : std_logic;\r
+signal clip_min : std_logic; -- clip UDF values to minimum\r
+signal next_bad_corr : std_logic_vector(6 downto 2);\r
+signal bad_corr : std_logic_vector(6 downto 2);\r
+signal toggle : std_logic_vector(6 downto 0);\r
+\r
+-- Channel counter\r
+signal channel : std_logic_vector(6 downto 0);\r
+\r
+signal count : std_logic_vector(9 downto 0);\r
+\r
+signal anydata : std_logic;\r
+\r
+-- Debug signals\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
begin\r
\r
---------------------------------------------------------------------------------\r
-- 000 RAW128 128 raw data (+ 4096 + 8192)\r
-- 001 PED128 128 pedestal data (+ 4096 - pedestal)\r
-- 010 PED128THR <=128 pedestal data above threshold\r
--- 011 --- --- ---\r
+-- 011 RAW64 64 raw data \r
-- 100 NC64PED64 128 do NC on physic channels, corr. channels pedestal corrected\r
-- 101 NC64 64 only NC physic channels\r
-- 110 NC64GOOD <=64 only good NC channels\r
-- 111 NC64THR <=64 only good NC channels above threshold\r
---------------------------------------------------------------------------------\r
\r
--- Switch off pedestals (RAW128 mode)\r
-next_ped_off <= '1' when ( evt_type_in = "000" ) else '0';\r
+-- Switch off pedestals (RAW128 and RAW64 mode)\r
+next_ped_off <= '1' when ( (evt_type_in = b"000") or (evt_type_in = b"011") ) else '0';\r
\r
--- Switch off local baseline (RAW128, PED128, PED128THR modes)\r
-next_lcb_off <= '1' when ( (evt_type_in = "000") or (evt_type_in = "001") or (evt_type_in = "010") ) else '0';\r
+-- Switch off local baseline (RAW128, PED128, PED128THR, RAW64 modes)\r
+next_lcb_off <= '1' when ( (evt_type_in = b"000") or (evt_type_in = b"001") or (evt_type_in = b"010") or (evt_type_in = b"011") ) \r
+ else '0';\r
\r
--- Clipping function for neighbour corrected values (all modes except RAW128)\r
-next_clip_min <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or \r
- (evt_type_in(2) = '1') ) and (udf_int(2) = '1') ) \r
+-- Clipping function for neighbour corrected values (all modes except RAW128 and RAW64)\r
+next_clip_min <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or\r
+ (evt_type_in(2) = '1') ) and (udf_int(2) = '1') )\r
else '0';\r
-next_clip_max <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or \r
- (evt_type_in(2) = '1') ) and (ovf_int(2) = '1') ) \r
+next_clip_max <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or\r
+ (evt_type_in(2) = '1') ) and (ovf_int(2) = '1') )\r
else '0';\r
\r
-- Neighbour correction: handle broken or switched off correction channels.\r
-- A broken (UDF/OVF) or switched off (OFF) correction channel kills its two physical neighbour channels.\r
next_bad_corr(2) <= '1' when ( (udf_int(0) = '1') or (udf_int(2) = '1') or\r
- (ovf_int(0) = '1') or (ovf_int(2) = '1') or\r
- (off_int(0) = '1') or (off_int(2) = '1') ) \r
- else '0';\r
+ (ovf_int(0) = '1') or (ovf_int(2) = '1') or\r
+ (off_int(0) = '1') or (off_int(2) = '1') )\r
+ else '0';\r
\r
next_bad_corr(3) <= '1' when ( (bad_corr(2) = '1') and (evt_type_in(2) = '1') ) else '0';\r
\r
-next_bad_corr(4) <= '1' when ( ((bad_corr(3) = '1') and (toggle(3) = '1') and (frame_int(3) = '1')) or \r
- (off_int(3) = '1') ) \r
- else '0';\r
+next_bad_corr(4) <= '1' when ( ((bad_corr(3) = '1') and (toggle(3) = '1') and (frame_int(3) = '1')) or\r
+ (off_int(3) = '1') )\r
+ else '0';\r
next_bad_corr(5) <= bad_corr(4);\r
next_bad_corr(6) <= bad_corr(5);\r
\r
+-- baseline shifting for raw modes (4096)\r
+adjust_data <= b"01_0000_0000_0000" when evt_type_in(2) = '0' else b"00_0000_0000_0000";\r
+\r
-- We carry the OVF/UDF/OFF information all through the chain!\r
THE_SYNC_PROC: process( clk_in )\r
begin\r
THE_RAW_INPUT_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
- raw_data_q <= '1' & raw_data_in(11 downto 0); \r
+ raw_data_q <= '1' & raw_data_in(11 downto 0);\r
end if;\r
end process THE_RAW_INPUT_PROC;\r
\r
if( (reset_in = '1') or (ped_off = '1') ) then\r
ped_data_q <= (others => '0');\r
else\r
- ped_data_q <= '0' & ped_data_in(11 downto 0); \r
+ ped_data_q <= '0' & ped_data_in(11 downto 0);\r
end if;\r
end if;\r
end process THE_PED_INPUT_PROC;\r
begin\r
if( rising_edge(clk_in) ) then\r
if( (reset_in = '1') or (lcb_off = '1') ) then\r
- loc_baseline_q <= (others => '0'); \r
+ loc_baseline_q <= (others => '0');\r
else\r
loc_baseline_q <= ('0' & ped_corr_data_q) + ('0' & ped_corr_data_qqq);\r
end if;\r
elsif( clip_max = '1' ) then\r
nc_corr_data_q <= (others => '1'); -- channel is overflow\r
else\r
- nc_corr_data_q <= ('1' & ped_corr_data_qqq) - ('0' & loc_baseline_q(13 downto 1)); \r
+ nc_corr_data_q <= ('1' & ped_corr_data_qqq) - ('0' & loc_baseline_q(13 downto 1));\r
end if;\r
end if;\r
end process THE_NC_CORR_PROC;\r
\r
-- One caveat: in PED128 our artificial baseline is 4096, in NC64THR it is 8192.\r
-thr_data_q(13) <= '1'; --'1' when (evt_type_in = "111") else '0';\r
+thr_data_q(13) <= '1';\r
thr_data_q(12) <= '0' when (evt_type_in = "111") else '1';\r
\r
-- Threshold comparison\r
THE_THR_COMP: comp14bit\r
-port map( DATAA => nc_corr_data_q,\r
- DATAB => thr_data_q,\r
- CLOCK => clk_in, \r
- CLOCKEN => '1', \r
- ACLR => reset_in, -- BUG 10092009 \r
- AGEB => thr_pass\r
- );\r
+port map(\r
+ DATAA => nc_corr_data_q,\r
+ DATAB => thr_data_q,\r
+ CLOCK => clk_in,\r
+ CLOCKEN => '1',\r
+ ACLR => reset_in,\r
+ AGEB => thr_pass\r
+);\r
+\r
+-- in raw modes, we must shift back to "normal" nominal baseline\r
+THE_ADJUSTMENT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ nc_corr_data_qq <= nc_corr_data_q - adjust_data; \r
+ end if;\r
+end process THE_ADJUSTMENT_PROC;\r
+\r
\r
-- Delay NCD by one cycle, store THR data\r
THE_NC_DELAY_PROC: process( clk_in )\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
nc_corr_data_qqq <= (others => '0');\r
- nc_corr_data_qq <= (others => '0');\r
+-- nc_corr_data_qq <= (others => '0');\r
thr_data_q(11 downto 0) <= (others => '0');\r
else\r
if ( (do_header_in = '0') and (do_error_in = '0') ) then\r
nc_corr_data_qqq(21) <= '0'; -- DATA\r
nc_corr_data_qqq(20 downto 14) <= channel;\r
nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq;\r
- elsif( (do_header_in = '1') ) then \r
+ elsif( (do_header_in = '1') ) then\r
nc_corr_data_qqq(21) <= '1'; -- HEADER\r
nc_corr_data_qqq(20) <= buf_bad_in;\r
nc_corr_data_qqq(19 downto 16) <= error_in;\r
nc_corr_data_qqq(15 downto 12) <= max_frames_in;\r
nc_corr_data_qqq(11 downto 8) <= curr_frame_in;\r
nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18);\r
- elsif( (do_error_in = '1') ) then \r
+ elsif( (do_error_in = '1') ) then\r
nc_corr_data_qqq(21) <= '1'; -- HEADER\r
nc_corr_data_qqq(20) <= raw_data_in(26); -- error\r
nc_corr_data_qqq(19 downto 16) <= eds_frm_ctr_in; -- EDS start frame\r
nc_corr_data_qqq(11 downto 8) <= raw_data_in(17 downto 14); -- frame counter\r
nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); -- row\r
end if;\r
- nc_corr_data_qq <= nc_corr_data_q;\r
+-- nc_corr_data_qq <= nc_corr_data_q;\r
thr_data_q(11 downto 0) <= thr_data_in(11 downto 0);\r
end if;\r
end if;\r
end process THE_NC_DELAY_PROC;\r
\r
-- Judgement day: will data survive?\r
-next_data_we <= '1' when ( ((buf_good_in = '1') and (evt_type_in = "000") and (frame_int(5) = '1')) or \r
- ((buf_good_in = '1') and (evt_type_in = "001") and (frame_int(5) = '1')) or\r
- ((buf_good_in = '1') and (evt_type_in = "010") and (frame_int(5) = '1') and (thr_pass = '1') and (bad_corr(5) = '0')) or\r
- ((buf_good_in = '1') and (evt_type_in = "100") and (frame_int(5) = '1')) or\r
- ((buf_good_in = '1') and (evt_type_in = "101") and (frame_int(5) = '1') and (toggle(5) = '1')) or\r
- ((buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or\r
- ((buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or\r
- (((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or\r
--- ((buf_bad_in = '1') and (do_error_in = '1'))\r
- ((do_error_in = '1'))\r
- ) \r
- else '0';\r
+next_data_we <= '1' when ( \r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "000") and (frame_int(5) = '1')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "001") and (frame_int(5) = '1')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "010") and (frame_int(5) = '1') and (thr_pass = '1') and (bad_corr(5) = '0')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "011") and (frame_int(5) = '1') and (toggle(5) = '1')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "100") and (frame_int(5) = '1')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "101") and (frame_int(5) = '1') and (toggle(5) = '1')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or\r
+ ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or\r
+ (((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or\r
+-- ((buf_bad_in = '1') and (do_error_in = '1'))\r
+ ((do_error_in = '1'))\r
+) else '0';\r
\r
-- Channel counter for outgoing data\r
THE_CHANNEL_CTR_PROC: process( clk_in )\r
end if;\r
end process THE_CHANNEL_CTR_PROC;\r
\r
--- Channel counter for outgoing data\r
+-- Data word counter, including all words written (i.e. also headers and debug words)\r
+--\r
+-- NB: we have 10 bits for COUNT. So we can use up to 1023 data words per event, including\r
+-- all debug words. \r
THE_DATA_CTR_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
anydata <= '0';\r
elsif( (data_we = '1') and (anydata = '0') ) then\r
anydata <= '1';\r
+ count <= count + 1; -- changed\r
elsif( (data_we = '1') and (anydata = '1') ) then\r
count <= count + 1;\r
end if;\r
end process THE_DATA_CTR_PROC;\r
\r
-- output signals (most of them are only needed for simulation!)\r
-we_out <= data_we; \r
+we_out <= data_we;\r
count_out <= count;\r
anydata_out <= anydata;\r
\r
fifo_data_out(24) <= bad_corr(6);\r
fifo_data_out(23) <= ovf_int(6);\r
fifo_data_out(22) <= udf_int(6);\r
-fifo_data_out(21 downto 0) <= nc_corr_data_qqq; \r
+fifo_data_out(21 downto 0) <= nc_corr_data_qqq;\r
\r
-- Debug signals\r
--debug(31 downto 16) <= (others => '0');\r
\r
dbg_out <= debug;\r
\r
-end behavioral;\r
-\r
---THE_NC_DELAY_PROC: process( clk_in )\r
---begin\r
--- if( rising_edge(clk_in) ) then\r
--- if( reset_in = '1' ) then\r
--- nc_corr_data_qqq <= (others => '0');\r
--- nc_corr_data_qq <= (others => '0');\r
--- thr_data_q(11 downto 0) <= (others => '0');\r
--- else\r
--- if( (do_header_in = '0') and (do_error_in = '0') ) then\r
--- nc_corr_data_qqq(21) <= '0'; -- DATA\r
--- nc_corr_data_qqq(20 downto 14) <= channel;\r
--- nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq;\r
--- else\r
--- nc_corr_data_qqq(21) <= '1'; -- HEADER\r
--- nc_corr_data_qqq(20) <= buf_bad_in;\r
--- nc_corr_data_qqq(19 downto 16) <= error_in;\r
--- nc_corr_data_qqq(15 downto 12) <= max_frames_in;\r
--- nc_corr_data_qqq(11 downto 8) <= curr_frame_in;\r
--- nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18);\r
--- end if;\r
--- nc_corr_data_qq <= nc_corr_data_q;\r
--- thr_data_q(11 downto 0) <= thr_data_in(11 downto 0);\r
--- end if;\r
--- end if;\r
---end process THE_NC_DELAY_PROC;\r
+end behavioral;
\ No newline at end of file
library work;\r
use work.adcmv3_components.all;\r
\r
--- This entity is used to decouple the ADC/APV part (with 40MHz) from the data \r
+-- This entity is used to decouple the ADC/APV part (with 40MHz) from the data\r
-- handling part (which runs with 100MHz).\r
-- Signals:\r
-- - all signals starting with ADC_* are synchronous to CLK_APV_IN\r
-- - take care of the one clock delay between BUF_ADDR_IN and BUF_DATA_OUT.\r
\r
entity apv_raw_buffer is\r
- port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
- RESET_IN : in std_logic;\r
- -- buffer level control signals\r
- FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
- MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
- -- CLK_APV_IN sync'ed signals from APV_LOCKER\r
- ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
- ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
- ADC_LAST_IN : in std_logic; -- last channel signal\r
- ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
- ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
- ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
- ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
- -- BUF_CLK_IN sync'ed signals from back side logic \r
- BUF_CLK_IN : in std_logic; -- read clock\r
- BUF_RESET_IN : in std_logic; -- 100MHz reset\r
- BUF_START_OUT : out std_logic; -- one block starts writing (aka ADC_START)\r
- BUF_READY_OUT : out std_logic; -- one block has been written (aka ADC_LAST)\r
- BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
- BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
- BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
- BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
- BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
- BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
- BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
- BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
- BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler+\r
- BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
+ RESET_IN : in std_logic;\r
+ -- buffer level control signals\r
+ FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
+ -- CLK_APV_IN sync'ed signals from APV_LOCKER\r
+ ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
+ ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
+ ADC_LAST_IN : in std_logic; -- last channel signal\r
+ ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
+ ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
+ ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
+ ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
+ -- BUF_CLK_IN sync'ed signals from back side logic\r
+ BUF_CLK_IN : in std_logic; -- read clock\r
+ BUF_RESET_IN : in std_logic; -- 100MHz reset\r
+ BUF_START_OUT : out std_logic; -- one block starts writing (aka ADC_START)\r
+ BUF_READY_OUT : out std_logic; -- one block has been written (aka ADC_LAST)\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
+ BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
+ BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
+ BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
+ BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
+ BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
+ BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
+ BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
+ BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler+\r
+ BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of apv_raw_buffer is\r
\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of behavioral : architecture is "APV_RAW_BUF_group";\r
-\r
- -- normal signals\r
- signal adc_status_q : std_logic_vector(7 downto 0);\r
- signal adc_status_qq : std_logic_vector(7 downto 0);\r
-\r
- signal adc_start_x : std_logic;\r
- signal adc_start : std_logic;\r
- signal adc_last_x : std_logic;\r
- signal adc_last : std_logic;\r
-\r
- signal ce_wr_pointer : std_logic;\r
- signal wr_pointer : std_logic_vector(3 downto 0);\r
- signal ce_rd_pointer : std_logic;\r
- signal rd_pointer : std_logic_vector(3 downto 0);\r
- \r
- signal buf_good_x : std_logic;\r
- signal buf_good : std_logic;\r
- signal buf_broken_x : std_logic;\r
- signal buf_broken : std_logic;\r
- signal buf_ignore_x : std_logic;\r
- signal buf_ignore : std_logic;\r
- \r
- signal buf_level : std_logic_vector(4 downto 0);\r
- signal buf_level_up_x : std_logic;\r
- signal buf_level_down_x : std_logic;\r
- \r
- signal wr_data_addr : std_logic_vector(10 downto 0);\r
- signal wr_data_d : std_logic_vector(17 downto 0);\r
- signal wr_data_ena : std_logic;\r
- signal rd_data_addr : std_logic_vector(10 downto 0);\r
- signal rd_data_d : std_logic_vector(17 downto 0);\r
- signal rd_data_ena : std_logic;\r
-\r
- signal buf_frame : std_logic_vector(11 downto 0);\r
- \r
- signal adc_tickmark : std_logic;\r
- signal buf_tickmark : std_logic;\r
-\r
- -- Alias names for status bits\r
- signal apv_on_x : std_logic; -- 40MHz clock domain signal\r
- signal apv_on : std_logic;\r
- signal apv_adcok_x : std_logic; -- 40MHz clock domain signal\r
- signal apv_adcok : std_logic;\r
- signal apv_locked_x : std_logic; -- 40MHz clock domain signal\r
- signal apv_locked : std_logic;\r
-\r
- -- from old APV_BUFHANDLER block\r
- signal apv_free_ctr : std_logic_vector(4 downto 0);\r
- signal apv_free_up : std_logic;\r
- signal apv_free_down : std_logic;\r
- signal buf_free_ctr : std_logic_vector(4 downto 0);\r
- signal buf_free_up : std_logic;\r
- signal buf_free_down : std_logic;\r
- \r
- signal sum_apv_buf : std_logic_vector(5 downto 0);\r
- signal sum_apv : std_logic_vector(5 downto 0);\r
- signal sum_buf : std_logic_vector(5 downto 0);\r
- signal trg_limit : std_logic_vector(5 downto 0);\r
- \r
- signal debug : std_logic_vector(15 downto 0);\r
- \r
- signal apv_or_buf_full_x : std_logic;\r
- signal apv_or_buf_full : std_logic;\r
- \r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behavioral : architecture is "APV_RAW_BUF_group";\r
+\r
+-- normal signals\r
+signal adc_status_q : std_logic_vector(7 downto 0);\r
+signal adc_status_qq : std_logic_vector(7 downto 0);\r
+\r
+signal adc_start_x : std_logic;\r
+signal adc_start : std_logic;\r
+signal adc_last_x : std_logic;\r
+signal adc_last : std_logic;\r
+\r
+signal ce_wr_pointer : std_logic;\r
+signal wr_pointer : std_logic_vector(3 downto 0);\r
+signal ce_rd_pointer : std_logic;\r
+signal rd_pointer : std_logic_vector(3 downto 0);\r
+\r
+signal buf_good_x : std_logic;\r
+signal buf_good : std_logic;\r
+signal buf_broken_x : std_logic;\r
+signal buf_broken : std_logic;\r
+signal buf_ignore_x : std_logic;\r
+signal buf_ignore : std_logic;\r
+\r
+signal buf_level : std_logic_vector(4 downto 0);\r
+signal buf_level_up_x : std_logic;\r
+signal buf_level_down_x : std_logic;\r
+\r
+signal wr_data_addr : std_logic_vector(10 downto 0);\r
+signal wr_data_d : std_logic_vector(17 downto 0);\r
+signal wr_data_ena : std_logic;\r
+signal rd_data_addr : std_logic_vector(10 downto 0);\r
+signal rd_data_d : std_logic_vector(17 downto 0);\r
+signal rd_data_ena : std_logic;\r
+\r
+signal buf_frame : std_logic_vector(11 downto 0);\r
+\r
+signal adc_tickmark : std_logic;\r
+signal buf_tickmark : std_logic;\r
+\r
+-- Alias names for status bits\r
+signal apv_on_x : std_logic; -- 40MHz clock domain signal\r
+signal apv_on : std_logic;\r
+signal apv_adcok_x : std_logic; -- 40MHz clock domain signal\r
+signal apv_adcok : std_logic;\r
+signal apv_locked_x : std_logic; -- 40MHz clock domain signal\r
+signal apv_locked : std_logic;\r
+\r
+-- from old APV_BUFHANDLER block\r
+signal apv_free_ctr : std_logic_vector(4 downto 0);\r
+signal apv_free_up : std_logic;\r
+signal apv_free_down : std_logic;\r
+signal buf_free_ctr : std_logic_vector(4 downto 0);\r
+signal buf_free_up : std_logic;\r
+signal buf_free_down : std_logic;\r
+\r
+signal sum_apv_buf : std_logic_vector(5 downto 0);\r
+signal sum_apv : std_logic_vector(5 downto 0);\r
+signal sum_buf : std_logic_vector(5 downto 0);\r
+signal trg_limit : std_logic_vector(5 downto 0);\r
+\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
+signal apv_or_buf_full_x : std_logic;\r
+signal apv_or_buf_full : std_logic;\r
+\r
begin\r
\r
-- Debugging signals\r
apv_on_x <= not adc_status_in(1); -- '0' = "off" means "ignore", '1' = "on" means "look at me"\r
\r
THE_APV_ON_SYNC: state_sync\r
-port map( STATE_A_IN => apv_on_x,\r
- CLK_B_IN => buf_clk_in,\r
- RESET_B_IN => buf_reset_in,\r
- STATE_B_OUT => apv_on\r
- );\r
+port map(\r
+ STATE_A_IN => apv_on_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ STATE_B_OUT => apv_on\r
+);\r
\r
THE_APV_LOCKED_SYNC: state_sync\r
-port map( STATE_A_IN => apv_locked_x,\r
- CLK_B_IN => buf_clk_in,\r
- RESET_B_IN => buf_reset_in,\r
- STATE_B_OUT => apv_locked\r
- );\r
+port map(\r
+ STATE_A_IN => apv_locked_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ STATE_B_OUT => apv_locked\r
+);\r
\r
THE_APV_ADCOK_SYNC: state_sync\r
-port map( STATE_A_IN => apv_adcok_x,\r
- CLK_B_IN => buf_clk_in,\r
- RESET_B_IN => buf_reset_in,\r
- STATE_B_OUT => apv_adcok\r
- );\r
+port map(\r
+ STATE_A_IN => apv_adcok_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ STATE_B_OUT => apv_adcok\r
+);\r
\r
-- We deliver three status signals to the data handler:\r
-- BUF_GOOD_OUT : APV is switched on and alive, so data packets can be expected in case of triggers.\r
\r
-- CLOCK DOMAINS!\r
buf_good_x <= '1' when ((apv_on = '1') and (apv_adcok = '1') and (apv_locked = '1')) else '0';\r
-buf_broken_x <= '1' when ((apv_on = '1') and (apv_adcok = '0' or apv_locked = '0')) else '0'; \r
+buf_broken_x <= '1' when ((apv_on = '1') and (apv_adcok = '0' or apv_locked = '0')) else '0';\r
buf_ignore_x <= '1' when ( apv_on = '0' ) else '0';\r
\r
-THE_BUF_SYNCER_PROC: process( buf_clk_in ) \r
+THE_BUF_SYNCER_PROC: process( buf_clk_in )\r
begin\r
if( rising_edge(buf_clk_in) ) then\r
buf_good <= buf_good_x;\r
adc_start_x <= (adc_start_in and buf_good_x);\r
\r
THE_ADC_START_SYNCER: pulse_sync\r
-port map( CLK_A_IN => clk_apv_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => adc_start_x,\r
- CLK_B_IN => buf_clk_in,\r
- RESET_B_IN => buf_reset_in,\r
- PULSE_B_OUT => adc_start\r
- );\r
+port map(\r
+ CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => adc_start_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ PULSE_B_OUT => adc_start\r
+);\r
\r
adc_last_x <= (adc_last_in and buf_good_x);\r
\r
THE_ADC_LAST_SYNCER: pulse_sync\r
-port map( CLK_A_IN => clk_apv_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => adc_last_x,\r
- CLK_B_IN => buf_clk_in,\r
- RESET_B_IN => buf_reset_in,\r
- PULSE_B_OUT => adc_last\r
- );\r
+port map(\r
+ CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => adc_last_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ PULSE_B_OUT => adc_last\r
+);\r
\r
-- The tickmark signal is also transfered from 40M to 100M clock domain\r
adc_tickmark <= adc_status_in(0); -- alias\r
THE_TICKMARK_SYNCER: pulse_sync\r
-port map( CLK_A_IN => clk_apv_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => adc_tickmark,\r
- CLK_B_IN => buf_clk_in,\r
- RESET_B_IN => buf_reset_in,\r
- PULSE_B_OUT => buf_tickmark\r
- );\r
+port map(\r
+ CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => adc_tickmark,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ PULSE_B_OUT => buf_tickmark\r
+);\r
\r
\r
-- Control signals for the write pointer counter\r
end process THE_RD_POINTER;\r
\r
-- We need a level counter for the EDS handler, anyhow\r
-buf_level_up_x <= adc_last; \r
+buf_level_up_x <= adc_last;\r
buf_level_down_x <= (buf_done_in and buf_good);\r
\r
THE_BUF_LEVEL_COUNTER_PROC: process( buf_clk_in )\r
\r
-- We have two EBRs to implement a 2kx18 ring buffer\r
THE_INPUT_BRAM: input_bram\r
-port map( WRADDRESS => wr_data_addr,\r
- RDADDRESS => rd_data_addr,\r
- DATA => wr_data_d, \r
- WE => wr_data_ena,\r
- RDCLOCK => buf_clk_in,\r
- RDCLOCKEN => rd_data_ena,\r
- RESET => reset_in,\r
- WRCLOCK => clk_apv_in,\r
- WRCLOCKEN => '1',\r
- Q => rd_data_d\r
- );\r
+port map(\r
+ WRADDRESS => wr_data_addr,\r
+ RDADDRESS => rd_data_addr,\r
+ DATA => wr_data_d,\r
+ WE => wr_data_ena,\r
+ RDCLOCK => buf_clk_in,\r
+ RDCLOCKEN => rd_data_ena,\r
+ RESET => reset_in,\r
+ WRCLOCK => clk_apv_in,\r
+ WRCLOCKEN => '1',\r
+ Q => rd_data_d\r
+);\r
\r
-- We use a LUT based DPRAM for the 16x12b status memory\r
THE_FRAME_STATUS_MEM: frame_status_mem\r
-port map( WRADDRESS => wr_pointer, \r
- DATA => adc_frame_in,\r
- WRCLOCK => clk_apv_in,\r
- WE => ce_wr_pointer, -- we store the frame status with the last ADC word\r
- WRCLOCKEN => '1',\r
- RDADDRESS => rd_pointer,\r
- RDCLOCK => buf_clk_in,\r
- RDCLOCKEN => '1',\r
- RESET => reset_in,\r
- Q => buf_frame\r
- );\r
+port map(\r
+ WRADDRESS => wr_pointer,\r
+ DATA => adc_frame_in,\r
+ WRCLOCK => clk_apv_in,\r
+ WE => ce_wr_pointer, -- we store the frame status with the last ADC word\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => rd_pointer,\r
+ RDCLOCK => buf_clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => buf_frame\r
+);\r
\r
------------------------------------------------------------------------------------------\r
-- Buffer fill levels, busy generation\r
------------------------------------------------------------------------------------------\r
\r
-- We need to keep track of the APV analog fifo fill level.\r
--- Two signals are used: \r
+-- Two signals are used:\r
-- - an early "FRAME_REQD" to decrement to number of free entries,\r
--- - a late "FRAME_RCVD" to notify that a requested frame has been transfered \r
+-- - a late "FRAME_RCVD" to notify that a requested frame has been transfered\r
-- from APV to the raw buffer.\r
\r
apv_free_down <= frm_reqd_in;\r
-apv_free_up <= adc_last; \r
+apv_free_up <= adc_last;\r
\r
THE_APV_FREE_COUNTER_PROC: process( buf_clk_in )\r
begin\r
if ( buf_reset_in = '1' ) then\r
apv_free_ctr <= "10000";\r
elsif( apv_free_down = '1' and apv_free_up = '0' ) then\r
- apv_free_ctr <= apv_free_ctr - 1; \r
+ apv_free_ctr <= apv_free_ctr - 1;\r
elsif( apv_free_down = '0' and apv_free_up = '1' ) then\r
apv_free_ctr <= apv_free_ctr + 1;\r
end if;\r
end if;\r
end process THE_APV_FREE_COUNTER_PROC;\r
\r
--- The raw data buffer is also to be watched carefully. \r
+-- The raw data buffer is also to be watched carefully.\r
-- An early signal reserved on raw buffer page, while a late one releases one\r
-- page to the buffer pool again.\r
\r
if ( buf_reset_in = '1' ) then\r
buf_free_ctr <= "10000";\r
elsif( buf_free_down = '1' and buf_free_up = '0' ) then\r
- buf_free_ctr <= buf_free_ctr - 1; \r
+ buf_free_ctr <= buf_free_ctr - 1;\r
elsif( buf_free_down = '0' and buf_free_up = '1' ) then\r
buf_free_ctr <= buf_free_ctr + 1;\r
end if;\r
port map( DATAA => sum_apv,\r
DATAB => sum_buf,\r
CLOCK => buf_clk_in,\r
- RESET => buf_reset_in, \r
- CLOCKEN => '1', \r
+ RESET => buf_reset_in,\r
+ CLOCKEN => '1',\r
RESULT => sum_apv_buf\r
);\r
\r
use work.adcmv3_components.all;\r
\r
entity apv_sync_handler is\r
- port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
- RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
- CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
- APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
- APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished (100MHz)\r
- APV_TRG_OUT : out std_logic; -- TRG line signal (40MHz APV)\r
- APV_SYNC_OUT : out std_logic; -- signal for statemachines (40MHz APV)\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished (100MHz)\r
+ APV_TRG_OUT : out std_logic; -- TRG line signal (40MHz APV)\r
+ APV_SYNC_OUT : out std_logic; -- signal for statemachines (40MHz APV)\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of apv_sync_handler is\r
\r
- -- state machine signals\r
- type STATES is (SLEEP,START,T2,T1,T0,DLY0,DLY1,DLY2,DLY3,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+-- state machine signals\r
+type STATES is (SLEEP,START,T2,T1,T0,DLY0,DLY1,DLY2,DLY3,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- -- normal signals\r
- signal apv_trgdone : std_logic;\r
- signal apv_trgstart : std_logic;\r
- signal comb_apv_trgstart : std_logic;\r
- -- state machine generated signals\r
- signal next_apv_done : std_logic;\r
- signal apv_done : std_logic;\r
- signal next_apv_trg : std_logic;\r
- signal apv_trg : std_logic;\r
- signal next_apv_sync : std_logic;\r
- signal apv_sync : std_logic;\r
+-- normal signals\r
+signal apv_trgdone : std_logic;\r
+signal apv_trgstart : std_logic;\r
+signal comb_apv_trgstart : std_logic;\r
+-- state machine generated signals\r
+signal next_apv_done : std_logic;\r
+signal apv_done : std_logic;\r
+signal next_apv_trg : std_logic;\r
+signal apv_trg : std_logic;\r
+signal next_apv_sync : std_logic;\r
+signal apv_sync : std_logic;\r
\r
\r
begin\r
\r
-- APV_TRGSTART_IN crosses a clock domain (100M -> 40M).\r
-comb_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; \r
+comb_apv_trgstart <= apv_trgstart_in and apv_trgsel_in;\r
\r
THE_APVTRGSTART_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => comb_apv_trgstart,\r
- CLK_B_IN => clk_apv_in,\r
- RESET_B_IN => reset_apv_in,\r
- PULSE_B_OUT => apv_trgstart\r
- );\r
+port map(\r
+ CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => comb_apv_trgstart,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => reset_apv_in,\r
+ PULSE_B_OUT => apv_trgstart\r
+);\r
\r
-- A statemachine handles all actions for creating the trigger sequence\r
-- state registers\r
-STATE_MEM: process( clk_apv_in ) \r
+STATE_MEM: process( clk_apv_in )\r
begin\r
if( rising_edge(clk_apv_in) ) then\r
if( reset_apv_in = '1' ) then\r
next_apv_trg <= '0';\r
next_apv_sync <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( apv_trgstart = '1' ) then\r
+ when SLEEP => if( apv_trgstart = '1' ) then\r
NEXT_STATE <= START;\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when START => NEXT_STATE <= T2;\r
+ when START => NEXT_STATE <= T2;\r
next_apv_trg <= '1';\r
- when T2 => NEXT_STATE <= T1;\r
- when T1 => NEXT_STATE <= T0;\r
+ when T2 => NEXT_STATE <= T1;\r
+ when T1 => NEXT_STATE <= T0;\r
next_apv_trg <= '1';\r
- when T0 => NEXT_STATE <= DLY0;\r
+ when T0 => NEXT_STATE <= DLY0;\r
next_apv_sync <= '1';\r
- when DLY0 => NEXT_STATE <= DLY1;\r
+ when DLY0 => NEXT_STATE <= DLY1;\r
next_apv_sync <= '1';\r
- when DLY1 => NEXT_STATE <= DLY2;\r
+ when DLY1 => NEXT_STATE <= DLY2;\r
next_apv_sync <= '1';\r
- when DLY2 => NEXT_STATE <= DLY3;\r
+ when DLY2 => NEXT_STATE <= DLY3;\r
next_apv_sync <= '1';\r
- when DLY3 => NEXT_STATE <= DONE;\r
+ when DLY3 => NEXT_STATE <= DONE;\r
next_apv_done <= '1';\r
next_apv_sync <= '1';\r
- when DONE => NEXT_STATE <= SLEEP;\r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process STATE_TRANSFORM;\r
\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_out <= x"0";\r
- when START => bsm_out <= x"1";\r
- when T2 => bsm_out <= x"2";\r
- when T1 => bsm_out <= x"3";\r
- when T0 => bsm_out <= x"4";\r
- when DLY0 => bsm_out <= x"5";\r
- when DLY1 => bsm_out <= x"6";\r
- when DLY2 => bsm_out <= x"7";\r
- when DLY3 => bsm_out <= x"8";\r
- when DONE => bsm_out <= x"9";\r
- when others => bsm_out <= x"f";\r
+ when SLEEP => bsm_out <= x"0";\r
+ when START => bsm_out <= x"1";\r
+ when T2 => bsm_out <= x"2";\r
+ when T1 => bsm_out <= x"3";\r
+ when T0 => bsm_out <= x"4";\r
+ when DLY0 => bsm_out <= x"5";\r
+ when DLY1 => bsm_out <= x"6";\r
+ when DLY2 => bsm_out <= x"7";\r
+ when DLY3 => bsm_out <= x"8";\r
+ when DONE => bsm_out <= x"9";\r
+ when others => bsm_out <= x"f";\r
end case;\r
end process STATE_DECODE;\r
\r
-- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M).\r
THE_APVTRGDONE_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_apv_in,\r
- RESET_A_IN => reset_apv_in,\r
- PULSE_A_IN => apv_done,\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- PULSE_B_OUT => apv_trgdone\r
- );\r
+port map(\r
+ CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_apv_in,\r
+ PULSE_A_IN => apv_done,\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ PULSE_B_OUT => apv_trgdone\r
+);\r
\r
-- output signals\r
apv_trgdone_out <= apv_trgdone;\r
apv_trg_out <= apv_trg;\r
apv_sync_out <= apv_sync;\r
\r
-debug_out(15 downto 0) <= (others => '0'); \r
+debug_out(15 downto 0) <= (others => '0');\r
\r
end behavioral;\r
\r
use work.adcmv3_components.all;\r
\r
entity apv_trg_handler is\r
- port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
- RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
- CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; -- synced reset signal (100MHz master clock)\r
- APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
- APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
- APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
- APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
- APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
- APV_TRG_OUT : out std_logic;\r
- APV_TRGSENT_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz master clock)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
+ APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_TRGSENT_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of apv_trg_handler is\r
\r
- -- state machine signals\r
- type STATES is (SLEEP,START,T2,T1,T0,DEL,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- normal signals\r
- signal apv_trgstart : std_logic;\r
- signal next_apv_trgstart : std_logic;\r
- signal todo_ctr : std_logic_vector(3 downto 0);\r
- signal comb_todo_done : std_logic;\r
- signal delay_ctr : std_logic_vector(3 downto 0);\r
- signal comb_delay_done : std_logic;\r
- signal apv_trgsent : std_logic;\r
- signal apv_trgdone : std_logic;\r
-\r
- -- State machine generates signals\r
- signal next_todo_ctr_ce : std_logic;\r
- signal todo_ctr_ce : std_logic;\r
- signal next_delay_ctr_ce : std_logic;\r
- signal delay_ctr_ce : std_logic;\r
- signal next_delay_ctr_ld : std_logic;\r
- signal delay_ctr_ld : std_logic;\r
- signal next_apv_done : std_logic;\r
- signal apv_done : std_logic;\r
- signal next_apv_trgcnt : std_logic;\r
- signal apv_trgcnt : std_logic;\r
- signal next_apv_trg : std_logic;\r
- signal apv_trg : std_logic;\r
+-- state machine signals\r
+type STATES is (SLEEP,START,T2,T1,T0,DEL,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- normal signals\r
+signal apv_trgstart : std_logic;\r
+signal next_apv_trgstart : std_logic;\r
+signal todo_ctr : std_logic_vector(3 downto 0);\r
+signal comb_todo_done : std_logic;\r
+signal delay_ctr : std_logic_vector(3 downto 0);\r
+signal comb_delay_done : std_logic;\r
+signal apv_trgsent : std_logic;\r
+signal apv_trgdone : std_logic;\r
+\r
+-- State machine generates signals\r
+signal next_todo_ctr_ce : std_logic;\r
+signal todo_ctr_ce : std_logic;\r
+signal next_delay_ctr_ce : std_logic;\r
+signal delay_ctr_ce : std_logic;\r
+signal next_delay_ctr_ld : std_logic;\r
+signal delay_ctr_ld : std_logic;\r
+signal next_apv_done : std_logic;\r
+signal apv_done : std_logic;\r
+signal next_apv_trgcnt : std_logic;\r
+signal apv_trgcnt : std_logic;\r
+signal next_apv_trg : std_logic;\r
+signal apv_trg : std_logic;\r
\r
begin\r
\r
-- APV_TRGSTART_IN crosses a clock domain (100M -> 40M).\r
-next_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; \r
+next_apv_trgstart <= apv_trgstart_in and apv_trgsel_in;\r
\r
THE_APVTRGSTART_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => next_apv_trgstart,\r
- CLK_B_IN => clk_apv_in,\r
- RESET_B_IN => reset_apv_in,\r
- PULSE_B_OUT => apv_trgstart\r
- );\r
+port map(\r
+ CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => next_apv_trgstart,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => reset_apv_in,\r
+ PULSE_B_OUT => apv_trgstart\r
+);\r
\r
-- A statemachine handles all actions for creating the trigger sequence (40MHz domain)\r
-- state registers\r
-STATE_MEM: process( clk_apv_in ) \r
+STATE_MEM: process( clk_apv_in )\r
begin\r
if( rising_edge(clk_apv_in) ) then\r
if( reset_apv_in = '1' ) then\r
CURRENT_STATE <= SLEEP;\r
- todo_ctr_ce <= '0';\r
+ todo_ctr_ce <= '0';\r
delay_ctr_ce <= '0';\r
delay_ctr_ld <= '0';\r
apv_done <= '0';\r
next_apv_trg <= '0';\r
next_apv_trgcnt <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( apv_trgstart = '1' ) then\r
+ when SLEEP => if( apv_trgstart = '1' ) then\r
NEXT_STATE <= START;\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when START => if( comb_todo_done = '1' ) then\r
+ when START => if( comb_todo_done = '1' ) then\r
NEXT_STATE <= DONE;\r
next_apv_done <= '1';\r
else\r
next_delay_ctr_ld <= '1';\r
next_apv_trg <= '1';\r
end if;\r
- when T2 => NEXT_STATE <= T1;\r
+ when T2 => NEXT_STATE <= T1;\r
next_todo_ctr_ce <= '1';\r
next_apv_trgcnt <= '1';\r
- when T1 => NEXT_STATE <= T0;\r
+ when T1 => NEXT_STATE <= T0;\r
next_delay_ctr_ce <= '1';\r
- when T0 => if ( (comb_todo_done = '1') ) then\r
+ when T0 => if ( (comb_todo_done = '1') ) then\r
NEXT_STATE <= DONE;\r
next_apv_done <= '1';\r
elsif( (comb_todo_done = '0') and (comb_delay_done = '0') ) then\r
next_delay_ctr_ld <= '1';\r
next_apv_trg <= '1';\r
end if;\r
- when DEL => if( comb_delay_done = '1' ) then\r
+ when DEL => if( comb_delay_done = '1' ) then\r
NEXT_STATE <= T2;\r
next_delay_ctr_ld <= '1';\r
next_apv_trg <= '1';\r
NEXT_STATE <= DEL;\r
next_delay_ctr_ce <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process STATE_TRANSFORM;\r
\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_out <= x"0";\r
- when START => bsm_out <= x"1";\r
- when T2 => bsm_out <= x"2";\r
- when T1 => bsm_out <= x"3";\r
- when T0 => bsm_out <= x"4";\r
- when DEL => bsm_out <= x"5";\r
- when DONE => bsm_out <= x"6";\r
- when others => bsm_out <= x"f";\r
+ when SLEEP => bsm_out <= x"0";\r
+ when START => bsm_out <= x"1";\r
+ when T2 => bsm_out <= x"2";\r
+ when T1 => bsm_out <= x"3";\r
+ when T0 => bsm_out <= x"4";\r
+ when DEL => bsm_out <= x"5";\r
+ when DONE => bsm_out <= x"6";\r
+ when others => bsm_out <= x"f";\r
end case;\r
end process STATE_DECODE;\r
\r
\r
-- APV_TRGSENT_OUT crosses a clock domain (40M -> 100M).\r
THE_APVTRGSENT_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_apv_in,\r
- RESET_A_IN => reset_apv_in, \r
- PULSE_A_IN => apv_trgcnt,\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- PULSE_B_OUT => apv_trgsent\r
- );\r
+port map(\r
+ CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_apv_in,\r
+ PULSE_A_IN => apv_trgcnt,\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ PULSE_B_OUT => apv_trgsent\r
+);\r
\r
-- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M).\r
THE_APVTRGDONE_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_apv_in,\r
- RESET_A_IN => reset_apv_in,\r
- PULSE_A_IN => apv_done,\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- PULSE_B_OUT => apv_trgdone\r
- );\r
+port map(\r
+ CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_apv_in,\r
+ PULSE_A_IN => apv_done,\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ PULSE_B_OUT => apv_trgdone\r
+);\r
\r
-- output signals\r
apv_trgdone_out <= apv_trgdone;\r
apv_trg_out <= apv_trg;\r
apv_trgsent_out <= apv_trgsent;\r
\r
-debug_out(15 downto 12) <= todo_ctr; \r
-debug_out(11 downto 8) <= delay_ctr; \r
+debug_out(15 downto 12) <= todo_ctr;\r
+debug_out(11 downto 8) <= delay_ctr;\r
debug_out(7) <= delay_ctr_ld;\r
debug_out(6) <= '0';\r
debug_out(5) <= comb_delay_done;\r
use work.adcmv3_components.all;\r
\r
entity apv_trgctrl is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; -- 100MHz clock domain reset\r
- CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
- -- Triggers\r
- SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
- TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
- TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
- STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
- TRG_FOUND_OUT : out std_logic; \r
- -- slow control settings\r
- TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
- TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
- TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
- TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
- TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
- TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
- TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
- -- TRB LVL1 signals\r
- TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
- TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
- TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
- TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
- TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
- TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
- TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter\r
- TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); -- timing trigger counter\r
- -- EDS signals\r
- EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
- EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
- EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
- EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
- EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
- -- APV signals \r
- APV_TRG_OUT : out std_logic;\r
- APV_SYNC_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- 100MHz clock domain reset\r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ -- Triggers\r
+ SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
+ TRG_FOUND_OUT : out std_logic;\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ -- slow control settings\r
+ TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- TRB LVL1 trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
+ TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
+ TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
+ TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local timing trigger counter\r
+ TRB_COUNTER_IN : in std_logic_vector(15 downto 0); -- TRB counter input\r
+ TRB_LD_COUNTER_IN : in std_logic; -- load local counter with TRB counter value\r
+ -- EDS signals\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
+ EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
+ EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
+ EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
+ EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
+ -- APV signals\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of apv_trgctrl is\r
\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of behavioral : architecture is "APV_TRG_CTRL_group";\r
-\r
- -- normal signals\r
- signal apv_trgsel : std_logic_vector(3 downto 0);\r
- signal apv_trgstart : std_logic;\r
- signal apv_trgdone : std_logic_vector(3 downto 0);\r
- signal next_apv_trgdone_all : std_logic;\r
- signal apv_trgdone_all : std_logic;\r
- signal apv_trg : std_logic_vector(3 downto 0);\r
- signal next_apv_trg_all : std_logic;\r
- signal apv_trg_all : std_logic;\r
- signal apv_clk_rst : std_logic; -- 40MHz sync'ed reset signal\r
-\r
- signal sc_trg_stretch : std_logic_vector(3 downto 0);\r
- signal maximum_trg : std_logic_vector(3 downto 0);\r
-\r
- -- EDS fill signals\r
- signal atc_eds_data : std_logic_vector(39 downto 0);\r
- signal atc_eds_start : std_logic;\r
- signal atc_eds_we : std_logic;\r
- signal eds_data : std_logic_vector(39 downto 0);\r
- signal eds_full : std_logic;\r
- signal eds_avail : std_logic;\r
- signal eds_level : std_logic_vector(4 downto 0);\r
- signal trb_release : std_logic;\r
- signal trb_missing : std_logic;\r
- signal trg_found : std_logic;\r
-\r
- signal test_eds_data : std_logic_vector(39 downto 0);\r
-\r
- -- APV signals \r
- signal apv_trgsent : std_logic_vector(3 downto 0);\r
- signal next_apv_trgsent_all : std_logic;\r
- signal apv_trgsent_all : std_logic;\r
- signal apv_sync : std_logic;\r
- signal apv_sync_signal : std_logic;\r
- \r
- signal trb_counter : std_logic_vector(15 downto 0);\r
- signal busy_release : std_logic;\r
-\r
- signal debug : std_logic_vector(63 downto 0);\r
- signal bsm : std_logic_vector(7 downto 0);\r
- \r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behavioral : architecture is "APV_TRG_CTRL_group";\r
+\r
+-- normal signals\r
+signal apv_trgsel : std_logic_vector(3 downto 0);\r
+signal apv_trgstart : std_logic;\r
+signal apv_trgdone : std_logic_vector(3 downto 0);\r
+signal next_apv_trgdone_all : std_logic;\r
+signal apv_trgdone_all : std_logic;\r
+signal apv_trg : std_logic_vector(3 downto 0);\r
+signal next_apv_trg_all : std_logic;\r
+signal apv_trg_all : std_logic;\r
+signal apv_clk_rst : std_logic; -- 40MHz sync'ed reset signal\r
+\r
+signal sc_trg_stretch : std_logic_vector(3 downto 0);\r
+signal maximum_trg : std_logic_vector(3 downto 0);\r
+\r
+-- EDS fill signals\r
+signal atc_eds_data : std_logic_vector(39 downto 0);\r
+signal atc_eds_start : std_logic;\r
+signal atc_eds_we : std_logic;\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_full : std_logic;\r
+signal eds_avail : std_logic;\r
+signal eds_level : std_logic_vector(4 downto 0);\r
+signal trb_release : std_logic;\r
+signal trb_missing : std_logic;\r
+signal trg_found : std_logic;\r
+\r
+signal test_eds_data : std_logic_vector(39 downto 0);\r
+\r
+-- APV signals\r
+signal apv_trgsent : std_logic_vector(3 downto 0);\r
+signal next_apv_trgsent_all : std_logic;\r
+signal apv_trgsent_all : std_logic;\r
+signal apv_sync : std_logic;\r
+signal apv_sync_signal : std_logic;\r
+\r
+signal trb_counter : std_logic_vector(15 downto 0);\r
+signal busy_release : std_logic;\r
+\r
+signal debug : std_logic_vector(63 downto 0);\r
+signal bsm : std_logic_vector(7 downto 0);\r
+\r
begin\r
\r
---------------------------------------------------------------------------\r
-- RESET signal clock domain crossing (100MHz sysclk -> 40MHz APV clock)\r
---------------------------------------------------------------------------\r
THE_RESET_SYNC: state_sync\r
-port map( STATE_A_IN => reset_in,\r
- CLK_B_IN => clk_apv_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => apv_clk_rst\r
- );\r
- \r
+port map(\r
+ STATE_A_IN => reset_in,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => apv_clk_rst\r
+);\r
+\r
---------------------------------------------------------------------------\r
-- TRB trigger (one clock pulse) stretchers\r
---------------------------------------------------------------------------\r
SC_TRG0_STRECH: pulse_stretch\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(0),\r
- PULSE_OUT => sc_trg_stretch(0),\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(0),\r
+ PULSE_OUT => sc_trg_stretch(0),\r
+ DEBUG_OUT => open\r
+);\r
SC_TRG1_STRECH: pulse_stretch\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(1),\r
- PULSE_OUT => sc_trg_stretch(1),\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(1),\r
+ PULSE_OUT => sc_trg_stretch(1),\r
+ DEBUG_OUT => open\r
+);\r
SC_TRG2_STRECH: pulse_stretch\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(2),\r
- PULSE_OUT => sc_trg_stretch(2),\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(2),\r
+ PULSE_OUT => sc_trg_stretch(2),\r
+ DEBUG_OUT => open\r
+);\r
SC_TRG3_STRECH: pulse_stretch\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(3),\r
- PULSE_OUT => sc_trg_stretch(3),\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(3),\r
+ PULSE_OUT => sc_trg_stretch(3),\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- Busy handling\r
-- for generation of APV TRG pulse sequences (like 1-0-0, or 1-0-1, etc.)\r
---------------------------------------------------------------------------\r
THE_REAL_TRG_HANDLER: real_trg_handler\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in, \r
- TIME_TRG_IN => time_trg_in,\r
- TRB_TRG_IN => sc_trg_stretch,\r
- APV_TRGDONE_IN => apv_trgdone_all,\r
- TRG_3_TODO_IN => trg_3_todo_in,\r
- TRG_2_TODO_IN => trg_2_todo_in,\r
- TRG_1_TODO_IN => trg_1_todo_in,\r
- TRG_0_TODO_IN => trg_0_todo_in,\r
- TRG_SETUP_IN => trg_setup_in,\r
- TRG_FOUND_OUT => trg_found,\r
- TRB_TTAG_IN => trb_ttag_in,\r
- TRB_TRND_IN => trb_trnd_in,\r
- TRB_TTYPE_IN => trb_ttype_in,\r
- TRB_TRGRCVD_IN => trb_trgrcvd_in,\r
- TRB_MISSING_OUT => trb_missing,\r
- BUSY_RELEASE_IN => busy_release,\r
- RST_LVL1_COUNTER_IN => trb_rst_counter_in,\r
- LVL1_COUNTER_OUT => trb_counter,\r
- APV_TRGSEL_OUT => apv_trgsel,\r
- APV_TRGSTART_OUT => apv_trgstart,\r
- EDS_DATA_OUT => atc_eds_data,\r
- EDS_START_OUT => atc_eds_start, -- just for debugging\r
- EDS_WE_OUT => atc_eds_we,\r
- EDS_READY_OUT => trb_release,\r
- DBG_FRMCTR_OUT => open,\r
- BSM_OUT => bsm, --open,\r
- DEBUG_OUT => open --debug\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ TIME_TRG_IN => time_trg_in,\r
+ TRB_TRG_IN => sc_trg_stretch,\r
+ APV_TRGDONE_IN => apv_trgdone_all,\r
+ TRG_3_TODO_IN => trg_3_todo_in,\r
+ TRG_2_TODO_IN => trg_2_todo_in,\r
+ TRG_1_TODO_IN => trg_1_todo_in,\r
+ TRG_0_TODO_IN => trg_0_todo_in,\r
+ TRG_SETUP_IN => trg_setup_in,\r
+ TRG_FOUND_OUT => trg_found,\r
+ SECTOR_IN => sector_in,\r
+ TRB_TTAG_IN => trb_ttag_in,\r
+ TRB_TRND_IN => trb_trnd_in,\r
+ TRB_TTYPE_IN => trb_ttype_in,\r
+ TRB_TINFO_IN => trb_tinfo_in,\r
+ TRB_TRGRCVD_IN => trb_trgrcvd_in,\r
+ TRB_MISSING_OUT => trb_missing,\r
+ BUSY_RELEASE_IN => busy_release,\r
+ LVL1_COUNTER_OUT => trb_counter,\r
+ LVL1_COUNTER_IN => trb_counter_in,\r
+ LVL1_LD_COUNTER_IN => trb_ld_counter_in,\r
+ APV_TRGSEL_OUT => apv_trgsel,\r
+ APV_TRGSTART_OUT => apv_trgstart,\r
+ EDS_DATA_OUT => atc_eds_data,\r
+ EDS_START_OUT => atc_eds_start, -- just for debugging\r
+ EDS_WE_OUT => atc_eds_we,\r
+ EDS_READY_OUT => trb_release,\r
+ DBG_FRMCTR_OUT => open,\r
+ BSM_OUT => bsm, --open,\r
+ DEBUG_OUT => open --debug\r
+);\r
\r
-- automatically determine the maximum amount of APV frames per trigger\r
-- mind the delay in this block!\r
THE_MAX_TRG: max_data\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- TODO_3_IN => trg_3_todo_in,\r
- TODO_2_IN => trg_2_todo_in,\r
- TODO_1_IN => trg_1_todo_in,\r
- TODO_0_IN => trg_0_todo_in,\r
- TODO_MAX_OUT => maximum_trg,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ TODO_3_IN => trg_3_todo_in,\r
+ TODO_2_IN => trg_2_todo_in,\r
+ TODO_1_IN => trg_1_todo_in,\r
+ TODO_0_IN => trg_0_todo_in,\r
+ TODO_MAX_OUT => maximum_trg,\r
+ DEBUG_OUT => open\r
+);\r
\r
-- Only for storing last EDS for debugging!\r
THE_TEST_EDS_DATA_PROC: process( clk_in )\r
-- EDS buffer with fill level information\r
---------------------------------------------------------------------------\r
THE_EDS_BUF: eds_buf\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- EDS_DATA_IN => atc_eds_data, -- data from trigger handler\r
- EDS_WE_IN => atc_eds_we, -- write enable from trigger handler\r
- EDS_DONE_IN => eds_done_in, -- release current EDS page\r
- EDS_DATA_OUT => eds_data, -- current EDS data out\r
- EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid\r
- BUF_FULL_OUT => eds_full, -- EDS buffer is full\r
- BUF_LEVEL_OUT => eds_level, -- for debugging\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ EDS_DATA_IN => atc_eds_data, -- data from trigger handler\r
+ EDS_WE_IN => atc_eds_we, -- write enable from trigger handler\r
+ EDS_DONE_IN => eds_done_in, -- release current EDS page\r
+ EDS_DATA_OUT => eds_data, -- current EDS data out\r
+ EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid\r
+ BUF_FULL_OUT => eds_full, -- EDS buffer is full\r
+ BUF_LEVEL_OUT => eds_level, -- for debugging\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- Trigger input 3: normal trigger\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_3: apv_trg_handler\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- APV_TRGSTART_IN => apv_trgstart,\r
- APV_TRGSEL_IN => apv_trgsel(3),\r
- APV_TRG_TODO_IN => trg_3_todo_in,\r
- APV_TRG_DELAY_IN => trg_3_delay_in,\r
- APV_TRGDONE_OUT => apv_trgdone(3),\r
- APV_TRG_OUT => apv_trg(3),\r
- APV_TRGSENT_OUT => apv_trgsent(3),\r
- BSM_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(3),\r
+ APV_TRG_TODO_IN => trg_3_todo_in,\r
+ APV_TRG_DELAY_IN => trg_3_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(3),\r
+ APV_TRG_OUT => apv_trg(3),\r
+ APV_TRGSENT_OUT => apv_trgsent(3),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- Trigger input 2: normal trigger\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_2: apv_trg_handler\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- APV_TRGSTART_IN => apv_trgstart,\r
- APV_TRGSEL_IN => apv_trgsel(2),\r
- APV_TRG_TODO_IN => trg_2_todo_in,\r
- APV_TRG_DELAY_IN => trg_2_delay_in,\r
- APV_TRGDONE_OUT => apv_trgdone(2),\r
- APV_TRG_OUT => apv_trg(2),\r
- APV_TRGSENT_OUT => apv_trgsent(2),\r
- BSM_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(2),\r
+ APV_TRG_TODO_IN => trg_2_todo_in,\r
+ APV_TRG_DELAY_IN => trg_2_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(2),\r
+ APV_TRG_OUT => apv_trg(2),\r
+ APV_TRGSENT_OUT => apv_trgsent(2),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- Trigger input 1: normal trigger\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_1: apv_trg_handler\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- APV_TRGSTART_IN => apv_trgstart,\r
- APV_TRGSEL_IN => apv_trgsel(1),\r
- APV_TRG_TODO_IN => trg_1_todo_in,\r
- APV_TRG_DELAY_IN => trg_1_delay_in,\r
- APV_TRGDONE_OUT => apv_trgdone(1),\r
- APV_TRG_OUT => apv_trg(1),\r
- APV_TRGSENT_OUT => apv_trgsent(1),\r
- BSM_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(1),\r
+ APV_TRG_TODO_IN => trg_1_todo_in,\r
+ APV_TRG_DELAY_IN => trg_1_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(1),\r
+ APV_TRG_OUT => apv_trg(1),\r
+ APV_TRGSENT_OUT => apv_trgsent(1),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- Trigger input 0: normal trigger\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_0: apv_trg_handler\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- APV_TRGSTART_IN => apv_trgstart,\r
- APV_TRGSEL_IN => apv_trgsel(0),\r
- APV_TRG_TODO_IN => trg_0_todo_in,\r
- APV_TRG_DELAY_IN => trg_0_delay_in,\r
- APV_TRGDONE_OUT => apv_trgdone(0),\r
- APV_TRG_OUT => apv_trg(0),\r
- APV_TRGSENT_OUT => apv_trgsent(0),\r
- BSM_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(0),\r
+ APV_TRG_TODO_IN => trg_0_todo_in,\r
+ APV_TRG_DELAY_IN => trg_0_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(0),\r
+ APV_TRG_OUT => apv_trg(0),\r
+ APV_TRGSENT_OUT => apv_trgsent(0),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- APV SYNC trigger signal -- NOT CLEAN, outside trigger logic!\r
---------------------------------------------------------------------------\r
THE_APV_SYNC_HANDLER: apv_sync_handler\r
-port map( CLK_APV_IN => clk_apv_in,\r
- RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in, \r
- APV_TRGSTART_IN => sync_trg_in,\r
- APV_TRGSEL_IN => '1',\r
- APV_TRGDONE_OUT => open,\r
- APV_TRG_OUT => apv_sync_signal,\r
- APV_SYNC_OUT => apv_sync,\r
- BSM_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => sync_trg_in,\r
+ APV_TRGSEL_IN => '1',\r
+ APV_TRGDONE_OUT => open,\r
+ APV_TRG_OUT => apv_sync_signal,\r
+ APV_SYNC_OUT => apv_sync,\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
-- combine all DONE and SENT signals for feedback\r
next_apv_trgdone_all <= apv_trgdone(3) or apv_trgdone(2) or apv_trgdone(1) or apv_trgdone(0);\r
-- ddmmyy - blafasel\r
\r
entity buf_toc is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
- BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
- WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
- FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
- BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
- GOODDATA_OUT : out std_logic; -- APV is on, sent data, process it\r
- BADDATA_OUT : out std_logic; -- APV is on, broken buffer, NO processing, only ERROR HDR\r
- NODATA_OUT : out std_logic; -- APV is off, do not send anything!\r
- READY_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
+ BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
+ WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
+ FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
+ BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
+ GOODDATA_OUT : out std_logic; -- APV is on, sent data, process it\r
+ BADDATA_OUT : out std_logic; -- APV is on, broken buffer, NO processing, only ERROR HDR\r
+ NODATA_OUT : out std_logic; -- APV is off, do not send anything!\r
+ READY_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of buf_toc is\r
\r
- -- components\r
+-- state machine signals\r
+type STATES is (SLEEP,CLEAR,RSTTOC,WATCH,COUNT,GDATA,BDATA,IDATA,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- -- state machine signals\r
- type STATES is (SLEEP,CLEAR,RSTTOC,WATCH,COUNT,GDATA,BDATA,IDATA,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+-- normal signals\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal debug_x : std_logic_vector(15 downto 0);\r
\r
- -- normal signals\r
- signal bsm_x : std_logic_vector(7 downto 0);\r
- signal debug_x : std_logic_vector(15 downto 0);\r
+signal buf_lvl : std_logic_vector(4 downto 0);\r
+signal buf_good : std_logic;\r
+signal buf_broken : std_logic;\r
+signal buf_ignore : std_logic;\r
\r
- signal buf_lvl : std_logic_vector(4 downto 0);\r
- signal buf_good : std_logic;\r
- signal buf_broken : std_logic;\r
- signal buf_ignore : std_logic;\r
- \r
- signal next_gooddata : std_logic;\r
- signal gooddata : std_logic;\r
- signal next_baddata : std_logic;\r
- signal baddata : std_logic;\r
- signal next_nodata : std_logic;\r
- signal nodata : std_logic;\r
- signal next_ready : std_logic;\r
- signal ready : std_logic;\r
+signal next_gooddata : std_logic;\r
+signal gooddata : std_logic;\r
+signal next_baddata : std_logic;\r
+signal baddata : std_logic;\r
+signal next_nodata : std_logic;\r
+signal nodata : std_logic;\r
+signal next_ready : std_logic;\r
+signal ready : std_logic;\r
\r
- signal frames_needed : std_logic_vector(4 downto 0);\r
+signal frames_needed : std_logic_vector(4 downto 0);\r
\r
- signal next_frames_avail : std_logic;\r
- signal frames_avail : std_logic;\r
+signal next_frames_avail : std_logic;\r
+signal frames_avail : std_logic;\r
+\r
+signal toc_ctr : std_logic_vector(3 downto 0);\r
+signal next_toc_rst : std_logic;\r
+signal toc_rst : std_logic;\r
+signal next_toc_ce : std_logic;\r
+signal toc_ce : std_logic;\r
+signal next_toc_hit : std_logic;\r
+signal toc_hit : std_logic;\r
+\r
+signal next_stat_clr : std_logic;\r
+signal stat_clr : std_logic;\r
+\r
+signal stat_good : std_logic;\r
+signal stat_bad : std_logic;\r
+signal stat_ignore : std_logic;\r
\r
- signal toc_ctr : std_logic_vector(3 downto 0);\r
- signal next_toc_rst : std_logic;\r
- signal toc_rst : std_logic;\r
- signal next_toc_ce : std_logic;\r
- signal toc_ce : std_logic;\r
- signal next_toc_hit : std_logic;\r
- signal toc_hit : std_logic;\r
- \r
- signal next_stat_clr : std_logic;\r
- signal stat_clr : std_logic;\r
- \r
- signal stat_good : std_logic;\r
- signal stat_bad : std_logic;\r
- signal stat_ignore : std_logic;\r
- \r
begin\r
\r
-- Aliasing\r
\r
-- state machine for handling synchronisation\r
-- state registers\r
-STATE_MEM: process( clk_in ) \r
+STATE_MEM: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
\r
\r
-- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, waitframe_in, buf_good, buf_ignore, \r
+STATE_TRANSFORM: process( CURRENT_STATE, waitframe_in, buf_good, buf_ignore,\r
buf_start_in, buf_tick_in, frames_avail, toc_hit )\r
begin\r
NEXT_STATE <= SLEEP; -- avoid latches\r
next_ready <= '0';\r
next_stat_clr <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( waitframe_in = '1' ) then\r
+ when SLEEP => if( waitframe_in = '1' ) then\r
NEXT_STATE <= CLEAR;\r
next_stat_clr <= '1';\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when CLEAR => if ( buf_ignore = '1' ) then\r
+ when CLEAR => if ( buf_ignore = '1' ) then\r
NEXT_STATE <= IDATA; -- switched off buffer, ignore it\r
next_nodata <= '1';\r
elsif( buf_good = '1' ) then\r
NEXT_STATE <= BDATA; -- bad buffer, so we skip it immediatly\r
next_baddata <= '1';\r
end if;\r
- when RSTTOC => NEXT_STATE <= WATCH;\r
- when WATCH => if ( frames_avail = '1' ) then\r
+ when RSTTOC => NEXT_STATE <= WATCH;\r
+ when WATCH => if ( frames_avail = '1' ) then\r
NEXT_STATE <= GDATA; -- all frames did arrive\r
next_gooddata <= '1';\r
elsif( (toc_hit = '1') or (buf_good = '0') ) then\r
else\r
NEXT_STATE <= WATCH;\r
end if;\r
- when COUNT => NEXT_STATE <= WATCH;\r
- when GDATA => NEXT_STATE <= DONE;\r
+ when COUNT => NEXT_STATE <= WATCH;\r
+ when GDATA => NEXT_STATE <= DONE;\r
next_ready <= '1';\r
- when BDATA => NEXT_STATE <= DONE;\r
+ when BDATA => NEXT_STATE <= DONE;\r
next_ready <= '1';\r
- when IDATA => NEXT_STATE <= DONE;\r
+ when IDATA => NEXT_STATE <= DONE;\r
next_ready <= '1';\r
- when DONE => if( waitframe_in = '1' ) then\r
+ when DONE => if( waitframe_in = '1' ) then\r
NEXT_STATE <= DONE;\r
next_ready <= '1';\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process STATE_TRANSFORM;\r
\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_x <= x"00";\r
- when CLEAR => bsm_x <= x"01"; \r
- when RSTTOC => bsm_x <= x"02"; \r
- when WATCH => bsm_x <= x"03";\r
- when COUNT => bsm_x <= x"04";\r
- when GDATA => bsm_x <= x"05";\r
- when BDATA => bsm_x <= x"06";\r
- when IDATA => bsm_x <= x"07";\r
- when DONE => bsm_x <= x"08";\r
- when others => bsm_x <= x"ff";\r
+ when SLEEP => bsm_x <= x"00";\r
+ when CLEAR => bsm_x <= x"01";\r
+ when RSTTOC => bsm_x <= x"02";\r
+ when WATCH => bsm_x <= x"03";\r
+ when COUNT => bsm_x <= x"04";\r
+ when GDATA => bsm_x <= x"05";\r
+ when BDATA => bsm_x <= x"06";\r
+ when IDATA => bsm_x <= x"07";\r
+ when DONE => bsm_x <= x"08";\r
+ when others => bsm_x <= x"ff";\r
end case;\r
end process STATE_DECODE;\r
\r
use work.adcmv3_components.all;\r
\r
entity dhdr_buf is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- -- DHDR information block\r
- DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
- DHDR_WE_IN : in std_logic; -- EDS write enable\r
- DHDR_DONE_IN : in std_logic; -- release EDS \r
- DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
- DHDR_AVAILABLE_OUT : out std_logic;\r
- -- trigger busy information\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ -- DHDR information block\r
+ DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
+ DHDR_WE_IN : in std_logic; -- EDS write enable\r
+ DHDR_DONE_IN : in std_logic; -- release EDS\r
+ DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
+ DHDR_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of dhdr_buf is\r
\r
- -- normal signals\r
- signal debug : std_logic_vector(15 downto 0);\r
-\r
- -- Signals for controlling the DHDR buffer memory\r
- signal dhdr_data : std_logic_vector(47 downto 0);\r
- signal dhdr_rd_addr : std_logic_vector(3 downto 0);\r
- signal dhdr_wr_addr : std_logic_vector(3 downto 0);\r
- signal dhdr_wr : std_logic;\r
- signal dhdr_rd : std_logic;\r
- signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
- signal dhdr_free_up : std_logic;\r
- signal dhdr_free_down : std_logic;\r
- signal dhdr_available_x : std_logic; \r
- signal dhdr_available : std_logic; -- at least one valid EDS entry is available\r
- signal dhdr_full_x : std_logic;\r
- signal dhdr_full : std_logic;\r
- \r
+-- normal signals\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
+-- Signals for controlling the DHDR buffer memory\r
+signal dhdr_data : std_logic_vector(47 downto 0);\r
+signal dhdr_rd_addr : std_logic_vector(3 downto 0);\r
+signal dhdr_wr_addr : std_logic_vector(3 downto 0);\r
+signal dhdr_wr : std_logic;\r
+signal dhdr_rd : std_logic;\r
+signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
+signal dhdr_free_up : std_logic;\r
+signal dhdr_free_down : std_logic;\r
+signal dhdr_available_x : std_logic;\r
+signal dhdr_available : std_logic; -- at least one valid EDS entry is available\r
+signal dhdr_full_x : std_logic;\r
+signal dhdr_full : std_logic;\r
+\r
begin\r
\r
-- General process for syncing combinatorial signals\r
begin\r
if( rising_edge(clk_in) ) then\r
if ( reset_in = '1' ) then\r
- dhdr_free_ctr <= "10000";\r
+ dhdr_free_ctr <= b"10000";\r
elsif( (dhdr_free_down = '1') and (dhdr_free_up = '0') ) then\r
- dhdr_free_ctr <= dhdr_free_ctr - 1; \r
+ dhdr_free_ctr <= dhdr_free_ctr - 1;\r
elsif( (dhdr_free_down = '0') and (dhdr_free_up = '1') ) then\r
dhdr_free_ctr <= dhdr_free_ctr + 1;\r
end if;\r
end if;\r
end process THE_DHDR_FREE_COUNTER_PROC;\r
\r
-dhdr_full_x <= '1' when (dhdr_free_ctr = "00000") else '0';\r
+dhdr_full_x <= '1' when (dhdr_free_ctr = b"00001") else '0'; -- was zero before\r
+dhdr_available_x <= '1' when (dhdr_free_ctr /= b"10000") else '0'; \r
+-- danger. may also fail in case you release an entry before reserving it!\r
+\r
+-- replace this ugly rd/wr/free counters and the DPRAM by a FIFO.\r
\r
-- A 16x32b DPRAM is used for buffering the DataHeaDeR (DHDR)\r
THE_DHDR_BUFFER: dhdr_buffer_dpram\r
-port map( WRADDRESS => dhdr_wr_addr,\r
- DATA => dhdr_data_in,\r
- WRCLOCK => clk_in, \r
- WE => dhdr_we_in, \r
- WRCLOCKEN => '1', \r
- RDADDRESS => dhdr_rd_addr, \r
- RDCLOCK => clk_in, \r
- RDCLOCKEN => '1', \r
- RESET => reset_in, \r
- Q => dhdr_data\r
- );\r
+port map(\r
+ WRADDRESS => dhdr_wr_addr,\r
+ DATA => dhdr_data_in,\r
+ WRCLOCK => clk_in,\r
+ WE => dhdr_we_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => dhdr_rd_addr,\r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => dhdr_data\r
+);\r
\r
-- Are there any EDS to work on?\r
-dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0';\r
+--dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0';\r
+-- Epic fail: take 17 fast triggers => WR_ADDR = 1.\r
+-- one slow IPU transfer => RD_ADDR = 1.\r
+-- and as (1 /= 1) is false, the buffer is empty, blocking the next IPU transfer.\r
\r
-- Debug signals\r
debug(15 downto 0) <= (others => '0');\r
use work.adcmv3_components.all;\r
\r
entity eds_buf is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- -- EDS input, all synced to CLK_IN\r
- EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
- EDS_WE_IN : in std_logic; -- EDS write enable\r
- EDS_DONE_IN : in std_logic; -- release EDS \r
- EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
- EDS_AVAILABLE_OUT : out std_logic;\r
- -- trigger busy information\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ -- EDS input, all synced to CLK_IN\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
+ EDS_WE_IN : in std_logic; -- EDS write enable\r
+ EDS_DONE_IN : in std_logic; -- release EDS\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ EDS_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of eds_buf is\r
\r
- -- normal signals\r
- signal debug : std_logic_vector(15 downto 0);\r
-\r
- -- Signals for controlling the EDS buffer memory\r
- signal eds_data : std_logic_vector(39 downto 0);\r
- signal eds_rd_addr : std_logic_vector(3 downto 0);\r
- signal eds_wr_addr : std_logic_vector(3 downto 0);\r
- signal eds_wr : std_logic;\r
- signal eds_rd : std_logic;\r
- signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
- signal eds_free_up : std_logic;\r
- signal eds_free_down : std_logic;\r
- signal eds_available_x : std_logic; \r
- signal eds_available : std_logic; -- at least one valid EDS entry is available\r
- signal eds_full_x : std_logic;\r
- signal eds_full : std_logic;\r
- \r
+-- normal signals\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
+-- Signals for controlling the EDS buffer memory\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_rd_addr : std_logic_vector(3 downto 0);\r
+signal eds_wr_addr : std_logic_vector(3 downto 0);\r
+signal eds_wr : std_logic;\r
+signal eds_rd : std_logic;\r
+signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
+signal eds_free_up : std_logic;\r
+signal eds_free_down : std_logic;\r
+signal eds_available_x : std_logic;\r
+signal eds_available : std_logic; -- at least one valid EDS entry is available\r
+signal eds_full_x : std_logic;\r
+signal eds_full : std_logic;\r
+\r
begin\r
\r
-- General process for syncing combinatorial signals\r
begin\r
if( rising_edge(clk_in) ) then\r
if ( reset_in = '1' ) then\r
- eds_free_ctr <= "10000";\r
+ eds_free_ctr <= b"10000";\r
elsif( eds_free_down = '1' and eds_free_up = '0' ) then\r
- eds_free_ctr <= eds_free_ctr - 1; \r
+ eds_free_ctr <= eds_free_ctr - 1;\r
elsif( eds_free_down = '0' and eds_free_up = '1' ) then\r
eds_free_ctr <= eds_free_ctr + 1;\r
end if;\r
end if;\r
end process THE_EDS_FREE_COUNTER_PROC;\r
\r
-eds_full_x <= '1' when (eds_free_ctr = "00000") else '0';\r
+eds_full_x <= '1' when (eds_free_ctr = b"00000") else '0';\r
+eds_available_x <= '1' when (eds_free_ctr /= b"10000") else '0'; \r
+-- danger. may also fail in case you release an entry before reserving it!\r
+\r
+-- replace this ugly rd/wr/free counters and the DPRAM by a FIFO.\r
\r
-- A 16x40b DPRAM is used for buffering the EventDataSheets (EDS)\r
THE_EDS_BUFFER: eds_buffer_dpram\r
-port map( WRADDRESS => eds_wr_addr,\r
- DATA => eds_data_in,\r
- WRCLOCK => clk_in, \r
- WE => eds_we_in, \r
- WRCLOCKEN => '1', \r
- RDADDRESS => eds_rd_addr, \r
- RDCLOCK => clk_in, \r
- RDCLOCKEN => '1', \r
- RESET => reset_in, \r
- Q => eds_data\r
- );\r
+port map(\r
+ WRADDRESS => eds_wr_addr,\r
+ DATA => eds_data_in,\r
+ WRCLOCK => clk_in,\r
+ WE => eds_we_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => eds_rd_addr,\r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => eds_data\r
+);\r
\r
-- Are there any EDS to work on?\r
-eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0';\r
+--eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0';\r
+-- epic fail: cut'n'paste error from dhdr_buf.vhd\r
\r
-- Debug signals\r
debug(15 downto 0) <= (others => '0');\r
CoreType=LPM\r
CoreStatus=Demo\r
CoreName=FIFO\r
-CoreRevision=4.5\r
+CoreRevision=4.7\r
ModuleName=fifo_16x11\r
SourceFormat=VHDL\r
ParameterFileVersion=1.0\r
-Date=03/03/2009\r
-Time=16:26:00\r
+Date=03/11/2010\r
+Time=10:33:40\r
\r
[Parameters]\r
Verilog=0\r
PeAssert=10\r
PeDeassert=12\r
FullFlg=0\r
-PfMode=Static - Single Threshold\r
-PfAssert=508\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=15\r
PfDeassert=506\r
RDataCount=1\r
EnECC=0\r
--- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 4.5
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 11 -depth 16 -no_enable -pe -1 -pf -1 -fill -e
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 11 -depth 16 -no_enable -pe -1 -pf -1 -fill -e
--- Tue Mar 03 16:26:00 2009
+-- Thu Mar 11 10:33:40 2010
library IEEE;
use IEEE.std_logic_1164.all;
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 4.5
--- Tue Mar 03 16:26:00 2009
+-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+-- Thu Mar 11 10:33:40 2010
-- parameterized module component declaration
component fifo_16x11
-- Only channels with GOODDATA are taken into account.\r
\r
entity frmctr_check is\r
- port( CLK_IN : in std_logic;\r
- GOODDATA_IN : in std_logic_vector(15 downto 0);\r
- FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
- FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
- FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
+ FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of frmctr_check is\r
\r
- -- normal signals\r
- signal debug_x : std_logic_vector(15 downto 0);\r
+-- normal signals\r
+signal debug_x : std_logic_vector(15 downto 0);\r
+\r
+signal next_frc_match : std_logic_vector(15 downto 0);\r
+signal frc_match : std_logic_vector(15 downto 0);\r
+signal next_frc_error : std_logic;\r
+signal frc_error : std_logic;\r
\r
- signal next_frc_match : std_logic_vector(15 downto 0); \r
- signal frc_match : std_logic_vector(15 downto 0); \r
- signal next_frc_error : std_logic;\r
- signal frc_error : std_logic;\r
- \r
begin\r
\r
-- Sync process\r
use work.adcmv3_components.all;\r
\r
entity I2C_GSTART is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- START_IN : in std_logic; \r
- DOSTART_IN : in std_logic; \r
- I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
- SDONE_OUT : out std_logic;\r
- SOK_OUT : out std_logic;\r
- SDA_IN : in std_logic;\r
- SCL_IN : in std_logic;\r
- R_SCL_OUT : out std_logic;\r
- S_SCL_OUT : out std_logic;\r
- R_SDA_OUT : out std_logic;\r
- S_SDA_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(3 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ DOSTART_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ SDONE_OUT : out std_logic;\r
+ SOK_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+);\r
end entity;\r
\r
architecture Behavioral of I2C_GSTART is\r
\r
-- Signals\r
- type STATES is (SLEEP,P_SCL,WCTR0,P_SDA,WCTR1,P_CHK,S_CHK0,RS_SDA,S_CHK1,ERROR,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+type STATES is (SLEEP,P_SCL,WCTR0,P_SDA,WCTR1,P_CHK,S_CHK0,RS_SDA,S_CHK1,ERROR,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- signal bsm : std_logic_vector(3 downto 0);\r
- signal cctr : std_logic_vector(7 downto 0); -- counter for bit length\r
+signal bsm : std_logic_vector(3 downto 0);\r
+signal cctr : std_logic_vector(7 downto 0); -- counter for bit length\r
\r
- signal cycdone_x : std_logic;\r
- signal cycdone : std_logic; -- one counter period done\r
+signal cycdone_x : std_logic;\r
+signal cycdone : std_logic; -- one counter period done\r
\r
- signal load_cyc_x : std_logic;\r
- signal load_cyc : std_logic;\r
- signal dec_cyc_x : std_logic;\r
- signal dec_cyc : std_logic; \r
- signal sdone_x : std_logic;\r
- signal sdone : std_logic; -- Start/Stop done\r
- signal sok_x : std_logic;\r
- signal sok : std_logic; -- Start/Stop OK\r
+signal load_cyc_x : std_logic;\r
+signal load_cyc : std_logic;\r
+signal dec_cyc_x : std_logic;\r
+signal dec_cyc : std_logic;\r
+signal sdone_x : std_logic;\r
+signal sdone : std_logic; -- Start/Stop done\r
+signal sok_x : std_logic;\r
+signal sok : std_logic; -- Start/Stop OK\r
\r
- signal r_scl : std_logic;\r
- signal s_scl : std_logic;\r
- signal r_sda : std_logic;\r
- signal s_sda : std_logic;\r
+signal r_scl : std_logic;\r
+signal s_scl : std_logic;\r
+signal r_sda : std_logic;\r
+signal s_sda : std_logic;\r
\r
-- Moduls\r
\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
cctr <= (others => '0');\r
- elsif( load_cyc = '1' ) then \r
+ elsif( load_cyc = '1' ) then\r
cctr <= i2c_speed_in;\r
elsif( dec_cyc = '1' ) then\r
cctr <= cctr - 1;\r
sdone_x <= '0';\r
sok_x <= '1';\r
case CURRENT_STATE is\r
- when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then\r
+ when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then\r
NEXT_STATE <= S_CHK0; -- generate a start condition\r
load_cyc_x <= '1';\r
elsif( (dostart_in = '1') and (start_in = '0') ) then\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when P_SCL => NEXT_STATE <= WCTR0;\r
+ when P_SCL => NEXT_STATE <= WCTR0;\r
dec_cyc_x <= '1';\r
- when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then\r
+ when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then\r
NEXT_STATE <= RS_SDA;\r
else\r
NEXT_STATE <= ERROR;\r
sok_x <= '0';\r
end if;\r
- when RS_SDA => NEXT_STATE <= WCTR0;\r
+ when RS_SDA => NEXT_STATE <= WCTR0;\r
dec_cyc_x <= '1';\r
- when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then\r
+ when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then\r
NEXT_STATE <= S_CHK1;\r
elsif( (cycdone = '1') and (start_in = '0') ) then\r
NEXT_STATE <= P_SDA;\r
NEXT_STATE <= WCTR0;\r
dec_cyc_x <= '1';\r
end if;\r
- when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then\r
+ when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= ERROR;\r
sok_x <= '0';\r
end if;\r
- when P_SDA => NEXT_STATE <= WCTR1;\r
+ when P_SDA => NEXT_STATE <= WCTR1;\r
dec_cyc_x <= '1';\r
- when WCTR1 => if( (cycdone = '1') ) then\r
+ when WCTR1 => if( (cycdone = '1') ) then\r
NEXT_STATE <= P_CHK;\r
else\r
NEXT_STATE <= WCTR1;\r
dec_cyc_x <= '1';\r
end if;\r
- when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then\r
+ when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then\r
NEXT_STATE <= DONE;\r
sdone_x <= '1';\r
else\r
NEXT_STATE <= ERROR;\r
sok_x <= '0';\r
end if;\r
- when ERROR => if( dostart_in = '0' ) then\r
+ when ERROR => if( dostart_in = '0' ) then\r
NEXT_STATE <= SLEEP;\r
else\r
NEXT_STATE <= ERROR;\r
sdone_x <= '1';\r
sok_x <= '0';\r
end if;\r
- when DONE => if( dostart_in = '0' ) then\r
+ when DONE => if( dostart_in = '0' ) then\r
NEXT_STATE <= SLEEP;\r
else\r
NEXT_STATE <= DONE;\r
sdone_x <= '1';\r
end if;\r
- when others => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
DECODE: process(CURRENT_STATE)\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm <= x"0";\r
- when S_CHK0 => bsm <= x"1";\r
- when RS_SDA => bsm <= x"2";\r
- when P_SCL => bsm <= x"3";\r
- when WCTR0 => bsm <= x"4";\r
- when S_CHK1 => bsm <= x"5";\r
- when P_SDA => bsm <= x"6";\r
- when WCTR1 => bsm <= x"7";\r
- when P_CHK => bsm <= x"8";\r
- when DONE => bsm <= x"9";\r
- when ERROR => bsm <= x"e";\r
- when others => bsm <= x"f";\r
+ when SLEEP => bsm <= x"0";\r
+ when S_CHK0 => bsm <= x"1";\r
+ when RS_SDA => bsm <= x"2";\r
+ when P_SCL => bsm <= x"3";\r
+ when WCTR0 => bsm <= x"4";\r
+ when S_CHK1 => bsm <= x"5";\r
+ when P_SDA => bsm <= x"6";\r
+ when WCTR1 => bsm <= x"7";\r
+ when P_CHK => bsm <= x"8";\r
+ when DONE => bsm <= x"9";\r
+ when ERROR => bsm <= x"e";\r
+ when others => bsm <= x"f";\r
end case;\r
end process DECODE;\r
\r
use work.adcmv3_components.all;\r
\r
entity i2c_master is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of i2c_master is\r
\r
-- Signals\r
- type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- slave bus signals\r
- signal slv_busy_x : std_logic;\r
- signal slv_busy : std_logic;\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
- signal reg_busy : std_logic;\r
-\r
- signal status_data : std_logic_vector(31 downto 0);\r
- signal i2c_debug : std_logic_vector(31 downto 0);\r
+type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- slave bus signals\r
+signal slv_busy_x : std_logic;\r
+signal slv_busy : std_logic;\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
+\r
+signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
+signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+signal reg_busy : std_logic;\r
+\r
+signal status_data : std_logic_vector(31 downto 0);\r
+signal i2c_debug : std_logic_vector(31 downto 0);\r
\r
begin\r
\r
---------------------------------------------------------\r
\r
THE_I2C_SLIM: i2c_slim\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- I2C command / setup\r
- I2C_GO_IN => reg_slv_data_in(31),\r
- ACTION_IN => reg_slv_data_in(30),\r
- I2C_SPEED_IN => reg_slv_data_in(29 downto 24),\r
- I2C_ADR_IN => reg_slv_data_in(23 downto 16),\r
- I2C_CMD_IN => reg_slv_data_in(15 downto 8),\r
- I2C_DW_IN => reg_slv_data_in(7 downto 0),\r
- I2C_DR_OUT => status_data(7 downto 0),\r
- STATUS_OUT => status_data(31 downto 24),\r
- I2C_BUSY_OUT => reg_busy,\r
- -- I2C connections\r
- SDA_IN => sda_in,\r
- SDA_OUT => sda_out,\r
- SCL_IN => scl_in,\r
- SCL_OUT => scl_out,\r
- -- Debug\r
- STAT => i2c_debug\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => reg_slv_data_in(31),\r
+ ACTION_IN => reg_slv_data_in(30),\r
+ I2C_SPEED_IN => reg_slv_data_in(29 downto 24),\r
+ I2C_ADR_IN => reg_slv_data_in(23 downto 16),\r
+ I2C_CMD_IN => reg_slv_data_in(15 downto 8),\r
+ I2C_DW_IN => reg_slv_data_in(7 downto 0),\r
+ I2C_DR_OUT => status_data(7 downto 0),\r
+ STATUS_OUT => status_data(31 downto 24),\r
+ I2C_BUSY_OUT => reg_busy,\r
+ -- I2C connections\r
+ SDA_IN => sda_in,\r
+ SDA_OUT => sda_out,\r
+ SCL_IN => scl_in,\r
+ SCL_OUT => scl_out,\r
+ -- Debug\r
+ STAT => i2c_debug\r
+);\r
\r
status_data(23 downto 21) <= (others => '0');\r
status_data(20 downto 16) <= i2c_debug(4 downto 0);\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
NEXT_STATE <= RD_RDY;\r
store_rd_x <= '1';\r
elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
NEXT_STATE <= WR_BSY;\r
slv_busy_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when RD_BSY => if( slv_read_in = '0' ) then\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_BSY;\r
slv_busy_x <= '1';\r
end if;\r
- when WR_BSY => if( slv_write_in = '0' ) then\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_BSY;\r
slv_busy_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
-entity I2C_SENDB is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- DOBYTE_IN : in std_logic; \r
- I2C_SPEED_IN : in std_logic_vector( 7 downto 0 );\r
- I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); \r
- I2C_BACK_OUT : out std_logic_vector( 8 downto 0 );\r
- SDA_IN : in std_logic;\r
- R_SDA_OUT : out std_logic;\r
- S_SDA_OUT : out std_logic;\r
--- SCL_IN : in std_logic;\r
- R_SCL_OUT : out std_logic;\r
- S_SCL_OUT : out std_logic;\r
- BDONE_OUT : out std_logic;\r
- BOK_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector( 3 downto 0 )\r
- );\r
+entity i2c_sendb is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ DOBYTE_IN : in std_logic;\r
+ I2C_SPEED_IN : in std_logic_vector( 7 downto 0 );\r
+ I2C_BYTE_IN : in std_logic_vector( 8 downto 0 );\r
+ I2C_BACK_OUT : out std_logic_vector( 8 downto 0 );\r
+ SDA_IN : in std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+-- SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ BDONE_OUT : out std_logic;\r
+ BOK_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector( 3 downto 0 )\r
+);\r
end entity;\r
\r
-architecture Behavioral of I2C_SENDB is\r
+architecture Behavioral of i2c_sendb is\r
\r
-- Signals\r
- type STATES is (SLEEP,LCL,WCL,LCH,WCH,FREE,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+type STATES is (SLEEP,LCL,WCL,LCH,WCH,FREE,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- signal bsm : std_logic_vector( 3 downto 0 );\r
+signal bsm : std_logic_vector( 3 downto 0 );\r
\r
- signal inc_bit_x : std_logic;\r
- signal inc_bit : std_logic; -- increment bit counter for byte to send\r
- signal rst_bit_x : std_logic;\r
- signal rst_bit : std_logic; -- reset bit counter for byte to send\r
- signal load_cyc_x : std_logic;\r
- signal load_cyc : std_logic; -- load cycle counter (SCL length)\r
- signal dec_cyc_x : std_logic;\r
- signal dec_cyc : std_logic; -- decrement cycle counter (SCL length)\r
- signal load_sr_x : std_logic;\r
- signal load_sr : std_logic; -- load output shift register\r
- signal shift_o_x : std_logic;\r
- signal shift_o : std_logic; -- output shift register control\r
- signal shift_i_x : std_logic;\r
- signal shift_i : std_logic; -- input shift register control\r
- signal bdone_x : std_logic;\r
- signal bdone : std_logic;\r
- signal r_scl_x : std_logic;\r
- signal r_scl : std_logic; -- output for SCL \r
- signal s_scl_x : std_logic;\r
- signal s_scl : std_logic; -- output for SCL\r
+signal inc_bit_x : std_logic;\r
+signal inc_bit : std_logic; -- increment bit counter for byte to send\r
+signal rst_bit_x : std_logic;\r
+signal rst_bit : std_logic; -- reset bit counter for byte to send\r
+signal load_cyc_x : std_logic;\r
+signal load_cyc : std_logic; -- load cycle counter (SCL length)\r
+signal dec_cyc_x : std_logic;\r
+signal dec_cyc : std_logic; -- decrement cycle counter (SCL length)\r
+signal load_sr_x : std_logic;\r
+signal load_sr : std_logic; -- load output shift register\r
+signal shift_o_x : std_logic;\r
+signal shift_o : std_logic; -- output shift register control\r
+signal shift_i_x : std_logic;\r
+signal shift_i : std_logic; -- input shift register control\r
+signal bdone_x : std_logic;\r
+signal bdone : std_logic;\r
+signal r_scl_x : std_logic;\r
+signal r_scl : std_logic; -- output for SCL\r
+signal s_scl_x : std_logic;\r
+signal s_scl : std_logic; -- output for SCL\r
\r
- signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9)\r
- signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length\r
- signal bok : std_logic;\r
- signal cycdone : std_logic; -- one counter period done\r
- signal bytedone : std_logic; -- all bits sents\r
- signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
- signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out\r
- signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
- signal r_sda : std_logic; -- output for SDA\r
- signal s_sda : std_logic; -- output for SDA\r
- signal load : std_logic; -- delay register\r
- signal i2c_d : std_logic; -- auxiliary register\r
+signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9)\r
+signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length\r
+signal bok : std_logic;\r
+signal cycdone : std_logic; -- one counter period done\r
+signal bytedone : std_logic; -- all bits sents\r
+signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
+signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out\r
+signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
+signal r_sda : std_logic; -- output for SDA\r
+signal s_sda : std_logic; -- output for SDA\r
+signal load : std_logic; -- delay register\r
+signal i2c_d : std_logic; -- auxiliary register\r
\r
-- Moduls\r
\r
begin\r
\r
--- Bit counter (for byte to send)\r
+-- Bit counter (for byte to send)\r
THE_BIT_CTR_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
cctr <= (others => '0');\r
- elsif( load_cyc = '1' ) then \r
+ elsif( load_cyc = '1' ) then\r
cctr <= i2c_speed_in;\r
elsif( dec_cyc = '1' ) then\r
cctr <= cctr - 1;\r
\r
-- end of cycle recognition\r
cycdone <= '1' when (cctr = x"00") else '0';\r
- \r
+\r
-- Bit output\r
THE_BIT_OUT_PROC: process( clk_in )\r
begin\r
-- Bit input\r
THE_BIT_IN_PROC: process( clk_in )\r
begin\r
- if( rising_edge(clk_in) ) then \r
+ if( rising_edge(clk_in) ) then\r
if ( reset_in = '1' ) then\r
in_sr <= (others => '1');\r
elsif( shift_o = '1' ) then\r
r_scl_x <= '0';\r
s_scl_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( dobyte_in = '1' ) then\r
+ when SLEEP => if( dobyte_in = '1' ) then\r
NEXT_STATE <= LCL;\r
inc_bit_x <= '1';\r
load_cyc_x <= '1';\r
NEXT_STATE <= SLEEP;\r
load_sr_x <= '1';\r
end if;\r
- when LCL => NEXT_STATE <= WCL;\r
+ when LCL => NEXT_STATE <= WCL;\r
dec_cyc_x <= '1';\r
- when WCL => if( cycdone = '1' ) then\r
+ when WCL => if( cycdone = '1' ) then\r
NEXT_STATE <= LCH;\r
load_cyc_x <= '1';\r
s_scl_x <= '1';\r
NEXT_STATE <= WCL;\r
dec_cyc_x <= '1';\r
end if;\r
- when LCH => NEXT_STATE <= WCH;\r
+ when LCH => NEXT_STATE <= WCH;\r
dec_cyc_x <= '1';\r
- when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then\r
+ when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then\r
NEXT_STATE <= LCL;\r
inc_bit_x <= '1';\r
load_cyc_x <= '1';\r
NEXT_STATE <= WCH;\r
dec_cyc_x <= '1';\r
end if;\r
- when FREE => NEXT_STATE <= DONE;\r
+ when FREE => NEXT_STATE <= DONE;\r
rst_bit_x <= '1';\r
bdone_x <= '1';\r
- when DONE => if( dobyte_in = '0' ) then\r
+ when DONE => if( dobyte_in = '0' ) then\r
NEXT_STATE <= SLEEP;\r
else\r
NEXT_STATE <= DONE;\r
bdone_x <= '1';\r
end if;\r
-- Just in case...\r
- when others => NEXT_STATE <= SLEEP; \r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
DECODE: process(CURRENT_STATE)\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm <= x"0";\r
- when LCL => bsm <= x"1";\r
- when WCL => bsm <= x"2";\r
- when LCH => bsm <= x"3";\r
- when WCH => bsm <= x"4";\r
- when FREE => bsm <= x"5";\r
- when DONE => bsm <= x"6";\r
- when others => bsm <= x"f";\r
- end case; \r
+ when SLEEP => bsm <= x"0";\r
+ when LCL => bsm <= x"1";\r
+ when WCL => bsm <= x"2";\r
+ when LCH => bsm <= x"3";\r
+ when WCH => bsm <= x"4";\r
+ when FREE => bsm <= x"5";\r
+ when DONE => bsm <= x"6";\r
+ when others => bsm <= x"f";\r
+ end case;\r
end process DECODE;\r
\r
-- SCL and SDA output pulses\r
r_sda <= '0';\r
s_sda <= '0';\r
else\r
- load <= shift_o; \r
+ load <= shift_o;\r
r_sda <= load and not i2c_d;\r
s_sda <= load and i2c_d;\r
end if;\r
bdone_out <= bdone;\r
bok_out <= bok;\r
\r
--- Debugging \r
+-- Debugging\r
bsm_out <= bsm;\r
\r
end Behavioral;\r
-- REMARK: this is not a bug, but a feature....\r
\r
entity i2c_slim is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- I2C command / setup\r
- I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
- ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
- I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
- I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
- I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
- I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
- I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
- STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
- I2C_BUSY_OUT : out std_logic;\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- -- Debug\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- I2C command / setup\r
+ I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
+ ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
+ I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
+ I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
+ STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
+ I2C_BUSY_OUT : out std_logic;\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Debug\r
+ STAT : out std_logic_vector(31 downto 0)\r
+);\r
end i2c_slim;\r
\r
architecture Behavioral of i2c_slim is\r
\r
-- Signals\r
- type STATES is (SLEEP,LOADA,GSTART,SENDA,LOADC,SENDC,LOADD,SENDD,GSTOP,INC,\r
- E_START,E_ADDR,E_CMD,E_WD,E_RSTART,E_RADDR,DONE,FAILED,CLRERR);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
- \r
- signal bsm : std_logic_vector( 4 downto 0 );\r
- signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle\r
+type STATES is (SLEEP,LOADA,GSTART,SENDA,LOADC,SENDC,LOADD,SENDD,GSTOP,INC,\r
+ E_START,E_ADDR,E_CMD,E_WD,E_RSTART,E_RADDR,DONE,FAILED,CLRERR);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- signal start_x : std_logic;\r
- signal start : std_logic; -- '0' => generate STOP, '1' => generate START\r
- signal dostart_x : std_logic;\r
- signal dostart : std_logic; -- trigger the GenStart module\r
- signal dobyte_x : std_logic;\r
- signal dobyte : std_logic; -- trigger the ByteSend module\r
- signal i2c_done_x : std_logic;\r
- signal i2c_done : std_logic; -- acknowledge signal to the outside world\r
- signal running_x : std_logic;\r
- signal running : std_logic; -- legacy\r
+signal bsm : std_logic_vector( 4 downto 0 );\r
+signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle\r
\r
- signal load_a_x : std_logic;\r
- signal load_a : std_logic;\r
- signal load_c_x : std_logic;\r
- signal load_c : std_logic;\r
- signal load_d_x : std_logic;\r
- signal load_d : std_logic;\r
+signal start_x : std_logic;\r
+signal start : std_logic; -- '0' => generate STOP, '1' => generate START\r
+signal dostart_x : std_logic;\r
+signal dostart : std_logic; -- trigger the GenStart module\r
+signal dobyte_x : std_logic;\r
+signal dobyte : std_logic; -- trigger the ByteSend module\r
+signal i2c_done_x : std_logic;\r
+signal i2c_done : std_logic; -- acknowledge signal to the outside world\r
+signal running_x : std_logic;\r
+signal running : std_logic; -- legacy\r
\r
- signal sdone : std_logic; -- acknowledge signal from GenStart module\r
- signal sok : std_logic; -- status signal from GenStart module\r
- signal bdone : std_logic; -- acknowledge signal from SendByte module\r
- signal bok : std_logic; -- status signal from SendByte module\r
- signal e_sf : std_logic; -- Start failed\r
- signal e_anak : std_logic; -- Adress byte NAK\r
- signal e_cnak : std_logic; -- Command byte NAK\r
- signal e_dnak : std_logic; -- Data byte NAK\r
- signal e_rsf : std_logic; -- Repeated Start failed\r
- signal e_ranak : std_logic; -- Repeated Adress NAK\r
- signal i2c_byte : std_logic_vector( 8 downto 0 );\r
- signal i2c_dr : std_logic_vector( 8 downto 0 );\r
+signal load_a_x : std_logic;\r
+signal load_a : std_logic;\r
+signal load_c_x : std_logic;\r
+signal load_c : std_logic;\r
+signal load_d_x : std_logic;\r
+signal load_d : std_logic;\r
\r
- signal s_scl : std_logic;\r
- signal r_scl : std_logic;\r
- signal s_sda : std_logic;\r
- signal r_sda : std_logic;\r
- signal r_scl_gs : std_logic;\r
- signal s_scl_gs : std_logic;\r
- signal r_sda_gs : std_logic;\r
- signal s_sda_gs : std_logic;\r
- signal r_scl_sb : std_logic;\r
- signal s_scl_sb : std_logic;\r
- signal r_sda_sb : std_logic;\r
- signal s_sda_sb : std_logic;\r
+signal sdone : std_logic; -- acknowledge signal from GenStart module\r
+signal sok : std_logic; -- status signal from GenStart module\r
+signal bdone : std_logic; -- acknowledge signal from SendByte module\r
+signal bok : std_logic; -- status signal from SendByte module\r
+signal e_sf : std_logic; -- Start failed\r
+signal e_anak : std_logic; -- Adress byte NAK\r
+signal e_cnak : std_logic; -- Command byte NAK\r
+signal e_dnak : std_logic; -- Data byte NAK\r
+signal e_rsf : std_logic; -- Repeated Start failed\r
+signal e_ranak : std_logic; -- Repeated Adress NAK\r
+signal i2c_byte : std_logic_vector( 8 downto 0 );\r
+signal i2c_dr : std_logic_vector( 8 downto 0 );\r
\r
- signal gs_debug : std_logic_vector(3 downto 0);\r
+signal s_scl : std_logic;\r
+signal r_scl : std_logic;\r
+signal s_sda : std_logic;\r
+signal r_sda : std_logic;\r
+signal r_scl_gs : std_logic;\r
+signal s_scl_gs : std_logic;\r
+signal r_sda_gs : std_logic;\r
+signal s_sda_gs : std_logic;\r
+signal r_scl_sb : std_logic;\r
+signal s_scl_sb : std_logic;\r
+signal r_sda_sb : std_logic;\r
+signal s_sda_sb : std_logic;\r
\r
- signal i2c_speed : std_logic_vector(7 downto 0);\r
+signal gs_debug : std_logic_vector(3 downto 0);\r
+\r
+signal i2c_speed : std_logic_vector(7 downto 0);\r
\r
begin\r
\r
load_c_x <= '0';\r
load_d_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( i2c_go_in = '1' ) then\r
+ when SLEEP => if( i2c_go_in = '1' ) then\r
NEXT_STATE <= CLRERR;\r
else\r
NEXT_STATE <= SLEEP;\r
running_x <= '0';\r
end if;\r
- when CLRERR => NEXT_STATE <= LOADA;\r
+ when CLRERR => NEXT_STATE <= LOADA;\r
load_a_x <= '1';\r
- when LOADA => NEXT_STATE <= GSTART;\r
+ when LOADA => NEXT_STATE <= GSTART;\r
start_x <= '1';\r
dostart_x <= '1';\r
- when GSTART => if ( (sdone = '1') and (sok = '1') ) then\r
+ when GSTART => if ( (sdone = '1') and (sok = '1') ) then\r
NEXT_STATE <= SENDA;\r
dobyte_x <= '1';\r
elsif( (sdone = '1') and (sok = '0') and (phase = '0') ) then\r
start_x <= '1';\r
dostart_x <= '1';\r
end if;\r
- when E_START => NEXT_STATE <= FAILED;\r
+ when E_START => NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
- when E_RSTART => NEXT_STATE <= FAILED;\r
+ when E_RSTART => NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
- when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
NEXT_STATE <= LOADC; -- I2C write\r
- load_c_x <= '1'; \r
+ load_c_x <= '1';\r
elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then\r
- NEXT_STATE <= LOADC; -- I2C read, send register address\r
+ NEXT_STATE <= LOADC; -- I2C read, send register address\r
load_c_x <= '1';\r
elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then\r
- NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte\r
+ NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte\r
load_d_x <= '1';\r
elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then\r
NEXT_STATE <= E_ADDR; -- first address phase failed\r
NEXT_STATE <= SENDA;\r
dobyte_x <= '1';\r
end if;\r
- when E_ADDR => NEXT_STATE <= FAILED;\r
+ when E_ADDR => NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
- when E_RADDR => NEXT_STATE <= FAILED;\r
+ when E_RADDR => NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
- when LOADC => NEXT_STATE <= SENDC;\r
--- dobyte_x <= '1';\r
- when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ when LOADC => NEXT_STATE <= SENDC;\r
+-- dobyte_x <= '1';\r
+ when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
NEXT_STATE <= LOADD; -- I2C write, prepare data\r
load_d_x <= '1';\r
elsif( (bdone = '1') and (bok = '1') and (action_in = '1') ) then\r
else\r
NEXT_STATE <= SENDC;\r
dobyte_x <= '1';\r
- end if; \r
- when E_CMD => NEXT_STATE <= FAILED;\r
+ end if;\r
+ when E_CMD => NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
- when LOADD => NEXT_STATE <= SENDD;\r
- when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
- NEXT_STATE <= GSTOP; -- I2C write, data phase failed\r
+ when LOADD => NEXT_STATE <= SENDD;\r
+ when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C write, data phase failed\r
dostart_x <= '1';\r
elsif( (bdone = '1') and (action_in = '1') ) then\r
NEXT_STATE <= GSTOP; -- I2C read, data phase\r
- dostart_x <= '1'; \r
+ dostart_x <= '1';\r
elsif( (bdone = '1') and (bok = '0') and (action_in = '0') ) then\r
NEXT_STATE <= E_WD; -- I2C write, data phase failed\r
else\r
NEXT_STATE <= SENDD;\r
dobyte_x <= '1';\r
end if;\r
- when E_WD => NEXT_STATE <= FAILED;\r
+ when E_WD => NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
- when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then\r
+ when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then\r
NEXT_STATE <= DONE;\r
elsif( (sdone = '1') and (action_in = '1') and (phase = '1') ) then\r
NEXT_STATE <= DONE;\r
NEXT_STATE <= GSTOP;\r
dostart_x <= '1';\r
end if;\r
- when INC => NEXT_STATE <= LOADA;\r
+ when INC => NEXT_STATE <= LOADA;\r
load_a_x <= '1';\r
- when FAILED => if( sdone = '1' ) then\r
+ when FAILED => if( sdone = '1' ) then\r
NEXT_STATE <= DONE;\r
i2c_done_x <= '1';\r
running_x <= '0';\r
NEXT_STATE <= FAILED;\r
dostart_x <= '1';\r
end if;\r
- when DONE => if( i2c_go_in = '1' ) then\r
+ when DONE => if( i2c_go_in = '1' ) then\r
NEXT_STATE <= DONE;\r
i2c_done_x <= '1';\r
running_x <= '0';\r
NEXT_STATE <= SLEEP;\r
end if;\r
-- Just in case...\r
- when others => NEXT_STATE <= SLEEP; \r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
DECODE: process(CURRENT_STATE)\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm <= b"00000"; -- 00\r
- when CLRERR => bsm <= b"01100"; -- 0c\r
- when LOADA => bsm <= b"00001"; -- 01\r
- when GSTART => bsm <= b"00010"; -- 02\r
- when SENDA => bsm <= b"00011"; -- 03\r
- when LOADC => bsm <= b"00100"; -- 04\r
- when SENDC => bsm <= b"00101"; -- 05\r
- when LOADD => bsm <= b"00110"; -- 06\r
- when SENDD => bsm <= b"00111"; -- 07\r
- when GSTOP => bsm <= b"01000"; -- 08\r
- when INC => bsm <= b"01001"; -- 09\r
- when FAILED => bsm <= b"01010"; -- 0a\r
- when DONE => bsm <= b"01011"; -- 0b\r
- when E_START => bsm <= b"10000"; -- 10\r
- when E_RSTART => bsm <= b"10001"; -- 11\r
- when E_ADDR => bsm <= b"10010"; -- 12\r
- when E_RADDR => bsm <= b"10011"; -- 13\r
- when E_CMD => bsm <= b"10100"; -- 14\r
- when E_WD => bsm <= b"10101"; -- 15\r
- when others => bsm <= b"11111"; -- 1f\r
- end case; \r
+ when SLEEP => bsm <= b"00000"; -- 00\r
+ when CLRERR => bsm <= b"01100"; -- 0c\r
+ when LOADA => bsm <= b"00001"; -- 01\r
+ when GSTART => bsm <= b"00010"; -- 02\r
+ when SENDA => bsm <= b"00011"; -- 03\r
+ when LOADC => bsm <= b"00100"; -- 04\r
+ when SENDC => bsm <= b"00101"; -- 05\r
+ when LOADD => bsm <= b"00110"; -- 06\r
+ when SENDD => bsm <= b"00111"; -- 07\r
+ when GSTOP => bsm <= b"01000"; -- 08\r
+ when INC => bsm <= b"01001"; -- 09\r
+ when FAILED => bsm <= b"01010"; -- 0a\r
+ when DONE => bsm <= b"01011"; -- 0b\r
+ when E_START => bsm <= b"10000"; -- 10\r
+ when E_RSTART => bsm <= b"10001"; -- 11\r
+ when E_ADDR => bsm <= b"10010"; -- 12\r
+ when E_RADDR => bsm <= b"10011"; -- 13\r
+ when E_CMD => bsm <= b"10100"; -- 14\r
+ when E_WD => bsm <= b"10101"; -- 15\r
+ when others => bsm <= b"11111"; -- 1f\r
+ end case;\r
end process DECODE;\r
\r
-- We need to load different data sets\r
\r
-- The SendByte module\r
THE_I2C_SENDB: I2C_SENDB\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- DOBYTE_IN => dobyte,\r
- I2C_SPEED_IN => i2c_speed,\r
- I2C_BYTE_IN => i2c_byte,\r
- I2C_BACK_OUT => i2c_dr,\r
- SDA_IN => sda_in,\r
- R_SDA_OUT => r_sda_sb,\r
- S_SDA_OUT => s_sda_sb,\r
--- SCL_IN => scl_in,\r
- R_SCL_OUT => r_scl_sb,\r
- S_SCL_OUT => s_scl_sb,\r
- BDONE_OUT => bdone,\r
- BOK_OUT => bok,\r
- BSM_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ DOBYTE_IN => dobyte,\r
+ I2C_SPEED_IN => i2c_speed,\r
+ I2C_BYTE_IN => i2c_byte,\r
+ I2C_BACK_OUT => i2c_dr,\r
+ SDA_IN => sda_in,\r
+ R_SDA_OUT => r_sda_sb,\r
+ S_SDA_OUT => s_sda_sb,\r
+-- SCL_IN => scl_in,\r
+ R_SCL_OUT => r_scl_sb,\r
+ S_SCL_OUT => s_scl_sb,\r
+ BDONE_OUT => bdone,\r
+ BOK_OUT => bok,\r
+ BSM_OUT => open\r
+);\r
\r
-- The GenStart module\r
THE_I2C_GSTART: I2C_GSTART\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => start,\r
- DOSTART_IN => dostart,\r
- I2C_SPEED_IN => i2c_speed,\r
- SDONE_OUT => sdone,\r
- SOK_OUT => sok,\r
- SDA_IN => sda_in,\r
- SCL_IN => scl_in,\r
- R_SCL_OUT => r_scl_gs,\r
- S_SCL_OUT => s_scl_gs,\r
- R_SDA_OUT => r_sda_gs,\r
- S_SDA_OUT => s_sda_gs,\r
- BSM_OUT => gs_debug --open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => start,\r
+ DOSTART_IN => dostart,\r
+ I2C_SPEED_IN => i2c_speed,\r
+ SDONE_OUT => sdone,\r
+ SOK_OUT => sok,\r
+ SDA_IN => sda_in,\r
+ SCL_IN => scl_in,\r
+ R_SCL_OUT => r_scl_gs,\r
+ S_SCL_OUT => s_scl_gs,\r
+ R_SDA_OUT => r_sda_gs,\r
+ S_SDA_OUT => s_sda_gs,\r
+ BSM_OUT => gs_debug --open\r
+);\r
\r
r_scl <= r_scl_gs or r_scl_sb;\r
s_scl <= s_scl_gs or s_scl_sb;\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
- e_sf <= '0';\r
- e_anak <= '0';\r
- e_cnak <= '0';\r
- e_dnak <= '0';\r
- e_rsf <= '0';\r
- e_ranak <= '0';\r
+ e_sf <= '0';\r
+ e_anak <= '0';\r
+ e_cnak <= '0';\r
+ e_dnak <= '0';\r
+ e_rsf <= '0';\r
+ e_ranak <= '0';\r
elsif( CURRENT_STATE = CLRERR ) then\r
- e_sf <= '0';\r
- e_anak <= '0';\r
- e_cnak <= '0';\r
- e_dnak <= '0';\r
- e_rsf <= '0';\r
- e_ranak <= '0';\r
+ e_sf <= '0';\r
+ e_anak <= '0';\r
+ e_cnak <= '0';\r
+ e_dnak <= '0';\r
+ e_rsf <= '0';\r
+ e_ranak <= '0';\r
elsif( CURRENT_STATE = E_START ) then\r
- e_sf <= '1';\r
+ e_sf <= '1';\r
elsif( CURRENT_STATE = E_RSTART ) then\r
- e_rsf <= '1';\r
+ e_rsf <= '1';\r
elsif( CURRENT_STATE = E_ADDR ) then\r
- e_anak <= '1';\r
+ e_anak <= '1';\r
elsif( CURRENT_STATE = E_RADDR ) then\r
- e_ranak <= '1';\r
+ e_ranak <= '1';\r
elsif( CURRENT_STATE = E_CMD ) then\r
- e_cnak <= '1';\r
+ e_cnak <= '1';\r
elsif( CURRENT_STATE = E_WD ) then\r
- e_dnak <= '1';\r
+ e_dnak <= '1';\r
end if;\r
end if;\r
end process THE_ERR_REG_PROC;\r
status_out(1) <= e_anak;\r
status_out(0) <= e_sf;\r
\r
--- Outputs \r
-i2c_dr_out <= i2c_dr(8 downto 1);\r
+-- Outputs\r
+i2c_dr_out <= i2c_dr(8 downto 1);\r
i2c_busy_out <= running;\r
\r
-- Debug stuff\r
-- Missing: FIFO buffer handling, full / empty checks\r
\r
entity ipu_fifo_stage is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- RESET_IN : in std_logic; -- synchronous reset\r
- -- Slow control signals \r
- SECTOR_IN : in std_logic_vector(2 downto 0);\r
- MODULE_IN : in std_logic_vector(2 downto 0);\r
- -- IPU channel connections\r
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
- IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
- IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
- IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
- IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
- IPU_READ_IN : in std_logic; -- read strobe, low every second cycle \r
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
- LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
- -- DHDR buffer input\r
- DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
- DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
- DHDR_STORE_IN : in std_logic;\r
- DHDR_BUF_FULL_OUT : out std_logic;\r
- -- processed data input\r
- FIFO_START_IN : in std_logic;\r
- FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
- FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
- FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
- -- Debug signals\r
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals\r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0);\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of ipu_fifo_stage is\r
\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group";\r
-\r
- -- state machine definitions\r
- type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE); \r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- signals\r
- signal debug : std_logic_vector(63 downto 0);\r
- signal bsm_x : std_logic_vector(7 downto 0);\r
- signal next_trgnum_match : std_logic;\r
- signal trgnum_match : std_logic;\r
-\r
- signal dhdr_fifo_in : std_logic_vector(47 downto 0);\r
- signal dhdr_fifo_out : std_logic_vector(47 downto 0);\r
- signal dhdr_avail : std_logic;\r
- signal next_todo_list : std_logic_vector(15 downto 0);\r
- signal todo_list : std_logic_vector(15 downto 0);\r
- signal next_fifo_sel : std_logic_vector(4 downto 0);\r
- signal fifo_sel : std_logic_vector(4 downto 0);\r
- signal next_sel_fifo : std_logic_vector(15 downto 0);\r
- signal sel_fifo : std_logic_vector(15 downto 0);\r
-\r
- signal comb_rd_dfifo : std_logic_vector(15 downto 0);\r
- signal comb_st_data : std_logic_vector(15 downto 0);\r
- signal comb_ack_todo : std_logic;\r
-\r
- signal ipu_out_data : std_logic_vector(31 downto 0);\r
-\r
- -- state machine signals\r
- signal next_rd_lfifo : std_logic;\r
- signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit)\r
- signal next_dataready : std_logic;\r
- signal dataready : std_logic; -- data word is available\r
- signal next_set_hdr : std_logic;\r
- signal set_hdr : std_logic; -- store DHDR in output register\r
- signal next_set_data : std_logic;\r
- signal set_data : std_logic; -- store DATA from current DATA FIFO in output register\r
- signal next_ld_todo : std_logic;\r
- signal ld_todo : std_logic; -- load initial TODO list\r
- signal next_ack_todo : std_logic;\r
- signal ack_todo : std_logic; -- remove current entry from TODO list\r
- signal next_finished : std_logic;\r
- signal finished : std_logic; -- readout is finished\r
-\r
- -- generate needs arrays...\r
- type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0);\r
- signal fifo_in_data : fifo_data_t;\r
- signal fifo_out_data : fifo_data_t;\r
- type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
- signal fifo_in_count : fifo_count_t;\r
- type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0);\r
- signal fifo_todo : fifo_todo_t;\r
- type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
- signal fifo_ldata : fifo_ldata_t;\r
- type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
- signal fifo_wcnt : fifo_wcnt_t;\r
- signal fifo_data_free : fifo_wcnt_t;\r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group";\r
+\r
+-- state machine definitions\r
+type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- signals\r
+signal debug : std_logic_vector(63 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal next_trgnum_match : std_logic;\r
+signal trgnum_match : std_logic;\r
+\r
+signal dhdr_fifo_in : std_logic_vector(47 downto 0);\r
+signal dhdr_fifo_out : std_logic_vector(47 downto 0);\r
+signal dhdr_avail : std_logic;\r
+signal next_todo_list : std_logic_vector(15 downto 0);\r
+signal todo_list : std_logic_vector(15 downto 0);\r
+signal next_fifo_sel : std_logic_vector(4 downto 0);\r
+signal fifo_sel : std_logic_vector(4 downto 0);\r
+signal next_sel_fifo : std_logic_vector(15 downto 0);\r
+signal sel_fifo : std_logic_vector(15 downto 0);\r
+\r
+signal comb_rd_dfifo : std_logic_vector(15 downto 0);\r
+signal comb_st_data : std_logic_vector(15 downto 0);\r
+signal comb_ack_todo : std_logic;\r
+\r
+signal ipu_out_data : std_logic_vector(31 downto 0);\r
+\r
+-- state machine signals\r
+signal next_rd_lfifo : std_logic;\r
+signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit)\r
+signal next_dataready : std_logic;\r
+signal dataready : std_logic; -- data word is available\r
+signal next_set_hdr : std_logic;\r
+signal set_hdr : std_logic; -- store DHDR in output register\r
+signal next_set_data : std_logic;\r
+signal set_data : std_logic; -- store DATA from current DATA FIFO in output register\r
+signal next_ld_todo : std_logic;\r
+signal ld_todo : std_logic; -- load initial TODO list\r
+signal next_ack_todo : std_logic;\r
+signal ack_todo : std_logic; -- remove current entry from TODO list\r
+signal next_finished : std_logic;\r
+signal finished : std_logic; -- readout is finished\r
+signal next_preload : std_logic;\r
+signal preload : std_logic; -- read first data word from DATA FIFOs\r
+\r
+-- generate needs arrays...\r
+type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0);\r
+signal fifo_in_data : fifo_data_t;\r
+signal fifo_out_data : fifo_data_t;\r
+type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+signal fifo_in_count : fifo_count_t;\r
+type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0);\r
+signal fifo_todo : fifo_todo_t;\r
+type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+signal fifo_ldata : fifo_ldata_t;\r
+type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal fifo_wcnt : fifo_wcnt_t;\r
+signal fifo_data_free : fifo_wcnt_t;\r
+type fifo_lunused_t is array (0 to 15) of std_logic_vector(6 downto 0);\r
+signal fifo_lunused : fifo_lunused_t;\r
+\r
+signal dfifo_available : std_logic_vector(15 downto 0);\r
+\r
+signal lfifo_empty : std_logic_vector(15 downto 0);\r
+signal lfifo_full : std_logic_vector(15 downto 0);\r
+\r
+signal next_fifo_done : std_logic_vector(15 downto 0);\r
+signal fifo_done : std_logic_vector(15 downto 0);\r
+signal next_fifo_last : std_logic;\r
+signal fifo_last : std_logic;\r
+\r
+signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking!\r
+\r
+signal old_apv_num : std_logic_vector(3 downto 0);\r
+signal new_apv_num : std_logic_vector(3 downto 0);\r
+\r
+signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter\r
+\r
+signal next_dhdr_buf_full : std_logic;\r
+signal dhdr_buf_full : std_logic;\r
\r
- \r
- signal next_fifo_done : std_logic_vector(15 downto 0);\r
- signal fifo_done : std_logic_vector(15 downto 0);\r
- signal next_fifo_last : std_logic;\r
- signal fifo_last : std_logic;\r
- \r
- signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking!\r
- \r
- signal old_apv_num : std_logic_vector(3 downto 0);\r
- signal new_apv_num : std_logic_vector(3 downto 0);\r
-\r
- signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter\r
-\r
- signal dhdr_buf_full : std_logic;\r
- \r
begin\r
---------------------------------------------------------------------------\r
-- Statemachine\r
---------------------------------------------------------------------------\r
\r
-- state registers\r
-STATE_MEM: process( clk_in ) \r
+STATE_MEM: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
set_data <= '0';\r
ld_todo <= '0';\r
ack_todo <= '0';\r
+ preload <= '0';\r
finished <= '0';\r
else\r
CURRENT_STATE <= NEXT_STATE;\r
set_data <= next_set_data;\r
ld_todo <= next_ld_todo;\r
ack_todo <= next_ack_todo;\r
+ preload <= next_preload;\r
finished <= next_finished;\r
end if;\r
end if;\r
next_set_data <= '0';\r
next_ld_todo <= '0';\r
next_ack_todo <= '0';\r
+ next_preload <= '0';\r
next_finished <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then\r
+ when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then\r
NEXT_STATE <= RDLF;\r
next_rd_lfifo <= '1';\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RDLF => NEXT_STATE <= GETFD;\r
+ when RDLF => NEXT_STATE <= GETFD;\r
next_set_hdr <= '1';\r
next_ld_todo <= '1';\r
- when GETFD => NEXT_STATE <= DELH;\r
- when DELH => NEXT_STATE <= WHDR;\r
+ when GETFD => NEXT_STATE <= DELH;\r
+ next_preload <= '1';\r
+ when DELH => NEXT_STATE <= WHDR;\r
next_dataready <= '1';\r
- when WHDR => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then\r
+ when WHDR => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then\r
NEXT_STATE <= GETD; -- there are datawords to send\r
next_set_data <= '1';\r
next_ack_todo <= '1';\r
NEXT_STATE <= WHDR;\r
next_dataready <= '1';\r
end if;\r
- when GETD => if( fifo_last = '1' ) then\r
+ when GETD => if( fifo_last = '1' ) then\r
NEXT_STATE <= DEL0;\r
- else \r
+ else\r
NEXT_STATE <= WAITD;\r
next_dataready <= '1';\r
end if;\r
- when WAITD => if( ipu_read_in = '1' ) then\r
+ when WAITD => if( ipu_read_in = '1' ) then\r
NEXT_STATE <= GETD;\r
next_set_data <= '1';\r
else\r
NEXT_STATE <= WAITD;\r
next_dataready <= '1';\r
end if;\r
- when DEL0 => NEXT_STATE <= WAITDL;\r
+ when DEL0 => NEXT_STATE <= WAITDL;\r
next_dataready <= '1';\r
- when WAITDL => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then\r
+ when WAITDL => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then\r
NEXT_STATE <= GETD;\r
next_set_data <= '1';\r
next_ack_todo <= '1';\r
NEXT_STATE <= WAITDL;\r
next_dataready <= '1';\r
end if;\r
- when DONE => if( ipu_start_readout_in = '0' ) then\r
+ when DONE => if( ipu_start_readout_in = '0' ) then\r
NEXT_STATE <= SLEEP;\r
else\r
NEXT_STATE <= DONE;\r
end if;\r
\r
- when others => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process STATE_TRANSFORM;\r
\r
ipu_length_out <= dhdr_fifo_out(47 downto 32);\r
\r
-- IPU error pattern: [24] => trigger tag mismatch\r
-ipu_error_pattern_out(31 downto 25) <= (others => '0');\r
-ipu_error_pattern_out(24) <= not trgnum_match;\r
-ipu_error_pattern_out(23 downto 0) <= (others => '0');\r
+ipu_error_pattern_out(31 downto 24) <= (others => '0');\r
+ipu_error_pattern_out(23) <= '0'; -- "single broken event"\r
+ipu_error_pattern_out(23) <= '0'; -- "severe problem"\r
+ipu_error_pattern_out(21) <= '0'; -- "partially not found"\r
+ipu_error_pattern_out(20) <= not trgnum_match; -- "not found"\r
+ipu_error_pattern_out(19 downto 0) <= (others => '0');\r
\r
-- state decoding (ONLY FOR DEBUGGING!)\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_x <= x"00";\r
- when RDLF => bsm_x <= x"01";\r
- when GETFD => bsm_x <= x"02";\r
- when DELH => bsm_x <= x"03";\r
- when WHDR => bsm_x <= x"04";\r
- when GETD => bsm_x <= x"05";\r
- when WAITD => bsm_x <= x"06";\r
- when WAITDL => bsm_x <= x"07";\r
- when DEL0 => bsm_x <= x"08";\r
- when DONE => bsm_x <= x"09";\r
- when others => bsm_x <= x"ff";\r
+ when SLEEP => bsm_x <= x"00";\r
+ when RDLF => bsm_x <= x"01";\r
+ when GETFD => bsm_x <= x"02";\r
+ when DELH => bsm_x <= x"03";\r
+ when WHDR => bsm_x <= x"04";\r
+ when GETD => bsm_x <= x"05";\r
+ when WAITD => bsm_x <= x"06";\r
+ when WAITDL => bsm_x <= x"07";\r
+ when DEL0 => bsm_x <= x"08";\r
+ when DONE => bsm_x <= x"09";\r
+ when others => bsm_x <= x"ff";\r
end case;\r
end process STATE_DECODE;\r
\r
---------------------------------------------------------------------------\r
-- Aliasing the data streams\r
---------------------------------------------------------------------------\r
-fifo_in_data(0) <= fifo_0_data_in(26 downto 0); fifo_in_count(0) <= fifo_0_data_in(37 downto 27);\r
-fifo_in_data(1) <= fifo_1_data_in(26 downto 0); fifo_in_count(1) <= fifo_1_data_in(37 downto 27);\r
-fifo_in_data(2) <= fifo_2_data_in(26 downto 0); fifo_in_count(2) <= fifo_2_data_in(37 downto 27);\r
-fifo_in_data(3) <= fifo_3_data_in(26 downto 0); fifo_in_count(3) <= fifo_3_data_in(37 downto 27);\r
-fifo_in_data(4) <= fifo_4_data_in(26 downto 0); fifo_in_count(4) <= fifo_4_data_in(37 downto 27);\r
-fifo_in_data(5) <= fifo_5_data_in(26 downto 0); fifo_in_count(5) <= fifo_5_data_in(37 downto 27);\r
-fifo_in_data(6) <= fifo_6_data_in(26 downto 0); fifo_in_count(6) <= fifo_6_data_in(37 downto 27);\r
-fifo_in_data(7) <= fifo_7_data_in(26 downto 0); fifo_in_count(7) <= fifo_7_data_in(37 downto 27);\r
-fifo_in_data(8) <= fifo_8_data_in(26 downto 0); fifo_in_count(8) <= fifo_8_data_in(37 downto 27);\r
-fifo_in_data(9) <= fifo_9_data_in(26 downto 0); fifo_in_count(9) <= fifo_9_data_in(37 downto 27);\r
-fifo_in_data(10) <= fifo_10_data_in(26 downto 0); fifo_in_count(10) <= fifo_10_data_in(37 downto 27);\r
-fifo_in_data(11) <= fifo_11_data_in(26 downto 0); fifo_in_count(11) <= fifo_11_data_in(37 downto 27);\r
-fifo_in_data(12) <= fifo_12_data_in(26 downto 0); fifo_in_count(12) <= fifo_12_data_in(37 downto 27);\r
-fifo_in_data(13) <= fifo_13_data_in(26 downto 0); fifo_in_count(13) <= fifo_13_data_in(37 downto 27);\r
-fifo_in_data(14) <= fifo_14_data_in(26 downto 0); fifo_in_count(14) <= fifo_14_data_in(37 downto 27);\r
-fifo_in_data(15) <= fifo_15_data_in(26 downto 0); fifo_in_count(15) <= fifo_15_data_in(37 downto 27);\r
+fifo_in_data(0) <= fifo_0_data_in(26 downto 0); fifo_in_count(0) <= fifo_0_data_in(37 downto 27);\r
+fifo_in_data(1) <= fifo_1_data_in(26 downto 0); fifo_in_count(1) <= fifo_1_data_in(37 downto 27);\r
+fifo_in_data(2) <= fifo_2_data_in(26 downto 0); fifo_in_count(2) <= fifo_2_data_in(37 downto 27);\r
+fifo_in_data(3) <= fifo_3_data_in(26 downto 0); fifo_in_count(3) <= fifo_3_data_in(37 downto 27);\r
+fifo_in_data(4) <= fifo_4_data_in(26 downto 0); fifo_in_count(4) <= fifo_4_data_in(37 downto 27);\r
+fifo_in_data(5) <= fifo_5_data_in(26 downto 0); fifo_in_count(5) <= fifo_5_data_in(37 downto 27);\r
+fifo_in_data(6) <= fifo_6_data_in(26 downto 0); fifo_in_count(6) <= fifo_6_data_in(37 downto 27);\r
+fifo_in_data(7) <= fifo_7_data_in(26 downto 0); fifo_in_count(7) <= fifo_7_data_in(37 downto 27);\r
+fifo_in_data(8) <= fifo_8_data_in(26 downto 0); fifo_in_count(8) <= fifo_8_data_in(37 downto 27);\r
+fifo_in_data(9) <= fifo_9_data_in(26 downto 0); fifo_in_count(9) <= fifo_9_data_in(37 downto 27);\r
+fifo_in_data(10) <= fifo_10_data_in(26 downto 0); fifo_in_count(10) <= fifo_10_data_in(37 downto 27);\r
+fifo_in_data(11) <= fifo_11_data_in(26 downto 0); fifo_in_count(11) <= fifo_11_data_in(37 downto 27);\r
+fifo_in_data(12) <= fifo_12_data_in(26 downto 0); fifo_in_count(12) <= fifo_12_data_in(37 downto 27);\r
+fifo_in_data(13) <= fifo_13_data_in(26 downto 0); fifo_in_count(13) <= fifo_13_data_in(37 downto 27);\r
+fifo_in_data(14) <= fifo_14_data_in(26 downto 0); fifo_in_count(14) <= fifo_14_data_in(37 downto 27);\r
+fifo_in_data(15) <= fifo_15_data_in(26 downto 0); fifo_in_count(15) <= fifo_15_data_in(37 downto 27);\r
\r
---------------------------------------------------------------------------\r
-- DATA and LENGTH FIFO for the APV data streams\r
---------------------------------------------------------------------------\r
\r
+-- We also store the DHDR inside the LFIFOs. They are big enough and have unused bits like hell.\r
+dhdr_fifo_in <= dhdr_length_in & dhdr_data_in;\r
+\r
GEN_FIFO: for i in 0 to 15 generate\r
THE_DFIFO: fifo_2kx27\r
- port map( DATA => fifo_in_data(i),\r
- CLOCK => clk_in, \r
- WREN => fifo_we_in(i), \r
- RDEN => comb_rd_dfifo(i), -- BUG\r
- RESET => reset_in, \r
- Q => fifo_out_data(i), -- BUG\r
- WCNT => fifo_wcnt(i), -- BUG\r
- EMPTY => open, -- BUG\r
- FULL => open -- BUG\r
- );\r
+ port map(\r
+ DATA => fifo_in_data(i),\r
+ CLOCK => clk_in,\r
+ WREN => fifo_we_in(i),\r
+ RDEN => comb_rd_dfifo(i), -- BUG\r
+ RESET => reset_in,\r
+ Q => fifo_out_data(i), -- BUG\r
+ WCNT => fifo_wcnt(i), -- BUG\r
+ EMPTY => open, -- BUG\r
+ FULL => open -- BUG\r
+ );\r
\r
-- Combinatorial read pulse for FIFOs\r
- comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and ipu_read_in and dataready) or (ld_todo and fifo_ldata(i)(10)); \r
+ comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and ipu_read_in and dataready) or (preload and fifo_ldata(i)(10));\r
\r
-- Combinatorial store pulse for data (last data word need to be transfered also!)\r
comb_st_data(i) <= (sel_fifo(i) and ipu_read_in and dataready);\r
- -- BUGBUGBUG: one clock cycle too late when changing FIFOs....\r
\r
-- getting the number of free entries in the data fifo by subtracting [size] - [used entries]\r
THE_SUBTRACTOR: suber_12bit\r
- port map( DATAA => x"800",\r
- DATAB => fifo_wcnt(i),\r
- CLOCK => clk_in,\r
- RESET => reset_in,\r
- CLOCKEN => '1',\r
- RESULT => fifo_data_free(i)\r
- );\r
-\r
+ port map(\r
+ DATAA => x"800",\r
+ DATAB => fifo_wcnt(i),\r
+ CLOCK => clk_in,\r
+ RESET => reset_in,\r
+ CLOCKEN => '1',\r
+ RESULT => fifo_data_free(i)\r
+ );\r
+\r
+ -- check if next event will still fit into data FIFO\r
+ THE_COMPARATOR: comp_12bit\r
+ port map(\r
+ DATAA => fifo_data_free(i),\r
+ DATAB => fifo_space_req_in,\r
+ CLOCK => clk_in,\r
+ CLOCKEN => '1',\r
+ ACLR => '0',\r
+ AGTB => dfifo_available(i)\r
+ );\r
+ \r
-- length fifo - stores the number of words to fetch from dfifo\r
- THE_LFIFO: fifo_16x11\r
- port map( DATA => fifo_in_count(i), \r
- CLOCK => clk_in,\r
- WREN => fifo_done_in, \r
- RDEN => rd_lfifo,\r
- RESET => reset_in, \r
- Q => fifo_ldata(i), \r
- WCNT => open, -- BUG\r
- EMPTY => open, -- BUG\r
- FULL => open -- BUG\r
- );\r
+ THE_LFIFO: fifo_1kx18\r
+ port map(\r
+ DATA(17 downto 15) => dhdr_fifo_in(i*3 + 2 downto i*3),\r
+ DATA(14 downto 11) => b"0000", -- free for other stuff!\r
+ DATA(10 downto 0) => fifo_in_count(i),\r
+ CLOCK => clk_in,\r
+ WREN => fifo_done_in,\r
+ RDEN => rd_lfifo,\r
+ RESET => reset_in,\r
+ Q(17 downto 11) => fifo_lunused(i), -- will be portions of DHDR\r
+ Q(10 downto 0) => fifo_ldata(i),\r
+ WCNT => open, -- BUG\r
+ EMPTY => lfifo_empty(i), -- open -- BUG\r
+ FULL => lfifo_full(i) --open -- BUG\r
+ );\r
next_todo_list(i) <= fifo_ldata(i)(10);\r
\r
+ -- reassamble the DHDR information \r
+ dhdr_fifo_out(i*3 + 2 downto i*3) <= fifo_lunused(i)(6 downto 4);\r
+ \r
+ -- TODO counter for all FIFOs\r
THE_TODO_CTR_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
\r
comb_ack_todo <= fifo_last and set_data;\r
\r
-\r
----------------------------------------------------------------------------\r
--- DHDR buffer - delivers all information\r
----------------------------------------------------------------------------\r
-dhdr_fifo_in <= dhdr_length_in & dhdr_data_in;\r
-\r
-THE_DHDR_BUF: dhdr_buf\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in, \r
- DHDR_DATA_IN => dhdr_fifo_in,\r
- DHDR_WE_IN => dhdr_store_in,\r
- DHDR_DONE_IN => finished,\r
- DHDR_DATA_OUT => dhdr_fifo_out,\r
- DHDR_AVAILABLE_OUT => dhdr_avail,\r
- BUF_FULL_OUT => dhdr_buf_full,\r
- BUF_LEVEL_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+next_dhdr_buf_full <= '1' when (lfifo_full(0) = '1') or\r
+ (dfifo_available /= b"1111_1111_1111_1111")\r
+ else '0';\r
+dhdr_avail <= not lfifo_empty(0); -- FAKE\r
\r
-- compare incoming trigger number with stored DHDR information\r
next_trgnum_match <= '1' when ( ipu_number_in = dhdr_fifo_out(15 downto 0) ) else '0';\r
---------------------------------------------------------------------------\r
-- priority encoding is used to select the next buffer for readout\r
---------------------------------------------------------------------------\r
---THE_PRI_ENCODER_PROC: process( todo_list, fifo_sel, fifo_done )\r
THE_PRI_ENCODER_PROC: process( todo_list, fifo_done )\r
begin\r
if ( todo_list(15 downto 15) = "1" ) then\r
THE_SYNC_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
- fifo_sel <= next_fifo_sel;\r
- sel_fifo <= next_sel_fifo;\r
- fifo_done <= next_fifo_done;\r
- fifo_last <= next_fifo_last;\r
+ fifo_sel <= next_fifo_sel;\r
+ sel_fifo <= next_sel_fifo;\r
+ fifo_done <= next_fifo_done;\r
+ fifo_last <= next_fifo_last;\r
+ dhdr_buf_full <= next_dhdr_buf_full;\r
end if;\r
end process THE_SYNC_PROC;\r
\r
\r
---------------------------------------------------------------------------\r
--- backplane wise APV mapping \r
+-- backplane wise APV mapping\r
---------------------------------------------------------------------------\r
-old_apv_num <= fifo_sel(3 downto 0); \r
+old_apv_num <= fifo_sel(3 downto 0);\r
\r
THE_ADC_APV_MAP_MEM: adc_apv_map_mem\r
-port map( ADDRESS(6 downto 4) => module_in(2 downto 0),\r
- ADDRESS(3 downto 0) => old_apv_num, \r
- Q => new_apv_num\r
+port map( ADDRESS(6 downto 4) => module_in(2 downto 0),\r
+ ADDRESS(3 downto 0) => old_apv_num,\r
+ Q => new_apv_num\r
);\r
\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
-- debug information\r
---------------------------------------------------------------------------\r
-debug(63 downto 28) <= (others => '0');\r
-debug(27 downto 16) <= fifo_data_free(13);\r
-debug(15 downto 12) <= (others => '0');\r
-debug(11 downto 0) <= fifo_wcnt(13);\r
-\r
+debug(63 downto 48) <= todo_list;\r
+debug(47 downto 25) <= (others => '0');\r
+debug(24 downto 20) <= fifo_sel;\r
+debug(19 downto 17) <= (others => '0');\r
+debug(16) <= fifo_last;\r
+debug(15 downto 0) <= fifo_done;\r
\r
---------------------------------------------------------------------------\r
-- Output signals\r
end behavioral;\r
\r
\r
- \r
+\r
\r
\r
use work.adcmv3_components.all;\r
\r
entity logic_analyzer is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- control signals\r
- ARM_IN : in std_logic; -- arm the machine\r
- TRG_IN : in std_logic; -- trigger the data acquisition\r
- MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); \r
- -- status signals\r
- SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
- SM_CE_OUT : out std_logic;\r
- SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
- CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
- RUN_OUT : out std_logic; -- ready for trigger\r
- SAMPLE_OUT : out std_logic; -- data acquisition running\r
- READY_OUT : out std_logic; -- data acquisition is finished\r
- LAST_OUT : out std_logic; -- last data word of sampling\r
- -- Status lines\r
- BSM_OUT : out std_logic_vector(3 downto 0);\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- control signals\r
+ ARM_IN : in std_logic; -- arm the machine\r
+ TRG_IN : in std_logic; -- trigger the data acquisition\r
+ MAX_SAMPLE_IN : in std_logic_vector(9 downto 0);\r
+ -- status signals\r
+ SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
+ SM_CE_OUT : out std_logic;\r
+ SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
+ CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
+ RUN_OUT : out std_logic; -- ready for trigger\r
+ SAMPLE_OUT : out std_logic; -- data acquisition running\r
+ READY_OUT : out std_logic; -- data acquisition is finished\r
+ LAST_OUT : out std_logic; -- last data word of sampling\r
+ -- Status lines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of logic_analyzer is\r
\r
-- Signals\r
+type STATES is (SM_SLEEP,SM_CLEAR,SM_RUN,SM_SAMPLE,SM_READY);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- type STATES is (SM_SLEEP,SM_CLEAR,SM_RUN,SM_SAMPLE,SM_READY);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+signal sm_addr : std_logic_vector(9 downto 0);\r
+signal sm_counter : std_logic_vector(9 downto 0);\r
\r
- signal sm_addr : std_logic_vector(9 downto 0);\r
- signal sm_counter : std_logic_vector(9 downto 0);\r
+signal sm_we_x : std_logic;\r
+signal sm_we : std_logic;\r
+signal sm_ce_x : std_logic;\r
+signal sm_ce : std_logic;\r
+signal sm_rst_x : std_logic;\r
+signal sm_rst : std_logic;\r
+signal sm_acq_x : std_logic;\r
+signal sm_acq : std_logic;\r
+signal sm_done_x : std_logic;\r
+signal sm_done : std_logic;\r
\r
- signal sm_we_x : std_logic;\r
- signal sm_we : std_logic;\r
- signal sm_ce_x : std_logic;\r
- signal sm_ce : std_logic;\r
- signal sm_rst_x : std_logic;\r
- signal sm_rst : std_logic;\r
- signal sm_acq_x : std_logic;\r
- signal sm_acq : std_logic;\r
- signal sm_done_x : std_logic;\r
- signal sm_done : std_logic;\r
+signal sm_clear_done_x : std_logic;\r
+signal sm_clear_done : std_logic;\r
+signal sm_sample_done_x : std_logic;\r
+signal sm_sample_done : std_logic;\r
\r
- signal sm_clear_done_x : std_logic;\r
- signal sm_clear_done : std_logic;\r
- signal sm_sample_done_x : std_logic;\r
- signal sm_sample_done : std_logic;\r
+signal data_available : std_logic;\r
\r
- signal data_available : std_logic;\r
-\r
--- signal debug : std_logic_vector(31 downto 0);\r
+-- signal debug : std_logic_vector(31 downto 0);\r
\r
begin\r
\r
sm_acq_x <= '0';\r
sm_done_x <= '0';\r
case CURRENT_STATE is\r
- when SM_SLEEP => if( arm_in = '1' ) then\r
+ when SM_SLEEP => if( arm_in = '1' ) then\r
NEXT_STATE <= SM_CLEAR;\r
sm_rst_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SM_SLEEP;\r
end if;\r
- when SM_CLEAR => if( sm_clear_done = '1' ) then\r
+ when SM_CLEAR => if( sm_clear_done = '1' ) then\r
NEXT_STATE <= SM_RUN;\r
sm_ce_x <= '1';\r
sm_we_x <= '1';\r
sm_ce_x <= '1';\r
sm_we_x <= '1';\r
end if;\r
- when SM_RUN => if( trg_in = '1' ) then\r
+ when SM_RUN => if( trg_in = '1' ) then\r
NEXT_STATE <= SM_SAMPLE;\r
sm_ce_x <= '1';\r
sm_we_x <= '1';\r
sm_ce_x <= '1';\r
sm_we_x <= '1';\r
end if;\r
- when SM_SAMPLE => if( sm_sample_done = '1' ) then\r
+ when SM_SAMPLE => if( sm_sample_done = '1' ) then\r
NEXT_STATE <= SM_READY;\r
sm_done_x <= '1';\r
else\r
sm_we_x <= '1';\r
sm_acq_x <= '1';\r
end if;\r
- when SM_READY => NEXT_STATE <= SM_SLEEP;\r
+ when SM_READY => NEXT_STATE <= SM_SLEEP;\r
\r
- when others => NEXT_STATE <= SM_SLEEP;\r
+ when others => NEXT_STATE <= SM_SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SM_SLEEP => bsm_out <= x"0";\r
+ when SM_SLEEP => bsm_out <= x"0";\r
clear_out <= '0';\r
run_out <= '0';\r
- when SM_CLEAR => bsm_out <= x"1";\r
+ when SM_CLEAR => bsm_out <= x"1";\r
clear_out <= '1';\r
run_out <= '0';\r
- when SM_RUN => bsm_out <= x"2";\r
+ when SM_RUN => bsm_out <= x"2";\r
clear_out <= '0';\r
run_out <= '1';\r
- when SM_SAMPLE => bsm_out <= x"3";\r
+ when SM_SAMPLE => bsm_out <= x"3";\r
clear_out <= '0';\r
run_out <= '0';\r
- when SM_READY => bsm_out <= x"4";\r
+ when SM_READY => bsm_out <= x"4";\r
clear_out <= '0';\r
run_out <= '0';\r
- when others => bsm_out <= x"f";\r
+ when others => bsm_out <= x"f";\r
clear_out <= '0';\r
run_out <= '0';\r
end case;\r
-library ieee; \r
-use ieee.std_logic_1164.all; \r
-use ieee.std_logic_arith.all; \r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
entity max_data is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- TODO_3_IN : in std_logic_vector(3 downto 0);\r
- TODO_2_IN : in std_logic_vector(3 downto 0);\r
- TODO_1_IN : in std_logic_vector(3 downto 0);\r
- TODO_0_IN : in std_logic_vector(3 downto 0);\r
- TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ TODO_3_IN : in std_logic_vector(3 downto 0);\r
+ TODO_2_IN : in std_logic_vector(3 downto 0);\r
+ TODO_1_IN : in std_logic_vector(3 downto 0);\r
+ TODO_0_IN : in std_logic_vector(3 downto 0);\r
+ TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of max_data is\r
\r
- -- Placer Directives\r
-\r
- -- normal signals \r
- -- first comparatopr step\r
- signal max_32_data : std_logic_vector(3 downto 0);\r
- signal max_21_data : std_logic_vector(3 downto 0);\r
- signal max_10_data : std_logic_vector(3 downto 0);\r
- signal comb_3_gt_2 : std_logic;\r
- signal comb_2_gt_1 : std_logic;\r
- signal comb_1_gt_0 : std_logic;\r
- -- second comparator step\r
- signal max_321_data : std_logic_vector(3 downto 0);\r
- signal max_210_data : std_logic_vector(3 downto 0);\r
- signal comb_32_gt_21 : std_logic;\r
- signal comb_21_gt_10 : std_logic;\r
- -- third comparator step\r
- signal max_final_data : std_logic_vector(3 downto 0);\r
- signal comb_final : std_logic;\r
-\r
- signal debug : std_logic_vector(15 downto 0);\r
-\r
-begin \r
+-- Placer Directives\r
+\r
+-- normal signals\r
+-- first comparatopr step\r
+signal max_32_data : std_logic_vector(3 downto 0);\r
+signal max_21_data : std_logic_vector(3 downto 0);\r
+signal max_10_data : std_logic_vector(3 downto 0);\r
+signal comb_3_gt_2 : std_logic;\r
+signal comb_2_gt_1 : std_logic;\r
+signal comb_1_gt_0 : std_logic;\r
+-- second comparator step\r
+signal max_321_data : std_logic_vector(3 downto 0);\r
+signal max_210_data : std_logic_vector(3 downto 0);\r
+signal comb_32_gt_21 : std_logic;\r
+signal comb_21_gt_10 : std_logic;\r
+-- third comparator step\r
+signal max_final_data : std_logic_vector(3 downto 0);\r
+signal comb_final : std_logic;\r
+\r
+signal debug : std_logic_vector(15 downto 0);\r
+\r
+begin\r
\r
-- FIRST COMPARATOR STEP\r
-- compare MAX_3 against MAX_2, store the bigger one\r
THE_COMP_3_2: comp4bit\r
-port map( DATAA => todo_3_in,\r
- DATAB => todo_2_in,\r
- AGTB => comb_3_gt_2\r
- );\r
+port map(\r
+ DATAA => todo_3_in,\r
+ DATAB => todo_2_in,\r
+ AGTB => comb_3_gt_2\r
+);\r
\r
THE_3_2_STORE_PROC: process( clk_in )\r
begin\r
\r
-- compare MAX_2 against MAX_1, store the bigger one\r
THE_COMP_2_1: comp4bit\r
-port map( DATAA => todo_2_in,\r
- DATAB => todo_1_in,\r
- AGTB => comb_2_gt_1\r
- );\r
+port map(\r
+ DATAA => todo_2_in,\r
+ DATAB => todo_1_in,\r
+ AGTB => comb_2_gt_1\r
+);\r
\r
THE_2_1_STORE_PROC: process( clk_in )\r
begin\r
\r
-- compare MAX_1 against MAX_0, store the bigger one\r
THE_COMP_1_0: comp4bit\r
-port map( DATAA => todo_1_in,\r
- DATAB => todo_0_in,\r
- AGTB => comb_1_gt_0\r
- );\r
+port map(\r
+ DATAA => todo_1_in,\r
+ DATAB => todo_0_in,\r
+ AGTB => comb_1_gt_0\r
+);\r
\r
THE_1_0_STORE_PROC: process( clk_in )\r
begin\r
-- SECOND COMPARATOR STEP\r
-- compare MAX_32 against MAX_21, store the bigger one\r
THE_COMP_32_21: comp4bit\r
-port map( DATAA => max_32_data,\r
- DATAB => max_21_data,\r
- AGTB => comb_32_gt_21\r
- );\r
+port map(\r
+ DATAA => max_32_data,\r
+ DATAB => max_21_data,\r
+ AGTB => comb_32_gt_21\r
+);\r
\r
THE_32_21_STORE_PROC: process( clk_in )\r
begin\r
\r
-- compare MAX_21 against MAX_10, store the bigger one\r
THE_COMP_21_10: comp4bit\r
-port map( DATAA => max_21_data,\r
- DATAB => max_10_data,\r
- AGTB => comb_21_gt_10\r
- );\r
+port map(\r
+ DATAA => max_21_data,\r
+ DATAB => max_10_data,\r
+ AGTB => comb_21_gt_10\r
+);\r
\r
THE_21_10_STORE_PROC: process( clk_in )\r
begin\r
\r
-- FINAL COMPARATOR STEP\r
THE_COMP_FINAL: comp4bit\r
-port map( DATAA => max_321_data,\r
- DATAB => max_210_data,\r
- AGTB => comb_final\r
- );\r
+port map(\r
+ DATAA => max_321_data,\r
+ DATAB => max_210_data,\r
+ AGTB => comb_final\r
+);\r
\r
THE_FINAL_STORE_PROC: process( clk_in )\r
begin\r
\r
-- output signals\r
todo_max_out <= max_final_data;\r
-debug_out <= debug; \r
- \r
-end behavioral; \r
-
\ No newline at end of file
+debug_out <= debug;\r
+\r
+end behavioral;\r
+
\ No newline at end of file
-SCUBA, Version ispLever_v72_PROD_Build (44)\r
-Fri Nov 20 19:14:28 2009\r
+SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
+Fri Apr 16 11:05:24 2010\r
\r
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
Copyright (c) 1995 AT&T Corp. All rights reserved.\r
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
\r
BEGIN SCUBA Module Synthesis\r
\r
- Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e \r
- Circuit name : dpram_8x19\r
- Module type : sdpram\r
- Module Version : 3.4\r
- Address width : 4\r
- Data width : 19\r
+ Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -fill -e \r
+ Circuit name : fifo_1kx18\r
+ Module type : fifoblk\r
+ Module Version : 4.8\r
Ports : \r
- Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]\r
- Outputs : Q[18:0]\r
+ Inputs : Data[17:0], Clock, WrEn, RdEn, Reset\r
+ Outputs : Q[17:0], WCNT[10:0], Empty, Full\r
I/O buffer : not inserted\r
- Clock edge : rising edge\r
EDIF output : suppressed\r
- VHDL output : dpram_8x19.vhd\r
- VHDL template : dpram_8x19_tmpl.vhd\r
- VHDL testbench : tb_dpram_8x19_tmpl.vhd\r
+ VHDL output : fifo_1kx18.vhd\r
+ VHDL template : fifo_1kx18_tmpl.vhd\r
+ VHDL testbench : tb_fifo_1kx18_tmpl.vhd\r
VHDL purpose : for synthesis and simulation\r
Bus notation : big endian\r
- Report output : dpram_8x19.srp\r
+ Report output : fifo_1kx18.srp\r
Estimated Resource Usage:\r
- LUT : 1\r
- DRAM : 5\r
+ LUT : 80\r
+ EBR : 1\r
+ Reg : 35\r
\r
END SCUBA Module Synthesis\r
\r
-- stolen from Jan Michel, was trb_net_onewire.vhd
entity onewire_master is
- generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds
- port( CLK : in std_logic;
- RESET : in std_logic;
- READOUT_ENABLE_IN : in std_logic;
- -- connection to 1-wire interface (16 APV FEs)
- ONEWIRE : inout std_logic_vector(15 downto 0);
- BP_ONEWIRE : inout std_logic;
- -- connection to external DPRAM for slow control readout
- BP_DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(6 downto 0);
- WRITE_OUT : out std_logic;
- BUSY_OUT : out std_logic;
- -- debug
- BSM_OUT : out std_logic_vector(7 downto 0);
- STAT : out std_logic_vector(15 downto 0)
- );
+generic(
+ CLK_PERIOD : integer := 10 -- clock perion in nanoseconds
+);
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ READOUT_ENABLE_IN : in std_logic;
+ -- connection to 1-wire interface (16 APV FEs)
+ ONEWIRE : inout std_logic_vector(15 downto 0);
+ BP_ONEWIRE : inout std_logic;
+ -- connection to external DPRAM for slow control readout
+ BP_DATA_OUT : out std_logic_vector(15 downto 0);
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(6 downto 0);
+ WRITE_OUT : out std_logic;
+ BUSY_OUT : out std_logic;
+ -- debug
+ BSM_OUT : out std_logic_vector(7 downto 0);
+ STAT : out std_logic_vector(15 downto 0)
+);
end entity;
architecture onewire_master_arch of onewire_master is
- constant MAX_COUNTER : integer := 2**28-1;
- type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT,
- WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
- READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, CHECK_PULSE);
- signal STATE : state_t;
- signal NEXT_STATE : state_t;
- signal bsm : std_logic_vector(7 downto 0);
- signal timecounter : integer range 0 to MAX_COUNTER;
- signal bitcounter : integer range 0 to 127;
- signal bitcounter_vector : std_logic_vector(6 downto 0);
- signal inc_bitcounter : std_logic;
- signal reset_bitcounter : std_logic;
- signal reset_timecounter : std_logic;
- signal send_bit : std_logic;
- signal next_send_bit : std_logic;
- signal recv_bit_ready : std_logic;
- signal next_recv_bit_ready : std_logic;
- signal ext_ram_addr : std_logic_vector(3 downto 0);
- signal ram_addr : std_logic_vector(2 downto 0);
- signal ram_wr : std_logic;
-
- -- state machine auxiliary signals
- signal wait_pulse : std_logic;
- signal next_wait_pulse : std_logic;
- signal strong_pullup : std_logic;
- signal next_strong_pullup : std_logic;
- signal presence_reset : std_logic;
- signal next_presence_reset : std_logic;
- signal send_rom : std_logic; -- read UniqueID
- signal next_send_rom : std_logic;
- signal conv_temp : std_logic; -- send CONV_TEMP
- signal next_conv_temp : std_logic;
- signal reading_temp : std_logic; -- readback of temperature
- signal next_reading_temp : std_logic;
- signal skip_rom : std_logic; -- send SKIP_ROM
- signal next_skip_rom : std_logic;
- signal output_tmp : std_logic; -- 1W output signal
- signal next_output_tmp : std_logic;
- signal output : std_logic;
- signal next_output : std_logic;
-
- -- presence pulse detection
- signal neg_edge : std_logic_vector(16 downto 0); -- presence pulse edge detection
- signal presence_found : std_logic_vector(16 downto 0); -- set signal for presence bits
- signal presence : std_logic_vector(16 downto 0); -- presence bits
-
- type input_t is array (0 to 16) of std_logic_vector(7 downto 0);
- signal input : input_t;
-
- type word_t is array (0 to 16) of std_logic_vector(15 downto 0);
- signal word : word_t;
-
- signal recv_bit : std_logic_vector(16 downto 0);
- signal next_recv_bit : std_logic_vector(16 downto 0);
-
- signal comb_ext_addr_go : std_logic;
-
- -- output signals, delayed by one cycle
- signal mux_data : std_logic_vector(15 downto 0);
- signal mux_addr : std_logic_vector(6 downto 0);
- signal mux_wr : std_logic;
-
- signal onewire_tmp : std_logic_vector(16 downto 0);
-
- signal comb_busy : std_logic;
- signal busy : std_logic;
-
+constant MAX_COUNTER : integer := 2**28-1;
+type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT,
+ WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
+ READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, CHECK_PULSE);
+signal STATE : state_t;
+signal NEXT_STATE : state_t;
+signal bsm : std_logic_vector(7 downto 0);
+signal timecounter : integer range 0 to MAX_COUNTER;
+signal bitcounter : integer range 0 to 127;
+signal bitcounter_vector : std_logic_vector(6 downto 0);
+signal inc_bitcounter : std_logic;
+signal reset_bitcounter : std_logic;
+signal reset_timecounter : std_logic;
+signal send_bit : std_logic;
+signal next_send_bit : std_logic;
+signal recv_bit_ready : std_logic;
+signal next_recv_bit_ready : std_logic;
+signal ext_ram_addr : std_logic_vector(3 downto 0);
+signal ram_addr : std_logic_vector(2 downto 0);
+signal ram_wr : std_logic;
+
+-- state machine auxiliary signals
+signal wait_pulse : std_logic;
+signal next_wait_pulse : std_logic;
+signal strong_pullup : std_logic;
+signal next_strong_pullup : std_logic;
+signal presence_reset : std_logic;
+signal next_presence_reset : std_logic;
+signal send_rom : std_logic; -- read UniqueID
+signal next_send_rom : std_logic;
+signal conv_temp : std_logic; -- send CONV_TEMP
+signal next_conv_temp : std_logic;
+signal reading_temp : std_logic; -- readback of temperature
+signal next_reading_temp : std_logic;
+signal skip_rom : std_logic; -- send SKIP_ROM
+signal next_skip_rom : std_logic;
+signal output_tmp : std_logic; -- 1W output signal
+signal next_output_tmp : std_logic;
+signal output : std_logic;
+signal next_output : std_logic;
+
+-- presence pulse detection
+signal neg_edge : std_logic_vector(16 downto 0); -- presence pulse edge detection
+signal presence_found : std_logic_vector(16 downto 0); -- set signal for presence bits
+signal presence : std_logic_vector(16 downto 0); -- presence bits
+
+type input_t is array (0 to 16) of std_logic_vector(7 downto 0);
+signal input : input_t;
+
+type word_t is array (0 to 16) of std_logic_vector(15 downto 0);
+signal word : word_t;
+
+signal recv_bit : std_logic_vector(16 downto 0);
+signal next_recv_bit : std_logic_vector(16 downto 0);
+
+signal comb_ext_addr_go : std_logic;
+
+-- output signals, delayed by one cycle
+signal mux_data : std_logic_vector(15 downto 0);
+signal mux_addr : std_logic_vector(6 downto 0);
+signal mux_wr : std_logic;
+
+signal onewire_tmp : std_logic_vector(16 downto 0);
+
+signal comb_busy : std_logic;
+signal busy : std_logic;
+
begin
-- bidirectional connection
comb_busy <= '0' when (STATE = START) else '1';
-- State machine transitions
-THE_STATE_MACHINE: process( STATE, timecounter, bitcounter_vector, input, send_bit, output_tmp,
+THE_STATE_MACHINE: process( STATE, timecounter, bitcounter_vector, input, send_bit, output_tmp,
skip_rom, recv_bit, conv_temp, reading_temp, send_rom, readout_enable_in )
begin
NEXT_STATE <= STATE;
next_presence_reset <= '0';
case STATE is
- --
+ --
when START =>
if( readout_enable_in = '1' ) then
NEXT_STATE <= IDLE;
reset_timecounter <= '1';
end if;
- -- idle state for the DS1822
+ -- idle state for the DS1822
when IDLE =>
if( is_time_reached(timecounter,640000,CLK_PERIOD) = '1' ) then
NEXT_STATE <= SEND_RESET;
when WAIT_AFTER_RESET =>
if( is_time_reached(timecounter,10000,CLK_PERIOD) = '1' ) then
reset_timecounter <= '1';
- NEXT_STATE <= CHECK_PULSE;
+ NEXT_STATE <= CHECK_PULSE;
end if;
-- check if the is a pulse
NEXT_STATE <= WRITE_START;
if( send_rom = '1' ) then
- next_send_bit <= not bitcounter_vector(1); -- this is x33 (READ_ROM_COMMAND), lsb first
+ next_send_bit <= not bitcounter_vector(1); -- this is x33 (READ_ROM_COMMAND), lsb first
else
- next_send_bit <= bitcounter_vector(1); -- this is xCC (SKIP_ROM_COMMAND), lsb first
+ next_send_bit <= bitcounter_vector(1); -- this is xCC (SKIP_ROM_COMMAND), lsb first
end if;
if( bitcounter_vector(3) = '1' ) then --send 8 bit
--sending sensor commands
when SEND_CONV_TEMP =>
next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0);
- --this is x44, lsb first
+ --this is x44, lsb first
inc_bitcounter <= '1';
if( bitcounter_vector(3) = '1' ) then --send 8 bit
NEXT_STATE <= READ_CONV_TEMP;
end if;
inc_bitcounter <= '1';
-
+
if( bitcounter_vector(3) = '1' ) then --send 8 bit
NEXT_STATE <= READ_READ_TEMP;
reset_bitcounter <= '1';
when READ_CONV_TEMP => --waiting for end of conversion
next_strong_pullup <= '1';
if( is_time_reached(timecounter,1300000000,CLK_PERIOD) = '1' ) then -- reality is 1.3s delay
--- if( is_time_reached(timecounter,3000000,CLK_PERIOD) = '1' ) then -- simulation is 3ms delay
+-- if( is_time_reached(timecounter,3000000,CLK_PERIOD) = '1' ) then -- simulation is 3ms delay
NEXT_STATE <= IDLE;
reset_timecounter <= '1';
next_conv_temp <= '0';
next_output_tmp <= '0';
reset_timecounter <= '1';
end if;
-
+
when WRITE_WAIT =>
if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then
reset_timecounter <= '1';
next_recv_bit_ready <= '1';
NEXT_STATE <= READ_WAIT;
end if;
-
+
when READ_WAIT =>
if( is_time_reached(timecounter,80000,CLK_PERIOD) = '1' ) then
reset_timecounter <= '1';
STATE_DECODE: process( STATE )
begin
case STATE is
- when START => bsm <= x"00";
- when IDLE => bsm <= x"01";
- when SEND_RESET => bsm <= x"02";
- when WAIT_AFTER_RESET => bsm <= x"03";
- when CHECK_PULSE => bsm <= x"0e";
- when SEND_ROM_COMMAND => bsm <= x"04";
- when READ_WAIT => bsm <= x"05";
- when WRITE_START => bsm <= x"06";
- when WRITE_WAIT => bsm <= x"07";
- when READ_BIT => bsm <= x"08";
- when READ_READ_ROM => bsm <= x"09";
- when SEND_CONV_TEMP => bsm <= x"0a";
- when READ_CONV_TEMP => bsm <= x"0b";
- when SEND_READ_TEMP => bsm <= x"0c";
- when READ_READ_TEMP => bsm <= x"0d";
- when others => bsm <= x"ff";
+ when START => bsm <= x"00";
+ when IDLE => bsm <= x"01";
+ when SEND_RESET => bsm <= x"02";
+ when WAIT_AFTER_RESET => bsm <= x"03";
+ when CHECK_PULSE => bsm <= x"0e";
+ when SEND_ROM_COMMAND => bsm <= x"04";
+ when READ_WAIT => bsm <= x"05";
+ when WRITE_START => bsm <= x"06";
+ when WRITE_WAIT => bsm <= x"07";
+ when READ_BIT => bsm <= x"08";
+ when READ_READ_ROM => bsm <= x"09";
+ when SEND_CONV_TEMP => bsm <= x"0a";
+ when READ_CONV_TEMP => bsm <= x"0b";
+ when SEND_READ_TEMP => bsm <= x"0c";
+ when READ_READ_TEMP => bsm <= x"0d";
+ when others => bsm <= x"ff";
end case;
end process STATE_DECODE;
--------------------------------------------------------------------------------------
if( reset = '1' ) then
ram_addr(1 downto 0) <= (others => '0');
ram_wr <= '0';
--- word(i) <= (others => '0');
+-- word(i) <= (others => '0');
else
ram_wr <= '0';
-- Shift process for serial / parallel data conversion
ram_addr <= "100";
ram_wr <= '1';
for i in 0 to 16 loop
- word(i)(11) <= recv_bit(i);
+ word(i)(11) <= recv_bit(i);
word(i)(10 downto 0) <= word(i)(15 downto 5);
word(i)(14 downto 12) <= (others => '0');
word(i)(15) <= presence(i);
end loop;
-
+
end if;
end if;
end if;
ext_ram_addr <= (others => '0');
elsif( (comb_ext_addr_go = '1') ) then
ext_ram_addr <= ext_ram_addr + 1;
- end if;
+ end if;
end if;
end process THE_EXT_ADDR_PROC;
begin
if( rising_edge(clk) ) then
case ext_ram_addr is
- when x"0" => mux_data <= word(0);
- when x"1" => mux_data <= word(1);
- when x"2" => mux_data <= word(2);
- when x"3" => mux_data <= word(3);
- when x"4" => mux_data <= word(4);
- when x"5" => mux_data <= word(5);
- when x"6" => mux_data <= word(6);
- when x"7" => mux_data <= word(7);
- when x"8" => mux_data <= word(8);
- when x"9" => mux_data <= word(9);
- when x"a" => mux_data <= word(10);
- when x"b" => mux_data <= word(11);
- when x"c" => mux_data <= word(12);
- when x"d" => mux_data <= word(13);
- when x"e" => mux_data <= word(14);
- when x"f" => mux_data <= word(15);
- when others => mux_data <= x"dead";
+ when x"0" => mux_data <= word(0);
+ when x"1" => mux_data <= word(1);
+ when x"2" => mux_data <= word(2);
+ when x"3" => mux_data <= word(3);
+ when x"4" => mux_data <= word(4);
+ when x"5" => mux_data <= word(5);
+ when x"6" => mux_data <= word(6);
+ when x"7" => mux_data <= word(7);
+ when x"8" => mux_data <= word(8);
+ when x"9" => mux_data <= word(9);
+ when x"a" => mux_data <= word(10);
+ when x"b" => mux_data <= word(11);
+ when x"c" => mux_data <= word(12);
+ when x"d" => mux_data <= word(13);
+ when x"e" => mux_data <= word(14);
+ when x"f" => mux_data <= word(15);
+ when others => mux_data <= x"dead";
end case;
mux_addr(2 downto 0) <= ram_addr;
mux_addr(6 downto 3) <= ext_ram_addr;
-- max_space = (num_frames * 128 + num_frames) = num_frames * 129\r
\r
entity ped_corr_ctrl is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- RESET_IN : in std_logic; -- synchronous reset\r
- -- Slow control registers\r
- -- EDS buffer -- back to previous source stage\r
- EDS_DATA_IN : in std_logic_vector(39 downto 0); \r
- EDS_AVAIL_IN : in std_logic;\r
- EDS_DONE_OUT : out std_logic;\r
- EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
- -- DHDR information -- to next stage\r
- DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
- DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
- DHDR_STORE_OUT : out std_logic;\r
- DHDR_BUF_FULL_IN : in std_logic;\r
- -- data buffers -- from raw_buf_stage\r
- BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
- BUF_DONE_OUT : out std_logic;\r
- BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
- BUF_START_IN : in std_logic_vector(15 downto 0);\r
- -- raw data\r
- BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
- BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
- -- Pedestal data \r
- PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
- PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
- PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
- -- Threshold data\r
- THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
- THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
- THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
- -- processed data\r
- FIFO_START_OUT : out std_logic;\r
- FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
- FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
- FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
- -- Debug signals\r
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control registers\r
+ -- EDS buffer -- back to previous source stage\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : in std_logic;\r
+ EDS_DONE_OUT : out std_logic;\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ DHDR_STORE_OUT : out std_logic;\r
+ DHDR_BUF_FULL_IN : in std_logic;\r
+ FIFO_SPACE_REQ_OUT : out std_logic_vector(11 downto 0);\r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : out std_logic;\r
+ BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
+ BUF_START_IN : in std_logic_vector(15 downto 0);\r
+ -- raw data\r
+ BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
+ -- Pedestal data\r
+ PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- Threshold data\r
+ THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- processed data\r
+ FIFO_START_OUT : out std_logic;\r
+ FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of ped_corr_ctrl is\r
\r
- -- state machine definitions\r
- type STATES is (SLEEP,LOADFC,DELFC,CHECK,FULL,DEL0,NBERR,EMPTY,CHKFC,FCERR,CHKRW,RWERR,CHKAE,AEERR,\r
- FINIT,FLOAD,FZERO,FREAD,FDONE,FDEL,FDEC,WREDS,ACKEDS,WHDR,EHDR,CCNT,CDEL0,CDEL1,DEL1,DEL2); \r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- signals\r
- signal debug : std_logic_vector(15 downto 0);\r
- signal bsm_x : std_logic_vector(7 downto 0);\r
-\r
- -- status signals from TOCs\r
- signal buf_gooddata : std_logic_vector(15 downto 0);\r
- signal buf_baddata : std_logic_vector(15 downto 0);\r
- signal buf_nodata : std_logic_vector(15 downto 0);\r
- signal buf_ready : std_logic_vector(15 downto 0);\r
-\r
- -- local frame counter\r
- signal to_do_ctr : std_logic_vector(3 downto 0);\r
- signal done_ctr : std_logic_vector(3 downto 0);\r
- signal loc_frm_ctr : std_logic_vector(3 downto 0);\r
- signal next_ld_frm_ctr : std_logic;\r
- signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value \r
- signal next_ce_frm_ctr : std_logic;\r
- signal ce_frm_ctr : std_logic; -- increment frame counter\r
- signal next_last_frame : std_logic;\r
- signal last_frame : std_logic; -- all frame buffers have been copied\r
- signal next_cleaned_up : std_logic;\r
- signal cleaned_up : std_logic; -- only relevant in case of errors\r
- signal next_multi_frame : std_logic;\r
- signal multi_frame : std_logic; -- more than one frame requested\r
- signal next_do_hdr : std_logic;\r
- signal do_hdr : std_logic; -- insert debug header (in case of common errors, in case of multiframe)\r
- signal next_do_error : std_logic;\r
- signal do_error : std_logic; -- insert debug header (in case of broken buffer only) \r
- signal next_do_start : std_logic; \r
- signal do_start : std_logic; -- start signal for one event processing\r
- \r
- -- buffer status signals, error signals from checkers\r
- signal buffers_ready : std_logic; -- all buffers are ready for data transport\r
- signal buffers_valid : std_logic; -- at least one buffer has valid data\r
- signal frame_row_error : std_logic; \r
- signal frame_apv_error : std_logic;\r
- signal frame_ctr_error : std_logic;\r
- \r
- signal frame_busy : std_logic; -- from ALU\r
- \r
- -- Buffer read address counter, control signals\r
- signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address\r
- signal buf_half : std_logic;\r
- signal next_buf_addr_ce : std_logic;\r
- signal buf_addr_ce : std_logic;\r
- signal next_buf_addr_rst : std_logic;\r
- signal buf_addr_rst : std_logic;\r
- signal next_buf_addr_init : std_logic; -- needed for THR\r
- signal buf_addr_init : std_logic;\r
- signal next_buf_addr_done : std_logic;\r
- signal buf_addr_done : std_logic;\r
- signal next_buf_done : std_logic;\r
- signal buf_done : std_logic;\r
- signal next_frame_valid : std_logic;\r
- signal frame_valid : std_logic;\r
- signal buf_frame_valid : std_logic;\r
- signal raw_addr : std_logic_vector(6 downto 0);\r
- signal buf_raw_addr : std_logic_vector(6 downto 0);\r
-\r
- signal thr_addr : std_logic_vector(6 downto 0); -- threshold read address\r
- signal thr_addr_ce : std_logic;\r
- signal thr_addr_rst : std_logic;\r
- signal dly_thr_addr_ce : std_logic_vector(7 downto 0);\r
- signal dly_thr_addr_rst : std_logic_vector(7 downto 0);\r
-\r
--- signal ped_addr : std_logic_vector(6 downto 0); -- pedestal read address\r
-\r
- -- statemachine signals\r
- signal next_wait_frames : std_logic;\r
- signal wait_frames : std_logic; -- we are in the waiting phase for incoming frames\r
- signal next_eds_wr : std_logic;\r
- signal eds_wr : std_logic; -- copy current EDS into new buffer\r
- signal next_eds_done : std_logic;\r
- signal eds_done : std_logic; -- acknowledge and release old EDS\r
-\r
- -- generate needs arrays...\r
- type raw_data_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
- signal raw_data : raw_data_t;\r
- type fifo_data_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
- signal fifo_data : fifo_data_t;\r
- type sc_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
- signal ped_data : sc_data_t;\r
- signal thr_data : sc_data_t;\r
-\r
- signal fifo_we : std_logic_vector(15 downto 0);\r
-\r
- signal errors : std_logic_vector(3 downto 0);\r
-\r
- -- for summing up\r
- signal next_small_0_sum : std_logic_vector(4 downto 0);\r
- signal small_0_sum : std_logic_vector(4 downto 0);\r
- signal next_small_1_sum : std_logic_vector(4 downto 0);\r
- signal small_1_sum : std_logic_vector(4 downto 0);\r
- signal small_sum : std_logic_vector(15 downto 0);\r
- signal total_sum : std_logic_vector(15 downto 0);\r
- signal reset_sum : std_logic;\r
+-- state machine definitions\r
+type STATES is (SLEEP,LOADFC,DELFC,CHECK,FULL,DEL0,NBERR,EMPTY,CHKFC,FCERR,CHKRW,RWERR,CHKAE,AEERR,\r
+ FINIT,FLOAD,FZERO,FREAD,FDONE,FDEL,FDEC,WREDS,ACKEDS,WHDR,EHDR,CCNT,CDEL0,CDEL1,DEL1,DEL2);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- signals\r
+signal debug : std_logic_vector(15 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+\r
+-- status signals from TOCs\r
+signal buf_gooddata : std_logic_vector(15 downto 0);\r
+signal buf_baddata : std_logic_vector(15 downto 0);\r
+signal buf_nodata : std_logic_vector(15 downto 0);\r
+signal buf_ready : std_logic_vector(15 downto 0);\r
+\r
+-- local frame counter\r
+signal to_do_ctr : std_logic_vector(3 downto 0);\r
+signal done_ctr : std_logic_vector(3 downto 0);\r
+signal loc_frm_ctr : std_logic_vector(3 downto 0);\r
+signal next_ld_frm_ctr : std_logic;\r
+signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value\r
+signal next_ce_frm_ctr : std_logic;\r
+signal ce_frm_ctr : std_logic; -- increment frame counter\r
+signal next_last_frame : std_logic;\r
+signal last_frame : std_logic; -- all frame buffers have been copied\r
+signal next_cleaned_up : std_logic;\r
+signal cleaned_up : std_logic; -- only relevant in case of errors\r
+signal next_multi_frame : std_logic;\r
+signal multi_frame : std_logic; -- more than one frame requested\r
+signal next_do_hdr : std_logic;\r
+signal do_hdr : std_logic; -- insert debug header (in case of common errors, in case of multiframe)\r
+signal next_do_error : std_logic;\r
+signal do_error : std_logic; -- insert debug header (in case of broken buffer only)\r
+signal next_do_start : std_logic;\r
+signal do_start : std_logic; -- start signal for one event processing\r
+\r
+-- buffer status signals, error signals from checkers\r
+signal buffers_ready : std_logic; -- all buffers are ready for data transport\r
+signal buffers_valid : std_logic; -- at least one buffer has valid data\r
+signal frame_row_error : std_logic;\r
+signal frame_apv_error : std_logic;\r
+signal frame_ctr_error : std_logic;\r
+\r
+signal frame_busy : std_logic; -- from ALU\r
+\r
+-- Buffer read address counter, control signals\r
+signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address\r
+signal buf_half : std_logic;\r
+signal next_buf_addr_ce : std_logic;\r
+signal buf_addr_ce : std_logic;\r
+signal next_buf_addr_rst : std_logic;\r
+signal buf_addr_rst : std_logic;\r
+signal next_buf_addr_init : std_logic; -- needed for THR\r
+signal buf_addr_init : std_logic;\r
+signal next_buf_addr_done : std_logic;\r
+signal buf_addr_done : std_logic;\r
+signal next_buf_done : std_logic;\r
+signal buf_done : std_logic;\r
+signal next_frame_valid : std_logic;\r
+signal frame_valid : std_logic;\r
+signal buf_frame_valid : std_logic;\r
+signal raw_addr : std_logic_vector(6 downto 0);\r
+signal buf_raw_addr : std_logic_vector(6 downto 0);\r
+\r
+-- statemachine signals\r
+signal next_wait_frames : std_logic;\r
+signal wait_frames : std_logic; -- we are in the waiting phase for incoming frames\r
+signal next_eds_wr : std_logic;\r
+signal eds_wr : std_logic; -- copy current EDS into new buffer\r
+signal next_eds_done : std_logic;\r
+signal eds_done : std_logic; -- acknowledge and release old EDS\r
+\r
+-- generate needs arrays...\r
+type raw_data_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
+signal raw_data : raw_data_t;\r
+type fifo_data_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
+signal fifo_data : fifo_data_t;\r
+type sc_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal ped_data : sc_data_t;\r
+signal thr_data : sc_data_t;\r
+\r
+signal fifo_we : std_logic_vector(15 downto 0);\r
+\r
+signal errors : std_logic_vector(3 downto 0);\r
+\r
+-- for summing up\r
+signal next_small_0_sum : std_logic_vector(4 downto 0);\r
+signal small_0_sum : std_logic_vector(4 downto 0);\r
+signal next_small_1_sum : std_logic_vector(4 downto 0);\r
+signal small_1_sum : std_logic_vector(4 downto 0);\r
+signal small_sum : std_logic_vector(15 downto 0);\r
+signal total_sum : std_logic_vector(15 downto 0);\r
+signal reset_sum : std_logic;\r
+\r
+signal next_max_num_words : std_logic_vector(11 downto 0);\r
+signal max_num_words : std_logic_vector(11 downto 0);\r
+\r
+signal thr_addr_q : std_logic_vector(6 downto 0);\r
+signal thr_addr_qq : std_logic_vector(6 downto 0);\r
+signal thr_addr_qqq : std_logic_vector(6 downto 0);\r
\r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- "Calculate" the number of words needed in IPU buffer stage\r
+---------------------------------------------------------------------------\r
+\r
+-- we need three informations: \r
+-- - number of APV data frames => EDS_DATA[35:32]\r
+-- - maximum number of surviving channels (64 or 128) => EDS_DATA[2:0]\r
+-- - number of debug words per APV frame => by design\r
+next_max_num_words(11) <= '0';\r
\r
+THE_DECIDER_PROC: process( eds_data_in(35 downto 32), eds_data_in(2 downto 0) )\r
begin\r
+ case eds_data_in(2 downto 0) is\r
+ when b"000" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - RAW128\r
+ when b"001" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - PED128\r
+ when b"010" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - PED128THR\r
+ when b"011" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - RAW64\r
+ when b"100" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - NC64PED64\r
+ when b"101" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64\r
+ when b"110" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64GOOD\r
+ when b"111" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64THR\r
+ when others => next_max_num_words(10 downto 6) <= (others => '0');\r
+ end case;\r
+end process THE_DECIDER_PROC;\r
+\r
+next_max_num_words(5) <= '0';\r
+next_max_num_words(4 downto 1) <= eds_data_in(35 downto 32);\r
+next_max_num_words(0) <= '0';\r
\r
---------------------------------------------------------------------------\r
-- Aliasing the data streams\r
-- framecounter check, must be done once per frame\r
---------------------------------------------------------------------------\r
THE_FRMCTR_CHECK: frmctr_check\r
-port map( CLK_IN => clk_in,\r
- GOODDATA_IN => buf_gooddata,\r
- FRAMECOUNTER_IN => loc_frm_ctr,\r
- FRM_NR_0_IN => raw_data(0)(17 downto 14),\r
- FRM_NR_1_IN => raw_data(1)(17 downto 14),\r
- FRM_NR_2_IN => raw_data(2)(17 downto 14),\r
- FRM_NR_3_IN => raw_data(3)(17 downto 14),\r
- FRM_NR_4_IN => raw_data(4)(17 downto 14),\r
- FRM_NR_5_IN => raw_data(5)(17 downto 14),\r
- FRM_NR_6_IN => raw_data(6)(17 downto 14),\r
- FRM_NR_7_IN => raw_data(7)(17 downto 14),\r
- FRM_NR_8_IN => raw_data(8)(17 downto 14),\r
- FRM_NR_9_IN => raw_data(9)(17 downto 14),\r
- FRM_NR_10_IN => raw_data(10)(17 downto 14),\r
- FRM_NR_11_IN => raw_data(11)(17 downto 14),\r
- FRM_NR_12_IN => raw_data(12)(17 downto 14),\r
- FRM_NR_13_IN => raw_data(13)(17 downto 14),\r
- FRM_NR_14_IN => raw_data(14)(17 downto 14),\r
- FRM_NR_15_IN => raw_data(15)(17 downto 14),\r
- FRC_ERROR_OUT => frame_ctr_error, -- BUG\r
- DBG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ GOODDATA_IN => buf_gooddata,\r
+ FRAMECOUNTER_IN => loc_frm_ctr,\r
+ FRM_NR_0_IN => raw_data(0)(17 downto 14),\r
+ FRM_NR_1_IN => raw_data(1)(17 downto 14),\r
+ FRM_NR_2_IN => raw_data(2)(17 downto 14),\r
+ FRM_NR_3_IN => raw_data(3)(17 downto 14),\r
+ FRM_NR_4_IN => raw_data(4)(17 downto 14),\r
+ FRM_NR_5_IN => raw_data(5)(17 downto 14),\r
+ FRM_NR_6_IN => raw_data(6)(17 downto 14),\r
+ FRM_NR_7_IN => raw_data(7)(17 downto 14),\r
+ FRM_NR_8_IN => raw_data(8)(17 downto 14),\r
+ FRM_NR_9_IN => raw_data(9)(17 downto 14),\r
+ FRM_NR_10_IN => raw_data(10)(17 downto 14),\r
+ FRM_NR_11_IN => raw_data(11)(17 downto 14),\r
+ FRM_NR_12_IN => raw_data(12)(17 downto 14),\r
+ FRM_NR_13_IN => raw_data(13)(17 downto 14),\r
+ FRM_NR_14_IN => raw_data(14)(17 downto 14),\r
+ FRM_NR_15_IN => raw_data(15)(17 downto 14),\r
+ FRC_ERROR_OUT => frame_ctr_error, -- BUG\r
+ DBG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- framewise ROW and ERROR checker\r
---------------------------------------------------------------------------\r
THE_REF_ROW_SEL: ref_row_sel\r
-port map( CLK_IN => clk_in,\r
- READY_IN => buf_ready,\r
- GOODDATA_IN => buf_gooddata,\r
- FRAME_0_IN => raw_data(0)(29 downto 18),\r
- FRAME_1_IN => raw_data(1)(29 downto 18),\r
- FRAME_2_IN => raw_data(2)(29 downto 18),\r
- FRAME_3_IN => raw_data(3)(29 downto 18),\r
- FRAME_4_IN => raw_data(4)(29 downto 18),\r
- FRAME_5_IN => raw_data(5)(29 downto 18),\r
- FRAME_6_IN => raw_data(6)(29 downto 18),\r
- FRAME_7_IN => raw_data(7)(29 downto 18),\r
- FRAME_8_IN => raw_data(8)(29 downto 18),\r
- FRAME_9_IN => raw_data(9)(29 downto 18),\r
- FRAME_10_IN => raw_data(10)(29 downto 18),\r
- FRAME_11_IN => raw_data(11)(29 downto 18),\r
- FRAME_12_IN => raw_data(12)(29 downto 18),\r
- FRAME_13_IN => raw_data(13)(29 downto 18),\r
- FRAME_14_IN => raw_data(14)(29 downto 18),\r
- FRAME_15_IN => raw_data(15)(29 downto 18),\r
- VALID_BUFS_OUT => buffers_valid,\r
- READY_OUT => buffers_ready,\r
- ROW_ERROR_OUT => frame_row_error,\r
- APV_ERROR_OUT => frame_apv_error,\r
- APV_ERROR_BITS_OUT => open, -- BUGBUGBUG\r
- REF_ROW_OUT => open, -- selected reference row\r
- DBG_OUT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ READY_IN => buf_ready,\r
+ GOODDATA_IN => buf_gooddata,\r
+ FRAME_0_IN => raw_data(0)(29 downto 18),\r
+ FRAME_1_IN => raw_data(1)(29 downto 18),\r
+ FRAME_2_IN => raw_data(2)(29 downto 18),\r
+ FRAME_3_IN => raw_data(3)(29 downto 18),\r
+ FRAME_4_IN => raw_data(4)(29 downto 18),\r
+ FRAME_5_IN => raw_data(5)(29 downto 18),\r
+ FRAME_6_IN => raw_data(6)(29 downto 18),\r
+ FRAME_7_IN => raw_data(7)(29 downto 18),\r
+ FRAME_8_IN => raw_data(8)(29 downto 18),\r
+ FRAME_9_IN => raw_data(9)(29 downto 18),\r
+ FRAME_10_IN => raw_data(10)(29 downto 18),\r
+ FRAME_11_IN => raw_data(11)(29 downto 18),\r
+ FRAME_12_IN => raw_data(12)(29 downto 18),\r
+ FRAME_13_IN => raw_data(13)(29 downto 18),\r
+ FRAME_14_IN => raw_data(14)(29 downto 18),\r
+ FRAME_15_IN => raw_data(15)(29 downto 18),\r
+ VALID_BUFS_OUT => buffers_valid,\r
+ READY_OUT => buffers_ready,\r
+ ROW_ERROR_OUT => frame_row_error,\r
+ APV_ERROR_OUT => frame_apv_error,\r
+ APV_ERROR_BITS_OUT => open, -- BUGBUGBUG\r
+ REF_ROW_OUT => open, -- selected reference row\r
+ DBG_OUT => open\r
+);\r
\r
---------------------------------------------------------------------------\r
-- Statemachine\r
---------------------------------------------------------------------------\r
\r
-- state registers\r
-STATE_MEM: process( clk_in ) \r
+STATE_MEM: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
errors(0) <= frame_apv_error;\r
\r
-- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy, \r
- buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error, \r
+STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy,\r
+ buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error,\r
buf_addr_done, buf_half )\r
begin\r
NEXT_STATE <= SLEEP; -- avoid latches\r
next_do_error <= '0';\r
next_do_start <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then\r
+ -- BUG: we need to delay this by some clock cycles to be sure that enough space is available in IPU stage.\r
+ -- calculation of max_num_words takes some time.\r
+ when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then\r
NEXT_STATE <= LOADFC;\r
next_ld_frm_ctr <= '1';\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when LOADFC => NEXT_STATE <= DELFC;\r
+ when LOADFC => NEXT_STATE <= DELFC;\r
next_do_start <= '1';\r
- when DELFC => NEXT_STATE <= CHECK;\r
- when CHECK => if( last_frame = '0' ) then\r
+ when DELFC => NEXT_STATE <= CHECK;\r
+ when CHECK => if( last_frame = '0' ) then\r
NEXT_STATE <= FULL;\r
next_wait_frames <= '1';\r
else\r
NEXT_STATE <= EMPTY;\r
end if;\r
- when EMPTY => NEXT_STATE <= WREDS;\r
+ when EMPTY => NEXT_STATE <= WREDS;\r
next_eds_wr <= '1';\r
- when FULL => if( buffers_ready = '1' ) then\r
+ when FULL => if( buffers_ready = '1' ) then\r
NEXT_STATE <= DEL0;\r
next_do_error <= '1'; -- here broken channels deliver a "I DON'T FEEL GOOD" word...\r
else\r
NEXT_STATE <= FULL;\r
next_wait_frames <= '1';\r
end if;\r
- when DEL0 => if ( buffers_valid = '1' ) then\r
+ when DEL0 => if ( buffers_valid = '1' ) then\r
NEXT_STATE <= CHKFC;\r
else\r
NEXT_STATE <= NBERR;\r
end if;\r
- when CHKFC => if( frame_ctr_error = '0' ) then\r
+ when CHKFC => if( frame_ctr_error = '0' ) then\r
NEXT_STATE <= CHKRW;\r
else\r
NEXT_STATE <= FCERR;\r
end if;\r
- when CHKRW => if( frame_row_error = '0' ) then\r
+ when CHKRW => if( frame_row_error = '0' ) then\r
NEXT_STATE <= CHKAE;\r
else\r
NEXT_STATE <= RWERR;\r
end if;\r
- when CHKAE => if ( (frame_apv_error = '0') and (multi_frame = '1') ) then\r
+ when CHKAE => if ( (frame_apv_error = '0') and (multi_frame = '1') ) then\r
NEXT_STATE <= WHDR;\r
next_do_hdr <= '1';\r
elsif( (frame_apv_error = '0') and (multi_frame = '0') ) then\r
else\r
NEXT_STATE <= AEERR;\r
end if;\r
- when WHDR => NEXT_STATE <= FINIT;\r
+ when WHDR => NEXT_STATE <= FINIT;\r
next_buf_addr_rst <= '1';\r
- when FINIT => NEXT_STATE <= FLOAD; -- load address x"01";\r
+ when FINIT => NEXT_STATE <= FLOAD; -- load address x"01";\r
next_buf_addr_ce <= '1';\r
- when FLOAD => NEXT_STATE <= FZERO; -- load address x"00";\r
+ when FLOAD => NEXT_STATE <= FZERO; -- load address x"00";\r
next_buf_addr_rst <= '1';\r
next_buf_addr_init <= not buf_half;\r
- when FZERO => NEXT_STATE <= FREAD;\r
+ when FZERO => NEXT_STATE <= FREAD;\r
next_buf_addr_ce <= '1';\r
- when FREAD => if ( (buf_addr_done = '1') and (buf_half = '1') ) then\r
+ when FREAD => if ( (buf_addr_done = '1') and (buf_half = '1') ) then\r
NEXT_STATE <= FDONE;\r
next_ce_frm_ctr <= '1';\r
next_buf_done <= '1';\r
next_buf_addr_ce <= '1';\r
next_frame_valid <= '1';\r
end if;\r
- when FDONE => if( frame_busy = '1' ) then\r
+ when FDONE => if( frame_busy = '1' ) then\r
NEXT_STATE <= FDONE;\r
else\r
NEXT_STATE <= FDEL;\r
end if;\r
- when FDEL => NEXT_STATE <= FDEC;\r
- when FDEC => if( last_frame = '1' ) then\r
+ when FDEL => NEXT_STATE <= FDEC;\r
+ when FDEC => if( last_frame = '1' ) then\r
NEXT_STATE <= WREDS; -- copy current EDS to new buffer\r
next_eds_wr <= '1';\r
else\r
NEXT_STATE <= DEL0; -- only for multiframe readout, will not work (needs headers!!!)\r
end if;\r
- when WREDS => NEXT_STATE <= ACKEDS; -- release old EDS\r
+ when WREDS => NEXT_STATE <= ACKEDS; -- release old EDS\r
next_eds_done <= '1';\r
- when ACKEDS => NEXT_STATE <= DEL1;\r
- when DEL1 => NEXT_STATE <= DEL2;\r
- when DEL2 => NEXT_STATE <= SLEEP;\r
- \r
- when NBERR => NEXT_STATE <= EHDR;\r
+ when ACKEDS => NEXT_STATE <= DEL1;\r
+ when DEL1 => NEXT_STATE <= DEL2;\r
+ when DEL2 => NEXT_STATE <= SLEEP;\r
+\r
+ when NBERR => NEXT_STATE <= EHDR;\r
next_do_hdr <= '1';\r
- when FCERR => NEXT_STATE <= EHDR;\r
+ when FCERR => NEXT_STATE <= EHDR;\r
next_do_hdr <= '1';\r
- when RWERR => NEXT_STATE <= EHDR;\r
+ when RWERR => NEXT_STATE <= EHDR;\r
next_do_hdr <= '1';\r
- when AEERR => NEXT_STATE <= EHDR;\r
+ when AEERR => NEXT_STATE <= EHDR;\r
next_do_hdr <= '1';\r
- when EHDR => if( last_frame = '1' ) then\r
+ when EHDR => if( last_frame = '1' ) then\r
NEXT_STATE <= WREDS;\r
next_eds_wr <= '1';\r
else\r
next_ce_frm_ctr <= '1';\r
next_buf_done <= '1';\r
end if;\r
- when CCNT => NEXT_STATE <= CDEL0;\r
- when CDEL0 => NEXT_STATE <= CDEL1;\r
- when CDEL1 => if( last_frame = '1' ) then\r
+ when CCNT => NEXT_STATE <= CDEL0;\r
+ when CDEL0 => NEXT_STATE <= CDEL1;\r
+ when CDEL1 => if( last_frame = '1' ) then\r
NEXT_STATE <= WREDS;\r
next_eds_wr <= '1';\r
else\r
NEXT_STATE <= EHDR;\r
next_do_hdr <= '1';\r
end if;\r
- when others => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
-end process STATE_TRANSFORM; \r
+end process STATE_TRANSFORM;\r
\r
-- state decoding (ONLY FOR DEBUGGING!)\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_x <= x"00";\r
- when LOADFC => bsm_x <= x"01";\r
- when DELFC => bsm_x <= x"02";\r
- when CHECK => bsm_x <= x"03";\r
- when FULL => bsm_x <= x"04";\r
- when EMPTY => bsm_x <= x"05";\r
- when NBERR => bsm_x <= x"06";\r
- when CHKFC => bsm_x <= x"07";\r
- when FCERR => bsm_x <= x"08";\r
- when CHKRW => bsm_x <= x"09";\r
- when RWERR => bsm_x <= x"0a";\r
- when CHKAE => bsm_x <= x"0b";\r
- when AEERR => bsm_x <= x"0c";\r
- when FINIT => bsm_x <= x"0d";\r
- when FLOAD => bsm_x <= x"0e";\r
- when FZERO => bsm_x <= x"0f";\r
- when FREAD => bsm_x <= x"10";\r
- when FDONE => bsm_x <= x"11";\r
- when FDEL => bsm_x <= x"12";\r
- when FDEC => bsm_x <= x"13";\r
- when WREDS => bsm_x <= x"14";\r
- when ACKEDS => bsm_x <= x"15";\r
- when EHDR => bsm_x <= x"16";\r
- when CDEL0 => bsm_x <= x"17";\r
- when CDEL1 => bsm_x <= x"18";\r
- when CCNT => bsm_x <= x"19";\r
- when DEL0 => bsm_x <= x"20";\r
- when DEL1 => bsm_x <= x"21";\r
- when DEL2 => bsm_x <= x"22";\r
- when WHDR => bsm_x <= x"23";\r
- when others => bsm_x <= x"ff";\r
+ when SLEEP => bsm_x <= x"00";\r
+ when LOADFC => bsm_x <= x"01";\r
+ when DELFC => bsm_x <= x"02";\r
+ when CHECK => bsm_x <= x"03";\r
+ when FULL => bsm_x <= x"04";\r
+ when EMPTY => bsm_x <= x"05";\r
+ when NBERR => bsm_x <= x"06";\r
+ when CHKFC => bsm_x <= x"07";\r
+ when FCERR => bsm_x <= x"08";\r
+ when CHKRW => bsm_x <= x"09";\r
+ when RWERR => bsm_x <= x"0a";\r
+ when CHKAE => bsm_x <= x"0b";\r
+ when AEERR => bsm_x <= x"0c";\r
+ when FINIT => bsm_x <= x"0d";\r
+ when FLOAD => bsm_x <= x"0e";\r
+ when FZERO => bsm_x <= x"0f";\r
+ when FREAD => bsm_x <= x"10";\r
+ when FDONE => bsm_x <= x"11";\r
+ when FDEL => bsm_x <= x"12";\r
+ when FDEC => bsm_x <= x"13";\r
+ when WREDS => bsm_x <= x"14";\r
+ when ACKEDS => bsm_x <= x"15";\r
+ when EHDR => bsm_x <= x"16";\r
+ when CDEL0 => bsm_x <= x"17";\r
+ when CDEL1 => bsm_x <= x"18";\r
+ when CCNT => bsm_x <= x"19";\r
+ when DEL0 => bsm_x <= x"20";\r
+ when DEL1 => bsm_x <= x"21";\r
+ when DEL2 => bsm_x <= x"22";\r
+ when WHDR => bsm_x <= x"23";\r
+ when others => bsm_x <= x"ff";\r
end case;\r
end process STATE_DECODE;\r
\r
\r
raw_addr <= buf_half & buf_addr;\r
\r
----------------------------------------------------------------------------\r
--- threshold address counter\r
----------------------------------------------------------------------------\r
-THE_THR_ADDR_COUNTER_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- if ( (thr_addr_rst = '1') or (reset_in = '1') ) then\r
- thr_addr <= (others => '0');\r
- elsif( thr_addr_ce = '1' ) then\r
- thr_addr <= thr_addr + 1;\r
- end if;\r
- end if;\r
-end process THE_THR_ADDR_COUNTER_PROC;\r
-\r
--- was '3'\r
-thr_addr_ce <= dly_thr_addr_ce(2);\r
-thr_addr_rst <= dly_thr_addr_rst(2);\r
-\r
---------------------------------------------------------------------------\r
-- local frame counter, loaded / counted by SM for checking\r
---------------------------------------------------------------------------\r
cleaned_up <= next_cleaned_up;\r
buf_addr_done <= next_buf_addr_done;\r
buf_frame_valid <= frame_valid;\r
- buf_raw_addr <= raw_addr;\r
small_0_sum <= next_small_0_sum;\r
small_1_sum <= next_small_1_sum;\r
- dly_thr_addr_ce(7 downto 0) <= dly_thr_addr_ce(6 downto 0) & buf_addr_ce;\r
- dly_thr_addr_rst(7 downto 0) <= dly_thr_addr_rst(6 downto 0) & buf_addr_init;\r
+ max_num_words <= next_max_num_words;\r
+ thr_addr_qqq <= thr_addr_qq;\r
+ thr_addr_qq <= thr_addr_q;\r
+ thr_addr_q <= buf_raw_addr;\r
+ buf_raw_addr <= raw_addr;\r
end if;\r
end process THE_SYNC_PROC;\r
\r
---------------------------------------------------------------------------\r
--- DHDR information assembly\r
----------------------------------------------------------------------------\r
-dhdr_data_out(31 downto 29) <= "000"; -- reserved bits\r
-dhdr_data_out(28) <= '1'; -- packbit\r
-dhdr_data_out(27 downto 24) <= eds_data_in(7 downto 4);\r
-dhdr_data_out(23 downto 16) <= eds_data_in(15 downto 8);\r
-dhdr_data_out(15 downto 0) <= eds_data_in(31 downto 16);\r
-\r
-dhdr_length_out <= total_sum;\r
-\r
-dhdr_store_out <= eds_wr;\r
-\r
---##########################################################################\r
---##########################################################################\r
-\r
-- generate TimeOutCounters for all 16 APVs\r
+---------------------------------------------------------------------------\r
GEN_TOC: for i in 0 to 15 generate\r
THE_BUF_TOC: buf_toc\r
- port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- BUF_TICK_IN => buf_tick_in(i),\r
- BUF_START_IN => buf_start_in(i),\r
- WAITFRAME_IN => wait_frames,\r
- FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same\r
- BUF_LVL_IN => raw_data(i)(37 downto 30),\r
- GOODDATA_OUT => buf_gooddata(i),\r
- BADDATA_OUT => buf_baddata(i),\r
- NODATA_OUT => buf_nodata(i),\r
- READY_OUT => buf_ready(i),\r
- BSM_OUT => open,\r
- DBG_OUT => open\r
- );\r
+ port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ BUF_TICK_IN => buf_tick_in(i),\r
+ BUF_START_IN => buf_start_in(i),\r
+ WAITFRAME_IN => wait_frames,\r
+ FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same\r
+ BUF_LVL_IN => raw_data(i)(37 downto 30),\r
+ GOODDATA_OUT => buf_gooddata(i),\r
+ BADDATA_OUT => buf_baddata(i),\r
+ NODATA_OUT => buf_nodata(i),\r
+ READY_OUT => buf_ready(i),\r
+ BSM_OUT => open,\r
+ DBG_OUT => open\r
+ );\r
end generate GEN_TOC;\r
\r
+---------------------------------------------------------------------------\r
-- generate ALUs for all 16 APV data streams\r
+---------------------------------------------------------------------------\r
GEN_ALU: for i in 0 to 15 generate\r
THE_ALU: apv_pc_nc_alu\r
- port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => ld_frm_ctr,\r
- MAX_FRAMES_IN => eds_data_in(35 downto 32),\r
- CURR_FRAME_IN => done_ctr,\r
- LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG\r
- EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG\r
- BUF_GOOD_IN => buf_gooddata(i),\r
- BUF_BAD_IN => buf_baddata(i),\r
- BUF_IGNORE_IN => buf_nodata(i),\r
- ERROR_IN => errors,\r
- DO_HEADER_IN => do_hdr,\r
- DO_ERROR_IN => do_error,\r
- EVT_TYPE_IN => eds_data_in(6 downto 4), --evt_type_in, -- just a quick fix, does not work lateron!\r
- RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle\r
- RAW_DATA_IN => raw_data(i),\r
- PED_DATA_IN => ped_data(i),\r
- THR_DATA_IN => thr_data(i),\r
- FRAME_IN => buf_frame_valid, -- delayed by one cycle\r
- FIFO_DATA_OUT => fifo_data(i)(26 downto 0),\r
- WE_OUT => fifo_we(i),\r
- COUNT_OUT => fifo_data(i)(36 downto 27),\r
- ANYDATA_OUT => fifo_data(i)(37),\r
- DBG_OUT => open\r
- );\r
- fifo_data(i)(39) <= '0';\r
- fifo_data(i)(38) <= '0';\r
+ port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => ld_frm_ctr,\r
+ MAX_FRAMES_IN => eds_data_in(35 downto 32),\r
+ CURR_FRAME_IN => done_ctr,\r
+ LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG\r
+ EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG\r
+ BUF_GOOD_IN => buf_gooddata(i),\r
+ BUF_BAD_IN => buf_baddata(i),\r
+ BUF_IGNORE_IN => buf_nodata(i),\r
+ ERROR_IN => errors,\r
+ DO_HEADER_IN => do_hdr,\r
+ DO_ERROR_IN => do_error,\r
+ SUPPRESS_IN => eds_data_in(3), -- suppress bit\r
+ EVT_TYPE_IN => eds_data_in(2 downto 0), -- RICH data configuration bits\r
+ RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle\r
+ RAW_DATA_IN => raw_data(i),\r
+ PED_DATA_IN => ped_data(i),\r
+ THR_DATA_IN => thr_data(i),\r
+ FRAME_IN => buf_frame_valid, -- delayed by one cycle\r
+ FIFO_DATA_OUT => fifo_data(i)(26 downto 0),\r
+ WE_OUT => fifo_we(i),\r
+ COUNT_OUT => fifo_data(i)(36 downto 27),\r
+ ANYDATA_OUT => fifo_data(i)(37),\r
+ DBG_OUT => open\r
+ );\r
+ fifo_data(i)(39) <= '0';\r
+ fifo_data(i)(38) <= '0';\r
end generate GEN_ALU;\r
\r
frame_busy <= fifo_data(0)(26); -- WORKAROUND!\r
\r
---##################################################################################\r
---------------------------------------------------------------------------\r
-- Sum up all data words of one event\r
---------------------------------------------------------------------------\r
THE_DECODER_0: decoder_8bit\r
-port map( ADDRESS => fifo_we(7 downto 0),\r
- Q => next_small_0_sum(3 downto 0)\r
- );\r
+port map(\r
+ ADDRESS => fifo_we(7 downto 0),\r
+ Q => next_small_0_sum(3 downto 0)\r
+);\r
next_small_0_sum(4) <= '0';\r
\r
THE_DECODER_1: decoder_8bit\r
-port map( ADDRESS => fifo_we(15 downto 8),\r
- Q => next_small_1_sum(3 downto 0)\r
- );\r
+port map(\r
+ ADDRESS => fifo_we(15 downto 8),\r
+ Q => next_small_1_sum(3 downto 0)\r
+);\r
next_small_1_sum(4) <= '0';\r
\r
reset_sum <= reset_in or ld_frm_ctr;\r
\r
THE_FIRST_ADDER: adder_5bit\r
-port map( DATAA => small_0_sum,\r
- DATAB => small_1_sum,\r
- CLOCK => clk_in, \r
- RESET => reset_sum, -- BUG\r
- CLOCKEN => '1', \r
- RESULT => small_sum(4 downto 0)\r
- );\r
+port map(\r
+ DATAA => small_0_sum,\r
+ DATAB => small_1_sum,\r
+ CLOCK => clk_in,\r
+ RESET => reset_sum, -- BUG\r
+ CLOCKEN => '1',\r
+ RESULT => small_sum(4 downto 0)\r
+);\r
small_sum(15 downto 5) <= (others => '0');\r
\r
THE_ACCUMULATOR: adder_16bit\r
-port map( DATAA => small_sum,\r
- DATAB => total_sum,\r
- CLOCK => clk_in, \r
- RESET => reset_sum, -- BUG \r
- CLOCKEN => '1',\r
- RESULT => total_sum\r
- );\r
-\r
-fifo_we_out <= fifo_we;\r
-fifo_start_out <= do_start;\r
-fifo_done_out <= eds_wr;\r
---##################################################################################\r
-\r
-\r
--- Aliasing the data output\r
-fifo_0_data_out <= fifo_data(0);\r
-fifo_1_data_out <= fifo_data(1);\r
-fifo_2_data_out <= fifo_data(2);\r
-fifo_3_data_out <= fifo_data(3);\r
-fifo_4_data_out <= fifo_data(4);\r
-fifo_5_data_out <= fifo_data(5);\r
-fifo_6_data_out <= fifo_data(6);\r
-fifo_7_data_out <= fifo_data(7);\r
-fifo_8_data_out <= fifo_data(8);\r
-fifo_9_data_out <= fifo_data(9);\r
-fifo_10_data_out <= fifo_data(10);\r
-fifo_11_data_out <= fifo_data(11);\r
-fifo_12_data_out <= fifo_data(12);\r
-fifo_13_data_out <= fifo_data(13);\r
-fifo_14_data_out <= fifo_data(14);\r
-fifo_15_data_out <= fifo_data(15);\r
+port map(\r
+ DATAA => small_sum,\r
+ DATAB => total_sum,\r
+ CLOCK => clk_in,\r
+ RESET => reset_sum, -- BUG\r
+ CLOCKEN => '1',\r
+ RESULT => total_sum\r
+);\r
+\r
\r
---------------------------------------------------------------------------\r
+-- DHDR information assembly\r
---------------------------------------------------------------------------\r
-debug(15) <= frame_valid;\r
-debug(14) <= buf_frame_valid;\r
-debug(13 downto 0) <= (others => '0');\r
---debug(15) <= last_frame;\r
---debug(14) <= cleaned_up;\r
---debug(13 downto 12) <= (others => '0');\r
---debug(11 downto 8) <= loc_frm_ctr;\r
---debug(7 downto 4) <= to_do_ctr;\r
---debug(3 downto 0) <= done_ctr;\r
+DHDR_DATA_OUT(31 downto 29) <= "000"; -- reserved bits\r
+DHDR_DATA_OUT(28) <= '0'; -- packbit, MUST NEVER BE SET IN FEs\r
+DHDR_DATA_OUT(27 downto 24) <= eds_data_in(7 downto 4);\r
+DHDR_DATA_OUT(23 downto 16) <= eds_data_in(15 downto 8);\r
+DHDR_DATA_OUT(15 downto 0) <= eds_data_in(31 downto 16);\r
+DHDR_LENGTH_OUT <= total_sum;\r
+DHDR_STORE_OUT <= eds_wr;\r
+\r
---------------------------------------------------------------------------\r
+-- Output signals\r
---------------------------------------------------------------------------\r
-\r
+FIFO_0_DATA_OUT <= fifo_data(0);\r
+FIFO_1_DATA_OUT <= fifo_data(1);\r
+FIFO_2_DATA_OUT <= fifo_data(2);\r
+FIFO_3_DATA_OUT <= fifo_data(3);\r
+FIFO_4_DATA_OUT <= fifo_data(4);\r
+FIFO_5_DATA_OUT <= fifo_data(5);\r
+FIFO_6_DATA_OUT <= fifo_data(6);\r
+FIFO_7_DATA_OUT <= fifo_data(7);\r
+FIFO_8_DATA_OUT <= fifo_data(8);\r
+FIFO_9_DATA_OUT <= fifo_data(9);\r
+FIFO_10_DATA_OUT <= fifo_data(10);\r
+FIFO_11_DATA_OUT <= fifo_data(11);\r
+FIFO_12_DATA_OUT <= fifo_data(12);\r
+FIFO_13_DATA_OUT <= fifo_data(13);\r
+FIFO_14_DATA_OUT <= fifo_data(14);\r
+FIFO_15_DATA_OUT <= fifo_data(15);\r
+FIFO_WE_OUT <= fifo_we;\r
+FIFO_START_OUT <= do_start;\r
+FIFO_DONE_OUT <= eds_wr;\r
+EDS_DONE_OUT <= eds_done;\r
+BUF_DONE_OUT <= buf_done;\r
+BUF_ADDR_OUT <= raw_addr;\r
+PED_ADDR_OUT <= raw_addr;\r
+THR_ADDR_OUT <= thr_addr_qqq;\r
+FIFO_SPACE_REQ_OUT <= max_num_words;\r
\r
---------------------------------------------------------------------------\r
--- Output signals\r
+-- Debug signals\r
---------------------------------------------------------------------------\r
-eds_done_out <= eds_done;\r
-buf_done_out <= buf_done;\r
-buf_addr_out <= raw_addr;\r
-ped_addr_out <= raw_addr;\r
-thr_addr_out <= thr_addr;\r
+debug(15) <= frame_valid;\r
+debug(14) <= buf_frame_valid;\r
+debug(13 downto 0) <= (others => '0');\r
\r
---------------------------------------------------------------------------\r
-- DEBUG signals\r
---------------------------------------------------------------------------\r
-dbg_bsm_out <= bsm_x;\r
-dbg_out <= debug;\r
+DBG_BSM_OUT <= bsm_x;\r
+DBG_OUT <= debug;\r
\r
end behavioral;\r
-\r
-\r
- \r
-\r
-\r
-library ieee; \r
-use ieee.std_logic_1164.all; \r
-use ieee.std_logic_arith.all; \r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
entity pulse_stretch is\r
- port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- START_IN : in std_logic;\r
- PULSE_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ PULSE_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of pulse_stretch is\r
\r
- -- normal signals\r
- signal pulse_cnt : std_logic_vector(3 downto 0);\r
- signal pulse_cnt_ce : std_logic;\r
- signal pulse_x : std_logic;\r
- signal pulse : std_logic;\r
- \r
-begin \r
+-- normal signals\r
+signal pulse_cnt : std_logic_vector(3 downto 0);\r
+signal pulse_cnt_ce : std_logic;\r
+signal pulse_x : std_logic;\r
+signal pulse : std_logic;\r
+\r
+begin\r
\r
-- Pulse length counter\r
THE_PULSE_LENGTH_CTR: process( clk_in )\r
else\r
pulse <= pulse_x;\r
end if;\r
- end if; \r
+ end if;\r
end process THE_SYNC_PROC;\r
\r
\r
-- output signals\r
pulse_out <= pulse;\r
-debug_out(15 downto 4) <= (others => '0'); \r
+debug_out(15 downto 4) <= (others => '0');\r
debug_out(3 downto 0) <= pulse_cnt;\r
\r
-end behavioral; \r
+end behavioral;\r
use work.adcmv3_components.all;\r
\r
entity pulse_sync is\r
- port( CLK_A_IN : in std_logic;\r
- RESET_A_IN : in std_logic;\r
- PULSE_A_IN : in std_logic;\r
- CLK_B_IN : in std_logic;\r
- RESET_B_IN : in std_logic;\r
- PULSE_B_OUT : out std_logic\r
- );\r
+port(\r
+ CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+);\r
end;\r
\r
architecture behavioral of pulse_sync is\r
\r
- -- normal signals\r
- signal toggle_ff : std_logic;\r
- signal sync_q : std_logic;\r
- signal sync_qq : std_logic;\r
- signal sync_qqq : std_logic;\r
- signal pulse_b : std_logic;\r
- \r
+-- normal signals\r
+signal toggle_ff : std_logic;\r
+signal sync_q : std_logic;\r
+signal sync_qq : std_logic;\r
+signal sync_qqq : std_logic;\r
+signal pulse_b : std_logic;\r
+\r
begin\r
\r
-- toggle flip flop in clock domain A\r
use work.adcmv3_components.all;\r
\r
entity raw_buf_stage_new is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
- RESET_IN : in std_logic; -- general reset (100MHz)\r
- -- trigger related signals\r
- APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
- APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
- APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
- -- ADC0 signals\r
- ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
- ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
- ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
- ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
- ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
- ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
- ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
- ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
- ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
- -- ADC1 signals\r
- ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
- ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
- ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
- ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
- ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
- ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
- ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
- ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
- ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
- -- Slow control registers\r
- MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
- BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
- BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
- FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
- FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
- APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
- -- 100MHZ synchronous interface\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
- BUF_DONE_IN : in std_logic;\r
- BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
- BUF_START_OUT : out std_logic_vector(15 downto 0);\r
- BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
- BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
- BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- trigger related signals\r
+ APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
+ APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
+ APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
+ ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
+ ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
+ ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
+ ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
+ ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
+ ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
+ ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
+ ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
+ ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
+ ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
+ ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
+ ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
+ ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
+ ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
+ APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
+ -- 100MHZ synchronous interface\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : in std_logic;\r
+ BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of raw_buf_stage_new is\r
\r
- -- Reset signals, combinatorial and registered\r
- signal next_reset_all : std_logic; \r
- signal reset_all : std_logic; -- 40MHz clock domain\r
- signal next_reset : std_logic; \r
- signal reset : std_logic; -- 100MHz clock domain \r
-\r
- -- APV locker signals (arrays / vectors)\r
- type adc_data_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
- signal adc_data : adc_data_t;\r
- type apv_status_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
- signal apv_status : apv_status_t;\r
- type apv_frame_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
- signal apv_frame : apv_frame_t;\r
- type apv_channel_t is array (0 to 15) of std_logic_vector(6 downto 0); \r
- signal apv_channel : apv_channel_t;\r
- type apv_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
- signal apv_data : apv_data_t;\r
-\r
- signal apv_analog : std_logic_vector(15 downto 0);\r
- signal apv_start : std_logic_vector(15 downto 0);\r
- signal apv_last : std_logic_vector(15 downto 0);\r
-\r
- -- Buffer signals (arrays / vectors)\r
- type buf_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
- signal buf_data : buf_data_t;\r
- type buf_status_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
- signal buf_status : buf_status_t;\r
- type buf_frame_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
- signal buf_frame : buf_frame_t;\r
- type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
- signal buf_level : buf_level_t; \r
-\r
- signal buf_tick : std_logic_vector(15 downto 0);\r
- signal buf_start : std_logic_vector(15 downto 0);\r
- signal buf_ready : std_logic_vector(15 downto 0);\r
- signal buf_full : std_logic_vector(15 downto 0); \r
-\r
- signal next_raw_buf_full : std_logic;\r
- signal raw_buf_full : std_logic;\r
-\r
- -- Debug\r
- signal debug : std_logic_vector(63 downto 0);\r
- \r
+-- Reset signals, combinatorial and registered\r
+signal next_reset_all : std_logic;\r
+signal reset_all : std_logic; -- 40MHz clock domain\r
+signal next_reset : std_logic;\r
+signal reset : std_logic; -- 100MHz clock domain\r
+\r
+-- APV locker signals (arrays / vectors)\r
+type adc_data_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal adc_data : adc_data_t;\r
+type apv_status_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
+signal apv_status : apv_status_t;\r
+type apv_frame_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal apv_frame : apv_frame_t;\r
+type apv_channel_t is array (0 to 15) of std_logic_vector(6 downto 0);\r
+signal apv_channel : apv_channel_t;\r
+type apv_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal apv_data : apv_data_t;\r
+\r
+signal apv_analog : std_logic_vector(15 downto 0);\r
+signal apv_start : std_logic_vector(15 downto 0);\r
+signal apv_last : std_logic_vector(15 downto 0);\r
+\r
+-- Buffer signals (arrays / vectors)\r
+type buf_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal buf_data : buf_data_t;\r
+type buf_status_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
+signal buf_status : buf_status_t;\r
+type buf_frame_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal buf_frame : buf_frame_t;\r
+type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
+signal buf_level : buf_level_t;\r
+\r
+signal buf_tick : std_logic_vector(15 downto 0);\r
+signal buf_start : std_logic_vector(15 downto 0);\r
+signal buf_ready : std_logic_vector(15 downto 0);\r
+signal buf_full : std_logic_vector(15 downto 0);\r
+\r
+signal next_raw_buf_full : std_logic;\r
+signal raw_buf_full : std_logic;\r
+\r
+-- Debug\r
+signal debug : std_logic_vector(63 downto 0);\r
+\r
begin\r
\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
-- Reset handling\r
---------------------------------------------------------------------------\r
-next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain \r
+next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain\r
next_reset <= (reset_in or apv_reset_in); -- 100MHz clock domain\r
\r
THE_RESET_SYNC: state_sync\r
-port map( STATE_A_IN => next_reset_all,\r
- CLK_B_IN => clk_apv_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => reset_all\r
- );\r
+port map(\r
+ STATE_A_IN => next_reset_all,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset_all\r
+);\r
\r
\r
---------------------------------------------------------------------------\r
\r
-- APV locker, handles synchronisation and all the other stuff\r
THE_APV_LOCKER: apv_locker\r
- port map( CLK_APV_IN => clk_apv_in,\r
- RESET_IN => reset_all,\r
- SYNC_IN => apv_sync_in,\r
- ADC_RAW_IN => adc_data(i),\r
- ADC_VALID_IN => adc0_valid_in,\r
- APV_ON_IN => apv_on_in(i),\r
- BIT_LOW_IN => bit_low_in,\r
- BIT_HIGH_IN => bit_high_in,\r
- FL_LOW_IN => fl_low_in,\r
- FL_HIGH_IN => fl_high_in,\r
- STATUS_IGNORE_OUT => apv_status(i)(1),\r
- STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
- STATUS_BADADC_OUT => apv_status(i)(7),\r
- STATUS_LOCKED_OUT => apv_status(i)(5),\r
- STATUS_LOST_OUT => apv_status(i)(4),\r
- STATUS_NOSYNC_OUT => apv_status(i)(3),\r
- STATUS_MISSING_OUT => apv_status(i)(2),\r
- STATUS_TICKMARK_OUT => apv_status(i)(0),\r
- FRAME_ROW_OUT => apv_frame(i)(7 downto 0),\r
- FRAME_ERROR_OUT => apv_frame(i)(8), \r
- FRAME_OVF_OUT => apv_frame(i)(9),\r
- FRAME_UDF_OUT => apv_frame(i)(10),\r
- FRAME_FLAT_OUT => apv_frame(i)(11),\r
- FRAME_CTR_OUT => apv_data(i)(17 downto 14),\r
- APV_CHANNEL_OUT => apv_channel(i),\r
- APV_OVERFLOW_OUT => apv_data(i)(13),\r
- APV_UNDERFLOW_OUT => apv_data(i)(12),\r
- APV_RAW_OUT => apv_data(i)(11 downto 0),\r
- APV_ANALOG_OUT => apv_analog(i),\r
- APV_START_OUT => apv_start(i),\r
- APV_LAST_OUT => apv_last(i),\r
- DEBUG_OUT => open\r
- ); \r
- \r
+ port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ SYNC_IN => apv_sync_in,\r
+ ADC_RAW_IN => adc_data(i),\r
+ ADC_VALID_IN => adc0_valid_in,\r
+ APV_ON_IN => apv_on_in(i),\r
+ BIT_LOW_IN => bit_low_in,\r
+ BIT_HIGH_IN => bit_high_in,\r
+ FL_LOW_IN => fl_low_in,\r
+ FL_HIGH_IN => fl_high_in,\r
+ STATUS_IGNORE_OUT => apv_status(i)(1),\r
+ STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
+ STATUS_BADADC_OUT => apv_status(i)(7),\r
+ STATUS_LOCKED_OUT => apv_status(i)(5),\r
+ STATUS_LOST_OUT => apv_status(i)(4),\r
+ STATUS_NOSYNC_OUT => apv_status(i)(3),\r
+ STATUS_MISSING_OUT => apv_status(i)(2),\r
+ STATUS_TICKMARK_OUT => apv_status(i)(0),\r
+ FRAME_ROW_OUT => apv_frame(i)(7 downto 0),\r
+ FRAME_ERROR_OUT => apv_frame(i)(8),\r
+ FRAME_OVF_OUT => apv_frame(i)(9),\r
+ FRAME_UDF_OUT => apv_frame(i)(10),\r
+ FRAME_FLAT_OUT => apv_frame(i)(11),\r
+ FRAME_CTR_OUT => apv_data(i)(17 downto 14),\r
+ APV_CHANNEL_OUT => apv_channel(i),\r
+ APV_OVERFLOW_OUT => apv_data(i)(13),\r
+ APV_UNDERFLOW_OUT => apv_data(i)(12),\r
+ APV_RAW_OUT => apv_data(i)(11 downto 0),\r
+ APV_ANALOG_OUT => apv_analog(i),\r
+ APV_START_OUT => apv_start(i),\r
+ APV_LAST_OUT => apv_last(i),\r
+ DEBUG_OUT => open\r
+ );\r
+\r
-- raw buffer, stores frame data, all outputs are 100MHz synchronized\r
THE_APV_RAW_BUFFER: apv_raw_buffer\r
- port map( CLK_APV_IN => clk_apv_in,\r
- RESET_IN => reset_all,\r
- FRM_REQD_IN => apv_frame_reqd_in,\r
- MAX_TRG_NUM_IN => max_trg_num_in,\r
- ADC_ANALOG_IN => apv_analog(i),\r
- ADC_START_IN => apv_start(i),\r
- ADC_LAST_IN => apv_last(i),\r
- ADC_CHANNEL_IN => apv_channel(i),\r
- ADC_RAW_IN => apv_data(i),\r
- ADC_STATUS_IN => apv_status(i),\r
- ADC_FRAME_IN => apv_frame(i),\r
- BUF_CLK_IN => clk_in,\r
- BUF_RESET_IN => reset,\r
- BUF_START_OUT => buf_start(i),\r
- BUF_READY_OUT => buf_ready(i),\r
- BUF_ADDR_IN => buf_addr_in,\r
- BUF_DONE_IN => buf_done_in, \r
- BUF_DATA_OUT => buf_data(i),\r
- BUF_STATUS_OUT => buf_status(i),\r
- BUF_FRAME_OUT => buf_frame(i),\r
- BUF_GOOD_OUT => buf_level(i)(7),\r
- BUF_BROKEN_OUT => buf_level(i)(6),\r
- BUF_IGNORE_OUT => buf_level(i)(5),\r
- BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
- BUF_TICKMARK_OUT => buf_tick(i),\r
- BUF_FULL_OUT => buf_full(i),\r
- DEBUG_OUT => open\r
- );\r
+ port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ FRM_REQD_IN => apv_frame_reqd_in,\r
+ MAX_TRG_NUM_IN => max_trg_num_in,\r
+ ADC_ANALOG_IN => apv_analog(i),\r
+ ADC_START_IN => apv_start(i),\r
+ ADC_LAST_IN => apv_last(i),\r
+ ADC_CHANNEL_IN => apv_channel(i),\r
+ ADC_RAW_IN => apv_data(i),\r
+ ADC_STATUS_IN => apv_status(i),\r
+ ADC_FRAME_IN => apv_frame(i),\r
+ BUF_CLK_IN => clk_in,\r
+ BUF_RESET_IN => reset,\r
+ BUF_START_OUT => buf_start(i),\r
+ BUF_READY_OUT => buf_ready(i),\r
+ BUF_ADDR_IN => buf_addr_in,\r
+ BUF_DONE_IN => buf_done_in,\r
+ BUF_DATA_OUT => buf_data(i),\r
+ BUF_STATUS_OUT => buf_status(i),\r
+ BUF_FRAME_OUT => buf_frame(i),\r
+ BUF_GOOD_OUT => buf_level(i)(7),\r
+ BUF_BROKEN_OUT => buf_level(i)(6),\r
+ BUF_IGNORE_OUT => buf_level(i)(5),\r
+ BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
+ BUF_TICKMARK_OUT => buf_tick(i),\r
+ BUF_FULL_OUT => buf_full(i),\r
+ DEBUG_OUT => open\r
+ );\r
\r
end generate GEN_ADC0;\r
\r
\r
-- APV locker, handles synchronisation and all the other stuff\r
THE_APV_LOCKER: apv_locker\r
- port map( CLK_APV_IN => clk_apv_in,\r
- RESET_IN => reset_all,\r
- SYNC_IN => apv_sync_in,\r
- ADC_RAW_IN => adc_data(i),\r
- ADC_VALID_IN => adc1_valid_in,\r
- APV_ON_IN => apv_on_in(i),\r
- BIT_LOW_IN => bit_low_in,\r
- BIT_HIGH_IN => bit_high_in,\r
- FL_LOW_IN => fl_low_in,\r
- FL_HIGH_IN => fl_high_in,\r
- STATUS_IGNORE_OUT => apv_status(i)(1),\r
- STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
- STATUS_BADADC_OUT => apv_status(i)(7),\r
- STATUS_LOCKED_OUT => apv_status(i)(5),\r
- STATUS_LOST_OUT => apv_status(i)(4),\r
- STATUS_NOSYNC_OUT => apv_status(i)(3),\r
- STATUS_MISSING_OUT => apv_status(i)(2),\r
- STATUS_TICKMARK_OUT => apv_status(i)(0),\r
- FRAME_ROW_OUT => apv_frame(i)(7 downto 0),\r
- FRAME_ERROR_OUT => apv_frame(i)(8), \r
- FRAME_OVF_OUT => apv_frame(i)(9),\r
- FRAME_UDF_OUT => apv_frame(i)(10),\r
- FRAME_FLAT_OUT => apv_frame(i)(11),\r
- FRAME_CTR_OUT => apv_data(i)(17 downto 14),\r
- APV_CHANNEL_OUT => apv_channel(i),\r
- APV_OVERFLOW_OUT => apv_data(i)(13),\r
- APV_UNDERFLOW_OUT => apv_data(i)(12),\r
- APV_RAW_OUT => apv_data(i)(11 downto 0),\r
- APV_ANALOG_OUT => apv_analog(i),\r
- APV_START_OUT => apv_start(i),\r
- APV_LAST_OUT => apv_last(i),\r
- DEBUG_OUT => open\r
- ); \r
- \r
+ port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ SYNC_IN => apv_sync_in,\r
+ ADC_RAW_IN => adc_data(i),\r
+ ADC_VALID_IN => adc1_valid_in,\r
+ APV_ON_IN => apv_on_in(i),\r
+ BIT_LOW_IN => bit_low_in,\r
+ BIT_HIGH_IN => bit_high_in,\r
+ FL_LOW_IN => fl_low_in,\r
+ FL_HIGH_IN => fl_high_in,\r
+ STATUS_IGNORE_OUT => apv_status(i)(1),\r
+ STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
+ STATUS_BADADC_OUT => apv_status(i)(7),\r
+ STATUS_LOCKED_OUT => apv_status(i)(5),\r
+ STATUS_LOST_OUT => apv_status(i)(4),\r
+ STATUS_NOSYNC_OUT => apv_status(i)(3),\r
+ STATUS_MISSING_OUT => apv_status(i)(2),\r
+ STATUS_TICKMARK_OUT => apv_status(i)(0),\r
+ FRAME_ROW_OUT => apv_frame(i)(7 downto 0),\r
+ FRAME_ERROR_OUT => apv_frame(i)(8),\r
+ FRAME_OVF_OUT => apv_frame(i)(9),\r
+ FRAME_UDF_OUT => apv_frame(i)(10),\r
+ FRAME_FLAT_OUT => apv_frame(i)(11),\r
+ FRAME_CTR_OUT => apv_data(i)(17 downto 14),\r
+ APV_CHANNEL_OUT => apv_channel(i),\r
+ APV_OVERFLOW_OUT => apv_data(i)(13),\r
+ APV_UNDERFLOW_OUT => apv_data(i)(12),\r
+ APV_RAW_OUT => apv_data(i)(11 downto 0),\r
+ APV_ANALOG_OUT => apv_analog(i),\r
+ APV_START_OUT => apv_start(i),\r
+ APV_LAST_OUT => apv_last(i),\r
+ DEBUG_OUT => open\r
+ );\r
+\r
-- raw buffer, stores frame data, all outputs are 100MHz synchronized\r
THE_APV_RAW_BUFFER: apv_raw_buffer\r
- port map( CLK_APV_IN => clk_apv_in,\r
- RESET_IN => reset_all,\r
- FRM_REQD_IN => apv_frame_reqd_in,\r
- MAX_TRG_NUM_IN => max_trg_num_in,\r
- ADC_ANALOG_IN => apv_analog(i),\r
- ADC_START_IN => apv_start(i),\r
- ADC_LAST_IN => apv_last(i),\r
- ADC_CHANNEL_IN => apv_channel(i),\r
- ADC_RAW_IN => apv_data(i),\r
- ADC_STATUS_IN => apv_status(i),\r
- ADC_FRAME_IN => apv_frame(i),\r
- BUF_CLK_IN => clk_in,\r
- BUF_RESET_IN => reset,\r
- BUF_START_OUT => buf_start(i),\r
- BUF_READY_OUT => buf_ready(i),\r
- BUF_ADDR_IN => buf_addr_in,\r
- BUF_DONE_IN => buf_done_in, \r
- BUF_DATA_OUT => buf_data(i),\r
- BUF_STATUS_OUT => buf_status(i),\r
- BUF_FRAME_OUT => buf_frame(i),\r
- BUF_GOOD_OUT => buf_level(i)(7),\r
- BUF_BROKEN_OUT => buf_level(i)(6),\r
- BUF_IGNORE_OUT => buf_level(i)(5),\r
- BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
- BUF_TICKMARK_OUT => buf_tick(i),\r
- BUF_FULL_OUT => buf_full(i),\r
- DEBUG_OUT => open\r
- );\r
+ port map(\r
+ CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ FRM_REQD_IN => apv_frame_reqd_in,\r
+ MAX_TRG_NUM_IN => max_trg_num_in,\r
+ ADC_ANALOG_IN => apv_analog(i),\r
+ ADC_START_IN => apv_start(i),\r
+ ADC_LAST_IN => apv_last(i),\r
+ ADC_CHANNEL_IN => apv_channel(i),\r
+ ADC_RAW_IN => apv_data(i),\r
+ ADC_STATUS_IN => apv_status(i),\r
+ ADC_FRAME_IN => apv_frame(i),\r
+ BUF_CLK_IN => clk_in,\r
+ BUF_RESET_IN => reset,\r
+ BUF_START_OUT => buf_start(i),\r
+ BUF_READY_OUT => buf_ready(i),\r
+ BUF_ADDR_IN => buf_addr_in,\r
+ BUF_DONE_IN => buf_done_in,\r
+ BUF_DATA_OUT => buf_data(i),\r
+ BUF_STATUS_OUT => buf_status(i),\r
+ BUF_FRAME_OUT => buf_frame(i),\r
+ BUF_GOOD_OUT => buf_level(i)(7),\r
+ BUF_BROKEN_OUT => buf_level(i)(6),\r
+ BUF_IGNORE_OUT => buf_level(i)(5),\r
+ BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
+ BUF_TICKMARK_OUT => buf_tick(i),\r
+ BUF_FULL_OUT => buf_full(i),\r
+ DEBUG_OUT => open\r
+ );\r
\r
end generate GEN_ADC1;\r
\r
---------------------------------------------------------------------------\r
\r
buf_full_out <= raw_buf_full;\r
-buf_tick_out <= buf_tick; -- needed for TOCs\r
-buf_start_out <= buf_start; -- needed for TOCs\r
-buf_ready_out <= buf_ready; -- debug signal\r
+buf_tick_out <= buf_tick; -- needed for TOCs\r
+buf_start_out <= buf_start; -- needed for TOCs\r
+buf_ready_out <= buf_ready; -- debug signal\r
\r
-- Alias the outputs from generator\r
buf_0_data_out(17 downto 0) <= buf_data(0);\r
end behavioral;\r
\r
\r
- \r
+\r
\r
\r
-- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced!\r
\r
entity real_trg_handler is\r
- port( CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic; \r
- TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
- TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
- APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
- TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
- TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
- TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
- TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
- TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
- TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
- -- TRB LVL1 channel signals\r
- TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag \r
- TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number \r
- TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type\r
- TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
- TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
- RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter\r
- LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
- BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
- -- \r
- APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
- APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine\r
- EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
- EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
- EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
- EDS_READY_OUT : out std_logic; -- APV trigger sequence done\r
- DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ -- TRB LVL1 channel signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 4bit trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_LD_COUNTER_IN : in std_logic;\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ --\r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of real_trg_handler is\r
\r
- -- state machine signals\r
- type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS, COMP, CTAG, STAG,\r
- DTAG, WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- normal signals\r
- signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs\r
- signal trg_q : std_logic_vector(3 downto 0);\r
- signal trg_qq : std_logic_vector(3 downto 0);\r
- signal trg_qqq : std_logic_vector(3 downto 0);\r
- signal trg_qqqq : std_logic_vector(3 downto 0);\r
- signal trg_edge : std_logic_vector(3 downto 0); \r
- signal decoded_trg : std_logic_vector(3 downto 0);\r
- signal todo_start : std_logic_vector(3 downto 0);\r
- signal trg_found : std_logic;\r
- signal trg_pattern : std_logic_vector(3 downto 0);\r
-\r
- signal evtctr : std_logic_vector(15 downto 0); -- event counter\r
- signal ce_evtctr : std_logic;\r
- signal ce_evtctr_x : std_logic;\r
- signal frmctr : std_logic_vector(3 downto 0); -- frame counter\r
- signal ce_frmctr : std_logic;\r
- signal ce_frmctr_x : std_logic;\r
- signal todo_ctr : std_logic_vector(3 downto 0);\r
- signal todo_done_x : std_logic;\r
- signal todo_done : std_logic;\r
- signal apv_trgstart_x : std_logic;\r
- signal apv_trgstart : std_logic;\r
- signal eds_data : std_logic_vector(39 downto 0);\r
- signal eds_start : std_logic;\r
- signal eds_start_x : std_logic;\r
- signal eds_we : std_logic;\r
- signal eds_we_x : std_logic;\r
- signal eds_ready_x : std_logic; \r
- signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff\r
- signal apv_trg_finished : std_logic;\r
- signal accept_x : std_logic; -- we can accept a trigger\r
- signal accept : std_logic; \r
- signal missed_trg_x : std_logic;\r
- signal missed_trg : std_logic;\r
- signal missing_trg : std_logic;\r
- signal rst_status_x : std_logic;\r
- signal rst_status : std_logic;\r
-\r
- signal time_trg : std_logic_vector(3 downto 0);\r
-\r
- -- Information to be collected for the EDS\r
- signal trb_ttag_reg : std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag (16bit)\r
- signal trb_trnd_reg : std_logic_vector(7 downto 0); -- TRB LVL1 random byte (8bit)\r
- signal trb_ttype_reg : std_logic_vector(3 downto 0); -- TRB LVL1 trigger type (4bit) \r
- signal trg_pattern_reg : std_logic_vector(3 downto 0); -- timing trigger input pattern (4bit)\r
- signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit)\r
- signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit)\r
- signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit)\r
-\r
- signal store_local_x : std_logic;\r
- signal store_local : std_logic;\r
- signal store_remote_x : std_logic;\r
- signal store_remote : std_logic;\r
-\r
- signal time_trg_on : std_logic_vector(3 downto 0);\r
- signal time_trg_inv : std_logic_vector(3 downto 0);\r
- \r
- signal bsm_x : std_logic_vector(7 downto 0);\r
+-- state machine signals\r
+type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS,\r
+ WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG, TTLTRG);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- normal signals\r
+signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs\r
+signal trg_q : std_logic_vector(3 downto 0);\r
+signal trg_qq : std_logic_vector(3 downto 0);\r
+signal trg_qqq : std_logic_vector(3 downto 0);\r
+signal trg_qqqq : std_logic_vector(3 downto 0);\r
+signal trg_edge : std_logic_vector(3 downto 0);\r
+signal decoded_trg : std_logic_vector(3 downto 0);\r
+signal todo_start : std_logic_vector(3 downto 0);\r
+signal trg_found : std_logic;\r
+\r
+signal evtctr : std_logic_vector(15 downto 0); -- event counter\r
+signal ce_evtctr : std_logic;\r
+signal next_ce_evtctr : std_logic;\r
+signal frmctr : std_logic_vector(3 downto 0); -- frame counter\r
+signal ce_frmctr : std_logic;\r
+signal next_ce_frmctr : std_logic;\r
+signal todo_ctr : std_logic_vector(3 downto 0);\r
+signal next_todo_done : std_logic;\r
+signal todo_done : std_logic;\r
+signal next_apv_trgstart : std_logic;\r
+signal apv_trgstart : std_logic;\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_start : std_logic;\r
+signal next_eds_start : std_logic;\r
+signal eds_we : std_logic;\r
+signal next_eds_we : std_logic;\r
+signal next_eds_ready : std_logic;\r
+signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff\r
+signal apv_trg_finished : std_logic;\r
+signal next_accept : std_logic; -- we can accept a trigger\r
+signal accept : std_logic;\r
+signal next_missed_trg : std_logic;\r
+signal missed_trg : std_logic;\r
+signal missing_trg : std_logic;\r
+signal next_rst_status : std_logic;\r
+signal rst_status : std_logic;\r
+\r
+signal time_trg : std_logic_vector(3 downto 0);\r
+\r
+-- Information to be collected for the EDS\r
+signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit)\r
+signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit)\r
+signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit)\r
+\r
+signal next_store_local : std_logic;\r
+signal store_local : std_logic;\r
+signal next_rst_local : std_logic;\r
+signal rst_local : std_logic;\r
+\r
+signal time_trg_on : std_logic_vector(3 downto 0);\r
+signal time_trg_inv : std_logic_vector(3 downto 0);\r
+\r
+signal big_event_comb : std_logic;\r
+signal tag_sector_match_comb : std_logic;\r
+signal suppress_data_comb : std_logic;\r
+\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
\r
begin\r
\r
------------------------------------------------------------\r
-- Synchronize the external trigger inputs\r
THE_TIME_TRG_3_SYNC: state_sync\r
-port map( STATE_A_IN => time_trg_in(3),\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- STATE_B_OUT => time_trg(3)\r
- );\r
+port map(\r
+ STATE_A_IN => time_trg_in(3),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(3)\r
+);\r
THE_TIME_TRG_2_SYNC: state_sync\r
-port map( STATE_A_IN => time_trg_in(2),\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- STATE_B_OUT => time_trg(2)\r
- );\r
+port map(\r
+ STATE_A_IN => time_trg_in(2),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(2)\r
+);\r
THE_TIME_TRG_1_SYNC: state_sync\r
-port map( STATE_A_IN => time_trg_in(1),\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- STATE_B_OUT => time_trg(1)\r
- );\r
+port map(\r
+ STATE_A_IN => time_trg_in(1),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(1)\r
+);\r
THE_TIME_TRG_0_SYNC: state_sync\r
-port map( STATE_A_IN => time_trg_in(0),\r
- CLK_B_IN => clk_in,\r
- RESET_B_IN => reset_in,\r
- STATE_B_OUT => time_trg(0)\r
- );\r
+port map(\r
+ STATE_A_IN => time_trg_in(0),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(0)\r
+);\r
------------------------------------------------------------\r
\r
-- For all four possible hardware triggers we combine hardware and TRB inputs\r
end if;\r
end process THE_RISING_EDGES_PROC;\r
\r
--- Now we are almost done. \r
+-- Now we are almost done.\r
-- The detected edges are priorized.\r
-THE_TRG_PRIORITY_PROC: process( clk_in ) \r
+THE_TRG_PRIORITY_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
todo_start <= trg_0_todo_in;\r
trg_found <= '1';\r
else\r
+ -- case of "timingtriggerless trigger"?\r
decoded_trg <= "0000";\r
todo_start <= "0000";\r
trg_found <= '0';\r
THE_LOCALSTORE_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
- if( (reset_in = '1') or (eds_we = '1') ) then\r
- trg_pattern_reg <= (others => '0');\r
+ if( (reset_in = '1') or (rst_local = '1') ) then\r
trg_frmctr_reg <= (others => '0');\r
trg_frmnum_reg <= (others => '0');\r
trg_dectrg_reg <= (others => '0');\r
elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse\r
- trg_pattern_reg <= trg_pattern; -- BUGBUGBUG\r
trg_frmctr_reg <= frmctr;\r
trg_frmnum_reg <= todo_start;\r
trg_dectrg_reg <= decoded_trg;\r
if ( reset_in = '1' ) then\r
todo_ctr <= (others => '0');\r
elsif( store_local = '1' ) then\r
- todo_ctr <= trg_frmnum_reg; --todo_start;\r
+ todo_ctr <= trg_frmnum_reg;\r
elsif( ce_frmctr = '1' ) then\r
todo_ctr <= todo_ctr - 1;\r
end if;\r
end if;\r
end process THE_TODO_COUNTER_PROC;\r
-todo_done_x <= '1' when (todo_ctr = x"0") else '0';\r
+next_todo_done <= '1' when (todo_ctr = x"0") else '0';\r
\r
--- We need to store some information for the EDS... from TRBnet LVL1 trigger endpoint\r
-THE_REMOTESTORE_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- trb_ttag_reg <= (others => '0');\r
- trb_trnd_reg <= (others => '0');\r
- trb_ttype_reg <= (others => '0'); \r
- elsif( store_remote = '1' ) then\r
- trb_ttag_reg <= trb_ttag_in;\r
- trb_trnd_reg <= trb_trnd_in;\r
- trb_ttype_reg <= trb_ttype_in;\r
- end if;\r
- end if;\r
-end process THE_REMOTESTORE_PROC;\r
\r
-------------------------------------------------\r
-------------------------------------------------\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
- trg_pattern <= (others => '0');\r
todo_done <= '0';\r
else\r
- trg_pattern <= trg_edge;\r
- todo_done <= todo_done_x;\r
+ todo_done <= next_todo_done;\r
end if;\r
end if;\r
end process THE_TRG_SYNC_PROC;\r
\r
-- A statemachine handles all actions for filling out the trigger information sheet\r
-- state registers\r
-STATE_MEM: process( clk_in ) \r
+STATE_MEM: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
eds_ready <= '0';\r
eds_we <= '0';\r
eds_start <= '0';\r
+ rst_local <= '0';\r
store_local <= '0';\r
- store_remote <= '0';\r
apv_trgstart <= '0';\r
accept <= '1';\r
missed_trg <= '0';\r
rst_status <= '0';\r
else\r
CURRENT_STATE <= NEXT_STATE;\r
- ce_evtctr <= ce_evtctr_x;\r
- ce_frmctr <= ce_frmctr_x;\r
- eds_ready <= eds_ready_x;\r
- eds_we <= eds_we_x;\r
- eds_start <= eds_start_x;\r
- store_local <= store_local_x;\r
- store_remote <= store_remote_x;\r
- apv_trgstart <= apv_trgstart_x;\r
- accept <= accept_x;\r
- missed_trg <= missed_trg_x;\r
- rst_status <= rst_status_x;\r
+ ce_evtctr <= next_ce_evtctr;\r
+ ce_frmctr <= next_ce_frmctr;\r
+ eds_ready <= next_eds_ready;\r
+ eds_we <= next_eds_we;\r
+ eds_start <= next_eds_start;\r
+ rst_local <= next_rst_local;\r
+ store_local <= next_store_local;\r
+ apv_trgstart <= next_apv_trgstart;\r
+ accept <= next_accept;\r
+ missed_trg <= next_missed_trg;\r
+ rst_status <= next_rst_status;\r
end if;\r
end if;\r
end process STATE_MEM;\r
\r
-- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, trb_trgrcvd_in, apv_trg_finished, busy_release_in, missing_trg )\r
+STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, trb_trgrcvd_in, apv_trg_finished, \r
+ busy_release_in, trb_ttype_in(3), trb_tinfo_in(7) )\r
begin\r
- NEXT_STATE <= SLEEP; -- avoid latches\r
- ce_evtctr_x <= '0'; \r
- ce_frmctr_x <= '0';\r
- eds_ready_x <= '0';\r
- eds_we_x <= '0';\r
- eds_start_x <= '0';\r
- store_local_x <= '0';\r
- store_remote_x <= '0';\r
- apv_trgstart_x <= '0';\r
- accept_x <= '0';\r
- missed_trg_x <= '0';\r
- rst_status_x <= '0';\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_ce_evtctr <= '0';\r
+ next_ce_frmctr <= '0';\r
+ next_eds_ready <= '0';\r
+ next_eds_we <= '0';\r
+ next_eds_start <= '0';\r
+ next_rst_local <= '0';\r
+ next_store_local <= '0';\r
+ next_apv_trgstart <= '0';\r
+ next_accept <= '0';\r
+ next_missed_trg <= '0';\r
+ next_rst_status <= '0';\r
case CURRENT_STATE is\r
-- not good. if no timing trigger was received but a trb trigger arrives, we must do something!\r
- when SLEEP => if ( trg_found = '1' ) then\r
+ when SLEEP => if ( trg_found = '1' ) then\r
-- normal way: timing trigger found\r
- NEXT_STATE <= STORE;\r
- store_local_x <= '1';\r
- eds_start_x <= '1';\r
- elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') ) then\r
- -- bad way: missing timing trigger\r
- NEXT_STATE <= BADTRG;\r
- missed_trg_x <= '1';\r
+ NEXT_STATE <= STORE;\r
+ next_store_local <= '1';\r
+ next_eds_start <= '1';\r
+ elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') and (trb_ttype_in(3) = '1') and (trb_tinfo_in(7) = '1') ) then\r
+ NEXT_STATE <= TTLTRG;\r
+ elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') and ((trb_ttype_in(3) = '0') or (trb_tinfo_in(7) = '0')) ) then\r
+ NEXT_STATE <= BADTRG;\r
+ next_missed_trg <= '1';\r
else\r
- NEXT_STATE <= SLEEP;\r
- accept_x <= '1';\r
+ NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
end if;\r
- when BADTRG => NEXT_STATE <= TRBS;\r
- store_remote_x <= '1';\r
- when STORE => NEXT_STATE <= START;\r
- apv_trgstart_x <= '1';\r
- when START => NEXT_STATE <= CHECK;\r
- when CHECK => if( todo_done = '1' ) then\r
+ when TTLTRG => NEXT_STATE <= TRBS;\r
+ when BADTRG => NEXT_STATE <= TRBS;\r
+ when STORE => NEXT_STATE <= START;\r
+ next_apv_trgstart <= '1';\r
+ when START => NEXT_STATE <= CHECK;\r
+ when CHECK => if( todo_done = '1' ) then\r
NEXT_STATE <= WAPV;\r
else\r
- NEXT_STATE <= COUNT;\r
- ce_frmctr_x <= '1';\r
+ NEXT_STATE <= COUNT;\r
+ next_ce_frmctr <= '1';\r
end if;\r
- when COUNT => NEXT_STATE <= RELAX;\r
- when RELAX => NEXT_STATE <= CHECK;\r
- when WAPV => if( apv_trg_finished = '1' ) then\r
+ when COUNT => NEXT_STATE <= RELAX;\r
+ when RELAX => NEXT_STATE <= CHECK;\r
+ when WAPV => if( apv_trg_finished = '1' ) then\r
NEXT_STATE <= WLVL1;\r
else\r
NEXT_STATE <= WAPV;\r
end if;\r
- when WLVL1 => if( trb_trgrcvd_in = '1' ) then\r
- NEXT_STATE <= TRBS;\r
- store_remote_x <= '1';\r
+ when WLVL1 => if( trb_trgrcvd_in = '1' ) then\r
+ NEXT_STATE <= TRBS;\r
else\r
NEXT_STATE <= WLVL1;\r
end if;\r
- when TRBS => NEXT_STATE <= CTAG;\r
- when CTAG => NEXT_STATE <= STAG;\r
- when STAG => NEXT_STATE <= DTAG;\r
- when DTAG => if( missing_trg = '0' ) then\r
- -- everything is fine\r
- NEXT_STATE <= WEDS;\r
- eds_we_x <= '1';\r
- else\r
- -- we missed a timing trigger, so no EDS was created\r
- NEXT_STATE <= CNTEVT;\r
- ce_evtctr_x <= '1';\r
- end if;\r
- when WEDS => NEXT_STATE <= CNTEVT;\r
- ce_evtctr_x <= '1';\r
- when CNTEVT => NEXT_STATE <= WDEL0;\r
- when WDEL0 => NEXT_STATE <= WDEL1;\r
- when WDEL1 => NEXT_STATE <= WBUSY;\r
- when WBUSY => if( busy_release_in = '1' ) then\r
- NEXT_STATE <= DONE;\r
- eds_ready_x <= '1';\r
+ when TRBS => NEXT_STATE <= WEDS;\r
+ next_eds_we <= '1';\r
+ next_rst_local <= '1';\r
+ when WEDS => NEXT_STATE <= CNTEVT;\r
+ next_ce_evtctr <= '1';\r
+ when CNTEVT => NEXT_STATE <= WDEL0;\r
+ when WDEL0 => NEXT_STATE <= WDEL1;\r
+ when WDEL1 => NEXT_STATE <= WBUSY;\r
+ when WBUSY => if( busy_release_in = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ next_eds_ready <= '1';\r
else\r
NEXT_STATE <= WBUSY;\r
end if;\r
- when DONE => if( trb_trgrcvd_in = '0' ) then -- mind the state synchronizer delay!!!\r
- NEXT_STATE <= SLEEP;\r
- accept_x <= '1';\r
- rst_status_x <= '1';\r
+ when DONE => if( trb_trgrcvd_in = '0' ) then -- mind the state synchronizer delay!!!\r
+ NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ next_rst_status <= '1';\r
else\r
NEXT_STATE <= DONE;\r
end if;\r
- when others => NEXT_STATE <= SLEEP;\r
- accept_x <= '1';\r
+ when others => NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
end case;\r
end process STATE_TRANSFORM;\r
\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_x <= x"00";\r
- when STORE => bsm_x <= x"01"; \r
- when START => bsm_x <= x"02";\r
- when CHECK => bsm_x <= x"03";\r
- when COUNT => bsm_x <= x"04";\r
- when RELAX => bsm_x <= x"14";\r
- when WAPV => bsm_x <= x"05";\r
- when WLVL1 => bsm_x <= x"06";\r
- when TRBS => bsm_x <= x"07";\r
- when CTAG => bsm_x <= x"08";\r
- when STAG => bsm_x <= x"09";\r
- when DTAG => bsm_x <= x"0a";\r
- when WEDS => bsm_x <= x"0b";\r
- when WDEL0 => bsm_x <= x"0c";\r
- when WDEL1 => bsm_x <= x"0d";\r
- when WBUSY => bsm_x <= x"0e";\r
- when DONE => bsm_x <= x"0f";\r
- when CNTEVT => bsm_x <= x"10";\r
- when BADTRG => bsm_x <= x"11";\r
- when others => bsm_x <= x"ff";\r
+ when SLEEP => bsm_x <= x"00";\r
+ when STORE => bsm_x <= x"01";\r
+ when START => bsm_x <= x"02";\r
+ when CHECK => bsm_x <= x"03";\r
+ when COUNT => bsm_x <= x"04";\r
+ when RELAX => bsm_x <= x"14";\r
+ when WAPV => bsm_x <= x"05";\r
+ when WLVL1 => bsm_x <= x"06";\r
+ when TRBS => bsm_x <= x"07";\r
+ when WEDS => bsm_x <= x"0b";\r
+ when WDEL0 => bsm_x <= x"0c";\r
+ when WDEL1 => bsm_x <= x"0d";\r
+ when WBUSY => bsm_x <= x"0e";\r
+ when DONE => bsm_x <= x"0f";\r
+ when CNTEVT => bsm_x <= x"10";\r
+ when BADTRG => bsm_x <= x"11";\r
+ when TTLTRG => bsm_x <= x"12";\r
+ when others => bsm_x <= x"ff";\r
end case;\r
end process STATE_DECODE;\r
\r
THE_EVENT_COUNTER_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
- if( (reset_in = '1') or (rst_lvl1_counter_in = '1') ) then\r
+ if ( reset_in = '1' ) then\r
evtctr <= (others => '0');\r
+ elsif( lvl1_ld_counter_in = '1' ) then\r
+ evtctr <= lvl1_counter_in; -- update with value from TRBnet counter\r
elsif( ce_evtctr = '1' ) then\r
evtctr <= evtctr + 1;\r
end if;\r
if( rising_edge(clk_in) ) then\r
if( (reset_in = '1') or (rst_status = '1') ) then\r
missing_trg <= '0';\r
- elsif( missed_trg = '1' ) then\r
- missing_trg <= '1';\r
- end if;\r
+ elsif( missed_trg = '1' ) then\r
+ missing_trg <= '1';\r
+ end if;\r
end if;\r
end process THE_MISSED_TRG_REG;\r
\r
+-- Now for something completely different: as we have two sectors connected\r
+-- to one GbE hub in the final setup, we must do a trick to stay below 64kB \r
+-- subevent size.\r
+-- So in all cases where 128 channels per event are requested, only those ADCM\r
+-- will produce data where the last bit of sector number and trigger number matches.\r
+-- I.e.: odd sectors fire on odd trigger numbers, even sectors on even trigger numbers.\r
+\r
+-- potentially dangerous (aka big) event\r
+big_event_comb <= '1' when (trb_tinfo_in(10 downto 8) = b"000") or -- RAW128\r
+ (trb_tinfo_in(10 downto 8) = b"001") or -- PED128\r
+ (trb_tinfo_in(10 downto 8) = b"010") or -- PED128THR\r
+ (trb_tinfo_in(10 downto 8) = b"100") -- NC64PED64\r
+ else '0';\r
+\r
+-- sector number matches trigger number\r
+tag_sector_match_comb <= '1' when ( sector_in(0) = trb_ttag_in(0) ) else '0';\r
+\r
+-- when to drop data\r
+suppress_data_comb <= (big_event_comb and not tag_sector_match_comb) or trb_tinfo_in(0);\r
+\r
-- EDS bits:\r
eds_data(39 downto 36) <= trg_frmctr_reg;\r
eds_data(35 downto 32) <= trg_frmnum_reg;\r
-eds_data(31 downto 16) <= trb_ttag_reg;\r
-eds_data(15 downto 8) <= trb_trnd_reg;\r
-eds_data(7 downto 4) <= trb_ttype_reg;\r
-eds_data(3 downto 0) <= trg_pattern_reg;\r
+eds_data(31 downto 16) <= trb_ttag_in;\r
+eds_data(15 downto 8) <= trb_trnd_in;\r
+eds_data(7 downto 4) <= trb_ttype_in;\r
+eds_data(3) <= suppress_data_comb; --trb_tinfo_in(0); -- suppress output bit\r
+eds_data(2 downto 0) <= trb_tinfo_in(10 downto 8); -- RICH data configuration bits\r
\r
-- output signals\r
apv_trgstart_out <= apv_trgstart;\r
\r
debug_out(63 downto 32) <= (others => '0');\r
debug_out(31 downto 24) <= evtctr(7 downto 0);\r
-debug_out(23 downto 16) <= trb_ttag_reg(7 downto 0);\r
+debug_out(23 downto 16) <= trb_ttag_in(7 downto 0);\r
debug_out(15) <= ce_evtctr;\r
debug_out(14) <= '0';\r
debug_out(13) <= missing_trg;\r
-library ieee; \r
-use ieee.std_logic_1164.all; \r
-use ieee.std_logic_arith.all; \r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
use ieee.std_logic_unsigned.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
entity reboot_handler is\r
- port( RESET_IN : in std_logic;\r
- CLK_IN : in std_logic;\r
- START_IN : in std_logic;\r
- REBOOT_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ REBOOT_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of reboot_handler is\r
\r
- -- normal signals \r
- signal reboot_counter : std_logic_vector(15 downto 0);\r
- signal reboot_ce : std_logic;\r
- signal reboot_x : std_logic;\r
- signal reboot : std_logic;\r
- \r
-begin \r
+-- normal signals\r
+signal reboot_counter : std_logic_vector(15 downto 0);\r
+signal reboot_ce : std_logic;\r
+signal reboot_x : std_logic;\r
+signal reboot : std_logic;\r
+\r
+begin\r
\r
-- Latch the start pulse\r
THE_START_PULSE: process( clk_in )\r
-- output signals\r
reboot_out <= reboot;\r
\r
-debug_out(15 downto 0) <= reboot_counter; \r
+debug_out(15 downto 0) <= reboot_counter;\r
\r
-end behavioral; \r
+end behavioral;\r
library work;\r
use work.adcmv3_components.all;\r
\r
--- This module takes ROW and ERROR information from all sixteen raw buffers, and \r
+-- This module takes ROW and ERROR information from all sixteen raw buffers, and\r
-- checks if the APVs with "good data" buffers are OK.\r
-- APV frame errors are sensed, as well as APV row errors.\r
-- The row error recognition is based somehow on the old RICH RC logic, as it takes\r
-- this reference row.\r
\r
entity ref_row_sel is\r
- port( CLK_IN : in std_logic;\r
- READY_IN : in std_logic_vector(15 downto 0); -- buffer ready signals (data or timeout)\r
- GOODDATA_IN : in std_logic_vector(15 downto 0); -- buffer data good signals\r
- FRAME_0_IN : in std_logic_vector(11 downto 0);\r
- FRAME_1_IN : in std_logic_vector(11 downto 0);\r
- FRAME_2_IN : in std_logic_vector(11 downto 0);\r
- FRAME_3_IN : in std_logic_vector(11 downto 0);\r
- FRAME_4_IN : in std_logic_vector(11 downto 0);\r
- FRAME_5_IN : in std_logic_vector(11 downto 0);\r
- FRAME_6_IN : in std_logic_vector(11 downto 0);\r
- FRAME_7_IN : in std_logic_vector(11 downto 0);\r
- FRAME_8_IN : in std_logic_vector(11 downto 0);\r
- FRAME_9_IN : in std_logic_vector(11 downto 0);\r
- FRAME_10_IN : in std_logic_vector(11 downto 0);\r
- FRAME_11_IN : in std_logic_vector(11 downto 0);\r
- FRAME_12_IN : in std_logic_vector(11 downto 0);\r
- FRAME_13_IN : in std_logic_vector(11 downto 0);\r
- FRAME_14_IN : in std_logic_vector(11 downto 0);\r
- FRAME_15_IN : in std_logic_vector(11 downto 0);\r
- READY_OUT : out std_logic; -- all buffers reported being ready for data transport\r
- VALID_BUFS_OUT : out std_logic; -- at least one APV raw buffer has data to fetch \r
- ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
- APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
- APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
- REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
- DBG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ READY_IN : in std_logic_vector(15 downto 0); -- buffer ready signals (data or timeout)\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0); -- buffer data good signals\r
+ FRAME_0_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_1_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_2_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_3_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_4_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_5_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_6_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_7_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_8_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_9_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_10_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_11_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_12_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_13_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_14_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_15_IN : in std_logic_vector(11 downto 0);\r
+ READY_OUT : out std_logic; -- all buffers reported being ready for data transport\r
+ VALID_BUFS_OUT : out std_logic; -- at least one APV raw buffer has data to fetch\r
+ ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
+ APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
+ APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
+ REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of ref_row_sel is\r
\r
- -- normal signals\r
- signal debug_x : std_logic_vector(15 downto 0);\r
- \r
- signal next_sel_ref_row : std_logic_vector(3 downto 0);\r
- signal sel_ref_row : std_logic_vector(3 downto 0);\r
- signal next_valid_bufs : std_logic;\r
- signal valid_bufs : std_logic;\r
- signal next_all_ready : std_logic;\r
- signal all_ready : std_logic;\r
- \r
- signal ref_row : std_logic_vector(7 downto 0); -- selected reference row number\r
- \r
- signal next_row_match : std_logic_vector(15 downto 0);\r
- signal row_match : std_logic_vector(15 downto 0); -- APV frame row matches reference number\r
- \r
- signal next_apv_error : std_logic_vector(15 downto 0);\r
- signal apv_error : std_logic_vector(15 downto 0); -- APV frame error is set\r
- \r
- signal next_frame_row_err : std_logic;\r
- signal frame_row_err : std_logic;\r
- signal next_frame_apv_err : std_logic;\r
- signal frame_apv_err : std_logic;\r
-\r
- \r
+-- normal signals\r
+signal debug_x : std_logic_vector(15 downto 0);\r
+\r
+signal next_sel_ref_row : std_logic_vector(3 downto 0);\r
+signal sel_ref_row : std_logic_vector(3 downto 0);\r
+signal next_valid_bufs : std_logic;\r
+signal valid_bufs : std_logic;\r
+signal next_all_ready : std_logic;\r
+signal all_ready : std_logic;\r
+\r
+signal ref_row : std_logic_vector(7 downto 0); -- selected reference row number\r
+\r
+signal next_row_match : std_logic_vector(15 downto 0);\r
+signal row_match : std_logic_vector(15 downto 0); -- APV frame row matches reference number\r
+\r
+signal next_apv_error : std_logic_vector(15 downto 0);\r
+signal apv_error : std_logic_vector(15 downto 0); -- APV frame error is set\r
+\r
+signal next_frame_row_err : std_logic;\r
+signal frame_row_err : std_logic;\r
+signal next_frame_apv_err : std_logic;\r
+signal frame_apv_err : std_logic;\r
+\r
+\r
begin\r
\r
-- Sync process\r
begin\r
if( rising_edge(clk_in) ) then\r
case sel_ref_row is\r
- when "0000" => ref_row <= frame_0_in(7 downto 0);\r
- when "0001" => ref_row <= frame_1_in(7 downto 0);\r
- when "0010" => ref_row <= frame_2_in(7 downto 0);\r
- when "0011" => ref_row <= frame_3_in(7 downto 0);\r
- when "0100" => ref_row <= frame_4_in(7 downto 0);\r
- when "0101" => ref_row <= frame_5_in(7 downto 0);\r
- when "0110" => ref_row <= frame_6_in(7 downto 0);\r
- when "0111" => ref_row <= frame_7_in(7 downto 0);\r
- when "1000" => ref_row <= frame_8_in(7 downto 0);\r
- when "1001" => ref_row <= frame_9_in(7 downto 0);\r
- when "1010" => ref_row <= frame_10_in(7 downto 0);\r
- when "1011" => ref_row <= frame_11_in(7 downto 0);\r
- when "1100" => ref_row <= frame_12_in(7 downto 0);\r
- when "1101" => ref_row <= frame_13_in(7 downto 0);\r
- when "1110" => ref_row <= frame_14_in(7 downto 0);\r
- when "1111" => ref_row <= frame_15_in(7 downto 0);\r
- when others => ref_row <= x"ee"; -- will not be used... all cases are covered.\r
+ when "0000" => ref_row <= frame_0_in(7 downto 0);\r
+ when "0001" => ref_row <= frame_1_in(7 downto 0);\r
+ when "0010" => ref_row <= frame_2_in(7 downto 0);\r
+ when "0011" => ref_row <= frame_3_in(7 downto 0);\r
+ when "0100" => ref_row <= frame_4_in(7 downto 0);\r
+ when "0101" => ref_row <= frame_5_in(7 downto 0);\r
+ when "0110" => ref_row <= frame_6_in(7 downto 0);\r
+ when "0111" => ref_row <= frame_7_in(7 downto 0);\r
+ when "1000" => ref_row <= frame_8_in(7 downto 0);\r
+ when "1001" => ref_row <= frame_9_in(7 downto 0);\r
+ when "1010" => ref_row <= frame_10_in(7 downto 0);\r
+ when "1011" => ref_row <= frame_11_in(7 downto 0);\r
+ when "1100" => ref_row <= frame_12_in(7 downto 0);\r
+ when "1101" => ref_row <= frame_13_in(7 downto 0);\r
+ when "1110" => ref_row <= frame_14_in(7 downto 0);\r
+ when "1111" => ref_row <= frame_15_in(7 downto 0);\r
+ when others => ref_row <= x"ee"; -- will not be used... all cases are covered.\r
end case;\r
end if;\r
end process THE_REF_ROW_SELECT_PROC;\r
-- Only channels with GOODDATA are to be taken into account; if the channel is invalid, we ignore it.\r
\r
next_row_match(0) <= '1' when ( (gooddata_in(0) = '0') or\r
- ((gooddata_in(0) = '1') and (frame_0_in(7 downto 0) = ref_row) ) ) \r
- else '0';\r
+ ((gooddata_in(0) = '1') and (frame_0_in(7 downto 0) = ref_row) ) )\r
+ else '0';\r
next_row_match(1) <= '1' when ( (gooddata_in(1) = '0') or\r
- ((gooddata_in(1) = '1') and (frame_1_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(1) = '1') and (frame_1_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(2) <= '1' when ( (gooddata_in(2) = '0') or\r
- ((gooddata_in(2) = '1') and (frame_2_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(2) = '1') and (frame_2_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(3) <= '1' when ( (gooddata_in(3) = '0') or\r
- ((gooddata_in(3) = '1') and (frame_3_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(3) = '1') and (frame_3_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(4) <= '1' when ( (gooddata_in(4) = '0') or\r
- ((gooddata_in(4) = '1') and (frame_4_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(4) = '1') and (frame_4_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(5) <= '1' when ( (gooddata_in(5) = '0') or\r
- ((gooddata_in(5) = '1') and (frame_5_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(5) = '1') and (frame_5_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(6) <= '1' when ( (gooddata_in(6) = '0') or\r
- ((gooddata_in(6) = '1') and (frame_6_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(6) = '1') and (frame_6_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(7) <= '1' when ( (gooddata_in(7) = '0') or\r
- ((gooddata_in(7) = '1') and (frame_7_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(7) = '1') and (frame_7_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(8) <= '1' when ( (gooddata_in(8) = '0') or\r
- ((gooddata_in(8) = '1') and (frame_8_in(7 downto 0) = ref_row) ) ) \r
- else '0';\r
+ ((gooddata_in(8) = '1') and (frame_8_in(7 downto 0) = ref_row) ) )\r
+ else '0';\r
next_row_match(9) <= '1' when ( (gooddata_in(9) = '0') or\r
- ((gooddata_in(9) = '1') and (frame_9_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(9) = '1') and (frame_9_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(10) <= '1' when ( (gooddata_in(10) = '0') or\r
- ((gooddata_in(10) = '1') and (frame_10_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(10) = '1') and (frame_10_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(11) <= '1' when ( (gooddata_in(11) = '0') or\r
- ((gooddata_in(11) = '1') and (frame_11_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(11) = '1') and (frame_11_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(12) <= '1' when ( (gooddata_in(12) = '0') or\r
- ((gooddata_in(12) = '1') and (frame_12_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(12) = '1') and (frame_12_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(13) <= '1' when ( (gooddata_in(13) = '0') or\r
- ((gooddata_in(13) = '1') and (frame_13_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(13) = '1') and (frame_13_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(14) <= '1' when ( (gooddata_in(14) = '0') or\r
- ((gooddata_in(14) = '1') and (frame_14_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(14) = '1') and (frame_14_in(7 downto 0) = ref_row) ) )\r
else '0';\r
next_row_match(15) <= '1' when ( (gooddata_in(15) = '0') or\r
- ((gooddata_in(15) = '1') and (frame_15_in(7 downto 0) = ref_row) ) ) \r
+ ((gooddata_in(15) = '1') and (frame_15_in(7 downto 0) = ref_row) ) )\r
else '0';\r
\r
-- APV error recognition - same issue.\r
next_frame_apv_err <= '1' when ( apv_error /= x"0000" ) else '0';\r
\r
-- output signals\r
-valid_bufs_out <= valid_bufs; \r
+valid_bufs_out <= valid_bufs;\r
ready_out <= all_ready;\r
row_error_out <= frame_row_err;\r
apv_error_out <= frame_apv_err;\r
use work.adcmv3_components.all;\r
\r
entity reset_handler is\r
- port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
- RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
- CLK_IN : in std_logic;\r
- TRB_RESET_IN : in std_logic;\r
- RESET_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
+port( \r
+ CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
+ RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
+ CLK_IN : in std_logic;\r
+ TRB_RESET_IN : in std_logic;\r
+ RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
end;\r
\r
architecture behavioral of reset_handler is\r
\r
-- normal signals\r
- signal async_sampler : std_logic_vector(7 downto 0);\r
- signal async_pulse_x : std_logic;\r
- signal async_pulse : std_logic;\r
- signal reset_cnt : std_logic_vector(15 downto 0);\r
- signal debug : std_logic_vector(15 downto 0);\r
- signal reset : std_logic;\r
+signal async_sampler : std_logic_vector(7 downto 0);\r
+signal async_pulse_x : std_logic;\r
+signal async_pulse : std_logic;\r
+signal reset_cnt : std_logic_vector(15 downto 0);\r
+signal debug : std_logic_vector(15 downto 0);\r
+signal reset : std_logic;\r
\r
- attribute syn_preserve : boolean;\r
- attribute syn_preserve of async_sampler : signal is true;\r
- attribute syn_preserve of async_pulse : signal is true;\r
- attribute syn_preserve of reset : signal is true;\r
- attribute syn_preserve of reset_cnt : signal is true;\r
+attribute syn_preserve : boolean;\r
+attribute syn_preserve of async_sampler : signal is true;\r
+attribute syn_preserve of async_pulse : signal is true;\r
+attribute syn_preserve of reset : signal is true;\r
+attribute syn_preserve of reset_cnt : signal is true;\r
\r
begin \r
\r
-- one global reset counter\r
THE_GLOBAL_RESET_PROC: process( clk_in )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then\r
- reset_cnt <= (others => '0');\r
- reset <= '1';\r
- else\r
- reset_cnt <= reset_cnt + 1;\r
- reset <= '1';\r
- if( reset_cnt = x"001F" ) then\r
- reset <= '0';\r
- reset_cnt <= x"001F";\r
- end if;\r
- end if;\r
- end if;\r
+ if( rising_edge(clk_in) ) then\r
+ if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then\r
+ reset_cnt <= (others => '0');\r
+ reset <= '1';\r
+ else\r
+ reset_cnt <= reset_cnt + 1;\r
+ reset <= '1';\r
+ if( reset_cnt = x"001F" ) then\r
+ reset <= '0';\r
+ reset_cnt <= x"001F";\r
+ end if;\r
+ end if;\r
+ end if;\r
end process THE_GLOBAL_RESET_PROC;\r
\r
\r
-- Output signals\r
debug_out <= debug;\r
reset_out <= reset;\r
- \r
+ \r
end behavioral; \r
-
\ No newline at end of file
+
\ No newline at end of file
use work.adcmv3_components.all;
entity rich_trb is
-port( CLK100M_IN : in std_logic; -- SerDes exclusive clock
- SYSCLK_IN : in std_logic; -- fabric clock
- RESET_IN : in std_logic; -- synchronous reset
- -- SFP connections
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_PRESENT_IN : in std_logic;
- SD_TXDIS_OUT : out std_logic;
- SD_LOS_IN : in std_logic;
- ONEWIRE_INOUT : inout std_logic;
- -- common regIO status / control registers
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
- -- status register input to regIO / control register output from regIO
- CONTROL_OUT : out std_logic_vector(63 downto 0);
- STATUS_IN : in std_logic_vector(127 downto 0);
- -- LVL1 signals
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_TRG_RECEIVED_OUT : out std_logic;
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- LVL1_TRG_RELEASE_IN : in std_logic;
- TIMING_TRG_FOUND_IN : in std_logic;
- -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)
- IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag
- IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information
- IPU_START_READOUT_OUT : out std_logic; -- gimme data!
- IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR
- IPU_DATAREADY_IN : in std_logic; -- data is valid
- IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM
- IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle
- IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)
- IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern
- -- regIO bus
- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
- REGIO_DATAREADY_IN : in std_logic;
- REGIO_NO_MORE_DATA_IN : in std_logic;
- REGIO_WRITE_ACK_IN : in std_logic;
- REGIO_UNKNOWN_ADDR_IN : in std_logic;
- REGIO_TIMEOUT_OUT : out std_logic;
- -- status LEDs
- LED_LINK_STAT : out std_logic;
- LED_LINK_TXD : out std_logic;
- LED_LINK_RXD : out std_logic;
- LINK_BSM_OUT : out std_logic_vector(3 downto 0);
- RESET_OUT : out std_logic;
- -- Debug
- DEBUG : out std_logic_vector(63 downto 0)
- );
+port(
+ CLK100M_IN : in std_logic; -- SerDes exclusive clock
+ SYSCLK_IN : in std_logic; -- fabric clock
+ RESET_IN : in std_logic; -- synchronous reset
+ -- SFP connections
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_PRESENT_IN : in std_logic;
+ SD_TXDIS_OUT : out std_logic;
+ SD_LOS_IN : in std_logic;
+ ONEWIRE_INOUT : inout std_logic;
+ -- common regIO status / control registers
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
+ -- status register input to regIO / control register output from regIO
+ CONTROL_OUT : out std_logic_vector(63 downto 0);
+ STATUS_IN : in std_logic_vector(127 downto 0);
+ -- LVL1 signals
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_OUT : out std_logic;
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ LVL1_TRG_RELEASE_IN : in std_logic;
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_INT_TRG_UPDATE_OUT : out std_logic;
+ TIMING_TRG_FOUND_IN : in std_logic;
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)
+ IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag
+ IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information
+ IPU_START_READOUT_OUT : out std_logic; -- gimme data!
+ IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR
+ IPU_DATAREADY_IN : in std_logic; -- data is valid
+ IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM
+ IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle
+ IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)
+ IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern
+ -- regIO bus
+ REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
+ REGIO_DATAREADY_IN : in std_logic;
+ REGIO_NO_MORE_DATA_IN : in std_logic;
+ REGIO_WRITE_ACK_IN : in std_logic;
+ REGIO_UNKNOWN_ADDR_IN : in std_logic;
+ REGIO_TIMEOUT_OUT : out std_logic;
+ -- status LEDs
+ LED_LINK_STAT : out std_logic;
+ LED_LINK_TXD : out std_logic;
+ LED_LINK_RXD : out std_logic;
+ LINK_BSM_OUT : out std_logic_vector(3 downto 0);
+ RESET_OUT : out std_logic;
+ -- Debug
+ DEBUG : out std_logic_vector(63 downto 0)
+);
end entity;
architecture rich_arch of rich_trb is
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of rich_arch : architecture is "RICH_TRB_group";
+-- Placer Directives
+attribute HGROUP : string;
+-- for whole architecture
+attribute HGROUP of rich_arch : architecture is "RICH_TRB_group";
- -- Signals
- signal clk_en : std_logic;
- signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_out : std_logic;
- signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_in : std_logic;
- signal med_stat_debug : std_logic_vector(63 downto 0);
- signal med_ctrl_op : std_logic_vector(15 downto 0);
- signal med_stat_op : std_logic_vector(15 downto 0);
+-- Signals
+signal clk_en : std_logic;
+signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal med_dataready_in : std_logic;
+signal med_read_out : std_logic;
+signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal med_dataready_out : std_logic;
+signal med_read_in : std_logic;
+signal med_stat_debug : std_logic_vector(63 downto 0);
+signal med_ctrl_op : std_logic_vector(15 downto 0);
+signal med_stat_op : std_logic_vector(15 downto 0);
- -- general purpose control and status registers in regIO
- signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0);
- signal regio_stat_regs : std_logic_vector(32*4-1 downto 0);
-
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
-
- signal debug_x : std_logic_vector(63 downto 0);
-
- signal stat_debug_1 : std_logic_vector(31 downto 0);
+-- general purpose control and status registers in regIO
+signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0);
+signal regio_stat_regs : std_logic_vector(32*4-1 downto 0);
+
+signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+
+signal debug_x : std_logic_vector(63 downto 0);
+
+signal stat_debug_1 : std_logic_vector(31 downto 0);
begin
-- Debug
debug <= debug_x;
-
+
-- Clock assignment. We don't use CLK_EN really in our designs.
clk_en <= '1';
-- Serdes
-------------------------------------------------------------
THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe
-generic map( SERDES_NUM => 2 )
-port map( CLK => clk100m_in,
- SYSCLK => sysclk_in,
- RESET => reset_in,
- CLK_EN => clk_en,
- --Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => sd_rxd_p_in,
- SD_RXD_N_IN => sd_rxd_n_in,
- SD_TXD_P_OUT => sd_txd_p_out,
- SD_TXD_N_OUT => sd_txd_n_out,
- SD_REFCLK_P_IN => '1',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => sd_present_in,
- SD_LOS_IN => sd_los_in,
- SD_TXDIS_OUT => sd_txdis_out,
- -- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op, -- input
- STAT_DEBUG => med_stat_debug,
- CTRL_DEBUG => (others => '0')
- );
+generic map(
+ SERDES_NUM => 2
+)
+port map(
+ CLK => clk100m_in,
+ SYSCLK => sysclk_in,
+ RESET => reset_in,
+ CLEAR => '0',
+ CLK_EN => clk_en,
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => sd_rxd_p_in,
+ SD_RXD_N_IN => sd_rxd_n_in,
+ SD_TXD_P_OUT => sd_txd_p_out,
+ SD_TXD_N_OUT => sd_txd_n_out,
+ SD_REFCLK_P_IN => '1',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => sd_present_in,
+ SD_LOS_IN => sd_los_in,
+ SD_TXDIS_OUT => sd_txdis_out,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op, -- input
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+);
--debug_x <= med_stat_debug;
debug_x(18 downto 16) <= med_packet_num_out; -- MED_PACKET_NUM_IN
debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN
--- 16 MED_DATA_IN : in std_logic_vector(15 downto 0);
--- 3 MED_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
--- 1 MED_DATAREADY_IN : in std_logic;
--- 1 MED_READ_OUT : out std_logic;
--- 16 MED_DATA_OUT : out std_logic_vector(15 downto 0);
--- 3 MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
--- 1 MED_DATAREADY_OUT : out std_logic;
--- 1 MED_READ_IN : in std_logic;
--- 42
-
------------------------------------------------------------
-- Full featured HADES endpoint
-------------------------------------------------------------
THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full
-generic map( USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before?
- REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES),
- REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO),
- BROADCAST_BITMASK => x"FB", -- RICH uses 0xfffb as subnet mask for broadcasts
- REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
- REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
- --standard values for output registers
- REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_00000000_00000000",
- --set to 0 for unused ctrl registers to save resources
- REGIO_USED_CTRL_REGS => "00000001",
- --set to 0 for each unused bit in a register
- REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
- REGIO_USE_DAT_PORT => c_YES,
- REGIO_INIT_ADDRESS => x"fb00",
- REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
- REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
- REGIO_INIT_ENDPOINT_ID => x"0001",
- REGIO_COMPILE_TIME => VERSION_NUMBER_TIME,
- REGIO_COMPILE_VERSION => x"0003",
- REGIO_HARDWARE_VERSION => x"0002_0000",
- REGIO_USE_1WIRE_INTERFACE => c_YES,
- CLOCK_FREQUENCY => 100
- )
-port map( CLK => sysclk_in,
- RESET => reset_in,
- CLK_EN => clk_en,
- -- Media direction port
- MED_DATAREADY_OUT => med_dataready_out,
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out,
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
- -- LVL1 trigger APL
- LVL1_TRG_TYPE_OUT => lvl1_trg_type_out,
- LVL1_TRG_RECEIVED_OUT => lvl1_trg_received_out,
- LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out,
- LVL1_TRG_CODE_OUT => lvl1_trg_code_out,
- LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out,
- LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in,
- LVL1_TRG_RELEASE_IN => lvl1_trg_release_in,
- LVL1_INT_TRG_NUMBER_OUT => open, -- unknown!!!
- -- IPU Port
- IPU_NUMBER_OUT => ipu_number_out,
- IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
- IPU_INFORMATION_OUT => ipu_information_out,
- IPU_START_READOUT_OUT => ipu_start_readout_out,
- IPU_DATA_IN => ipu_data_in,
- IPU_DATAREADY_IN => ipu_dataready_in,
- IPU_READOUT_FINISHED_IN => ipu_readout_finished_in,
- IPU_READ_OUT => ipu_read_out,
- IPU_LENGTH_IN => ipu_length_in,
- IPU_ERROR_PATTERN_IN => ipu_error_pattern_in,
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg,
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
- REGIO_REGISTERS_IN => regio_stat_regs,
- REGIO_REGISTERS_OUT => regio_ctrl_regs,
- COMMON_STAT_REG_STROBE => open, --: out std_logic_vector(std_COMSTATREG-1 downto 0);
- COMMON_CTRL_REG_STROBE => open, --: out std_logic_vector(std_COMCTRLREG-1 downto 0);
- STAT_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
- CTRL_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when using internal data port
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
- --IDRAM is used if no 1-wire interface, onewire used otherwise
- REGIO_IDRAM_DATA_IN => x"0000", -- not used
- REGIO_IDRAM_DATA_OUT => open, -- not used
- REGIO_IDRAM_ADDR_IN => "000", -- not used
- REGIO_IDRAM_WR_IN => '0', -- not used
- REGIO_ONEWIRE_INOUT => onewire_inout,
- REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
- REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
- -- New stuff?!?
- TRIGGER_MONITOR_IN => timing_trg_found_in,
- GLOBAL_TIME_OUT => open,
- LOCAL_TIME_OUT => open,
- TIME_SINCE_LAST_TRG_OUT => open,
- TIMER_US_TICK_OUT => open,
- -- Status and debug
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => stat_debug_1, --open,
- STAT_DEBUG_2 => open,
- MED_STAT_OP => open,
- CTRL_MPLEX => x"00000000",
- IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open
- );
+generic map(
+ USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before?
+ REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES),
+ REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO),
+ BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts
+ REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000",
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS => "0000000000000001",
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
+ REGIO_USE_DAT_PORT => c_YES,
+ REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register!
+ REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
+ REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_COMPILE_TIME => VERSION_NUMBER_TIME,
+ REGIO_COMPILE_VERSION => x"0003",
+ REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
+ REGIO_USE_1WIRE_INTERFACE => c_YES,
+ CLOCK_FREQUENCY => 100
+)
+port map(
+ CLK => sysclk_in,
+ RESET => reset_in,
+ CLK_EN => clk_en,
+ -- Media direction port
+ MED_DATAREADY_OUT => med_dataready_out,
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out,
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+ -- LVL1 trigger APL
+ LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
+ LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
+ LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ LVL1_TRG_DATA_VALID_OUT => lvl1_trg_received_out,
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_found_in,
+ LVL1_TRG_TYPE_OUT => lvl1_trg_type_out,
+ LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out,
+ LVL1_TRG_CODE_OUT => lvl1_trg_code_out,
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out,
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in,
+ LVL1_TRG_RELEASE_IN => lvl1_trg_release_in,
+ LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
+ -- IPU Port
+ IPU_NUMBER_OUT => ipu_number_out,
+ IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
+ IPU_INFORMATION_OUT => ipu_information_out,
+ IPU_START_READOUT_OUT => ipu_start_readout_out,
+ IPU_DATA_IN => ipu_data_in,
+ IPU_DATAREADY_IN => ipu_dataready_in,
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished_in,
+ IPU_READ_OUT => ipu_read_out,
+ IPU_LENGTH_IN => ipu_length_in,
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern_in,
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_REGISTERS_IN => regio_stat_regs,
+ REGIO_REGISTERS_OUT => regio_ctrl_regs,
+ COMMON_STAT_REG_STROBE => open,
+ COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number
+ STAT_REG_STROBE => open,
+ CTRL_REG_STROBE => open,
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN => x"0000", -- not used
+ REGIO_IDRAM_DATA_OUT => open, -- not used
+ REGIO_IDRAM_ADDR_IN => "000", -- not used
+ REGIO_IDRAM_WR_IN => '0', -- not used
+ REGIO_ONEWIRE_INOUT => onewire_inout,
+ REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
+ REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
+ -- New stuff?!?
+ GLOBAL_TIME_OUT => open,
+ LOCAL_TIME_OUT => open,
+ TIME_SINCE_LAST_TRG_OUT => open,
+ TIMER_TICKS_OUT => open,
+ -- Status and debug
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => stat_debug_1, --open,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => x"00000000",
+ IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open
+);
-- Control register assignment
common_ctrl_reg_out <= common_ctrl_reg;
-- User status register
-regio_stat_regs <= status_in;
-control_out <= regio_ctrl_regs;
+regio_stat_regs <= status_in;
+control_out <= regio_ctrl_regs;
+lvl1_int_trg_update_out <= common_ctrl_reg_strobe(1);
+lvl1_int_trg_number_out <= common_ctrl_reg(47 downto 32);
-- FPGA LEDs
led_link_stat <= not med_stat_op(9); -- link status
-led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive
+led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive
led_link_txd <= not med_stat_op(11); -- data transmit
link_bsm_out <= med_stat_op(7 downto 4); -- LSM state bits
reset_out <= med_stat_op(13); -- TRB generated reset
end architecture;
-
\ No newline at end of file
+
\ No newline at end of file
\r
\r
entity slave_bus is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- RegIO signals\r
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus \r
- REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
- REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
- REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
- REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
- REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
- REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
- REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
- REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- -- 1Wire connections\r
- ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
- ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
- BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- ADC 0 SPI connections\r
- SPI_ADC0_CS_OUT : out std_logic;\r
- SPI_ADC0_SCK_OUT : out std_logic;\r
- SPI_ADC0_SDO_OUT : out std_logic;\r
- ADC0_PLL_LOCKED_IN : in std_logic;\r
- ADC0_PD_OUT : out std_logic;\r
- ADC0_RST_OUT : out std_logic;\r
- ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
- ADC0_CLK_IN : in std_logic;\r
- ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
- ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
- APV0_RST_OUT : out std_logic;\r
- -- ADC 1 SPI connections\r
- SPI_ADC1_CS_OUT : out std_logic;\r
- SPI_ADC1_SCK_OUT : out std_logic;\r
- SPI_ADC1_SDO_OUT : out std_logic;\r
- ADC1_PLL_LOCKED_IN : in std_logic;\r
- ADC1_PD_OUT : out std_logic;\r
- ADC1_RST_OUT : out std_logic;\r
- ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
- ADC1_CLK_IN : in std_logic;\r
- ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
- ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
- APV1_RST_OUT : out std_logic;\r
- -- User specific inputs / outputs\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- -- pedestal interface\r
- PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
- PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
- PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
- -- threshold interface\r
- THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
- THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
- THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
- -- APV control / status\r
- CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
- STAT_0_IN : in std_logic_vector(15 downto 0);\r
- STAT_1_IN : in std_logic_vector(15 downto 0);\r
- STAT_2_IN : in std_logic_vector(15 downto 0);\r
- STAT_3_IN : in std_logic_vector(15 downto 0);\r
- STAT_4_IN : in std_logic_vector(15 downto 0);\r
- STAT_5_IN : in std_logic_vector(15 downto 0);\r
- STAT_6_IN : in std_logic_vector(15 downto 0);\r
- STAT_7_IN : in std_logic_vector(15 downto 0);\r
- STAT_8_IN : in std_logic_vector(15 downto 0);\r
- STAT_9_IN : in std_logic_vector(15 downto 0);\r
- STAT_10_IN : in std_logic_vector(15 downto 0);\r
- STAT_11_IN : in std_logic_vector(15 downto 0);\r
- STAT_12_IN : in std_logic_vector(15 downto 0);\r
- STAT_13_IN : in std_logic_vector(15 downto 0);\r
- STAT_14_IN : in std_logic_vector(15 downto 0);\r
- STAT_15_IN : in std_logic_vector(15 downto 0);\r
- -- some control signals\r
- CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
- CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
- CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
- STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
- -- temporary stuff\r
- TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
- TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
- -- Debug\r
- DEBUG_OUT : out std_logic_vector(63 downto 0);\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT : out std_logic;\r
+ SPI_ADC0_SCK_OUT : out std_logic;\r
+ SPI_ADC0_SDO_OUT : out std_logic;\r
+ ADC0_PLL_LOCKED_IN : in std_logic;\r
+ ADC0_PD_OUT : out std_logic;\r
+ ADC0_RST_OUT : out std_logic;\r
+ ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC0_CLK_IN : in std_logic;\r
+ ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV0_RST_OUT : out std_logic;\r
+ -- ADC 1 SPI connections\r
+ SPI_ADC1_CS_OUT : out std_logic;\r
+ SPI_ADC1_SCK_OUT : out std_logic;\r
+ SPI_ADC1_SDO_OUT : out std_logic;\r
+ ADC1_PLL_LOCKED_IN : in std_logic;\r
+ ADC1_PD_OUT : out std_logic;\r
+ ADC1_RST_OUT : out std_logic;\r
+ ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC1_CLK_IN : in std_logic;\r
+ ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV1_RST_OUT : out std_logic;\r
+ -- User specific inputs / outputs\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- pedestal interface\r
+ PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
+ PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- threshold interface\r
+ THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
+ THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- APV control / status\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- some control signals\r
+ CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
+ STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
+ -- temporary stuff\r
+ TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
+ TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
+ -- Debug\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+);\r
end entity;\r
\r
architecture Behavioral of slave_bus is\r
\r
- -- Signals\r
- signal slv_read : std_logic_vector(15-1 downto 0);\r
- signal slv_write : std_logic_vector(15-1 downto 0);\r
- signal slv_busy : std_logic_vector(15-1 downto 0);\r
- signal slv_ack : std_logic_vector(15-1 downto 0);\r
- signal slv_addr : std_logic_vector(15*16-1 downto 0);\r
- signal slv_data_rd : std_logic_vector(15*32-1 downto 0);\r
- signal slv_data_wr : std_logic_vector(15*32-1 downto 0);\r
- \r
- -- SPI controller BRAM lines\r
- signal spi_bram_addr : std_logic_vector(7 downto 0);\r
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
- signal spi_bram_we : std_logic;\r
- \r
- signal spi_cs : std_logic;\r
- signal spi_sck : std_logic;\r
- signal spi_sdi : std_logic;\r
- signal spi_sdo : std_logic;\r
- signal spi_debug : std_logic_vector(31 downto 0);\r
- \r
- signal ctrl_lvl : std_logic_vector(31 downto 0);\r
- signal ctrl_trg : std_logic_vector(31 downto 0);\r
- signal ctrl_pll : std_logic_vector(15 downto 0);\r
- \r
- signal debug : std_logic_vector(63 downto 0);\r
- signal onewire_debug : std_logic_vector(63 downto 0);\r
- \r
+-- Signals\r
+signal slv_read : std_logic_vector(15-1 downto 0);\r
+signal slv_write : std_logic_vector(15-1 downto 0);\r
+signal slv_busy : std_logic_vector(15-1 downto 0);\r
+signal slv_ack : std_logic_vector(15-1 downto 0);\r
+signal slv_addr : std_logic_vector(15*16-1 downto 0);\r
+signal slv_data_rd : std_logic_vector(15*32-1 downto 0);\r
+signal slv_data_wr : std_logic_vector(15*32-1 downto 0);\r
+\r
+-- SPI controller BRAM lines\r
+signal spi_bram_addr : std_logic_vector(7 downto 0);\r
+signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
+signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
+signal spi_bram_we : std_logic;\r
+\r
+signal spi_cs : std_logic;\r
+signal spi_sck : std_logic;\r
+signal spi_sdi : std_logic;\r
+signal spi_sdo : std_logic;\r
+signal spi_debug : std_logic_vector(31 downto 0);\r
+\r
+signal ctrl_lvl : std_logic_vector(31 downto 0);\r
+signal ctrl_trg : std_logic_vector(31 downto 0);\r
+signal ctrl_pll : std_logic_vector(15 downto 0);\r
+\r
+signal debug : std_logic_vector(63 downto 0);\r
+signal onewire_debug : std_logic_vector(63 downto 0);\r
+\r
begin\r
\r
-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
-generic map( PORT_NUMBER => 15,\r
- PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories \r
- 1 => x"a800", -- threshold memories\r
- 2 => x"8040", -- I2C master\r
- 3 => x"c000", -- 1Wire master + memory\r
- 4 => x"d000", -- SPI master\r
- 5 => x"d100", -- SPI data memory \r
- 6 => x"d010", -- ADC0 SPI \r
- 7 => x"d020", -- ADC1 SPI\r
- 8 => x"b000", -- APV control / status\r
- 9 => x"b010", -- ADC level settings\r
- 10 => x"b020", -- trigger settings\r
- 11 => x"b030", -- PLL settings\r
- 12 => x"f000", -- ADC 0 snooper\r
- 13 => x"f800", -- ADC 1 snooper\r
- 14 => x"8000", -- test register (busy)\r
- others => x"0000"), \r
- PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories\r
- 1 => 11, -- threshold memories\r
- 2 => 0, -- I2C master\r
- 3 => 6, -- 1Wire master + memory\r
- 4 => 1, -- SPI master\r
- 5 => 6, -- SPI data memory\r
- 6 => 0, -- ADC0 SPI\r
- 7 => 0, -- ADC1 SPI\r
- 8 => 4, -- APV control / status \r
- 9 => 0, -- ADC level settings\r
- 10 => 0, -- trigger settings\r
- 11 => 0, -- PLL settings\r
- 12 => 10, -- ADC 0 snooper\r
- 13 => 10, -- ADC 1 snooper\r
- 14 => 0, -- test register (normal)\r
- others => 0)\r
- )\r
-port map( CLK => clk_in,\r
- RESET => reset_in,\r
- DAT_ADDR_IN => regio_addr_in,\r
- DAT_DATA_IN => regio_data_in,\r
- DAT_DATA_OUT => regio_data_out,\r
- DAT_READ_ENABLE_IN => regio_read_enable_in,\r
- DAT_WRITE_ENABLE_IN => regio_write_enable_in,\r
- DAT_TIMEOUT_IN => regio_timeout_in,\r
- DAT_DATAREADY_OUT => regio_dataready_out,\r
- DAT_WRITE_ACK_OUT => regio_write_ack_out,\r
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_out,\r
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out,\r
- -- pedestal memories\r
- BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
- BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
- BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
- BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), \r
- BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
- BUS_TIMEOUT_OUT(0) => open,\r
- BUS_DATAREADY_IN(0) => slv_ack(0),\r
- BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
- BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
- BUS_UNKNOWN_ADDR_IN(0) => '0',\r
- -- threshold memories\r
- BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
- BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
- BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
- BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), \r
- BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
- BUS_TIMEOUT_OUT(1) => open,\r
- BUS_DATAREADY_IN(1) => slv_ack(1),\r
- BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
- BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
- BUS_UNKNOWN_ADDR_IN(1) => '0',\r
- -- I2C master\r
- BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
- BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
- BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
- BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), \r
- BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
- BUS_TIMEOUT_OUT(2) => open,\r
- BUS_DATAREADY_IN(2) => slv_ack(2),\r
- BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
- BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
- BUS_UNKNOWN_ADDR_IN(2) => '0',\r
- -- OneWire master\r
- BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
- BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
- BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
- BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), \r
- BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
- BUS_TIMEOUT_OUT(3) => open,\r
- BUS_DATAREADY_IN(3) => slv_ack(3),\r
- BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
- BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
- BUS_UNKNOWN_ADDR_IN(3) => '0',\r
- -- SPI control registers\r
- BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
- BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
- BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
- BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), \r
- BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
- BUS_TIMEOUT_OUT(4) => open,\r
- BUS_DATAREADY_IN(4) => slv_ack(4),\r
- BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
- BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
- BUS_UNKNOWN_ADDR_IN(4) => '0',\r
- -- SPI data memory\r
- BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
- BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
- BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
- BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), \r
- BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
- BUS_TIMEOUT_OUT(5) => open,\r
- BUS_DATAREADY_IN(5) => slv_ack(5),\r
- BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
- BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
- BUS_UNKNOWN_ADDR_IN(5) => '0',\r
- -- ADC 0 SPI control registers\r
- BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
- BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
- BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
- BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), \r
- BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
- BUS_TIMEOUT_OUT(6) => open,\r
- BUS_DATAREADY_IN(6) => slv_ack(6),\r
- BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
- BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
- BUS_UNKNOWN_ADDR_IN(6) => '0',\r
- -- ADC 1 SPI control registers\r
- BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
- BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
- BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
- BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), \r
- BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
- BUS_TIMEOUT_OUT(7) => open,\r
- BUS_DATAREADY_IN(7) => slv_ack(7),\r
- BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
- BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
- BUS_UNKNOWN_ADDR_IN(7) => '0',\r
- -- APV control / status registers\r
- BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
- BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
- BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
- BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), \r
- BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
- BUS_TIMEOUT_OUT(8) => open,\r
- BUS_DATAREADY_IN(8) => slv_ack(8),\r
- BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
- BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
- BUS_UNKNOWN_ADDR_IN(8) => '0',\r
- -- ADC / PLL / trigger ctrl register\r
- BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
- BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
- BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
- BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), \r
- BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
- BUS_TIMEOUT_OUT(11 downto 9) => open,\r
- BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
- BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
- BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
- BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
- -- ADC0 snooper\r
- BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
- BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
- BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
- BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), \r
- BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
- BUS_TIMEOUT_OUT(12) => open,\r
- BUS_DATAREADY_IN(12) => slv_ack(12),\r
- BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
- BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
- BUS_UNKNOWN_ADDR_IN(12) => '0',\r
- -- ADC1 snooper\r
- BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
- BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
- BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
- BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), \r
- BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
- BUS_TIMEOUT_OUT(13) => open,\r
- BUS_DATAREADY_IN(13) => slv_ack(13),\r
- BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
- BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
- BUS_UNKNOWN_ADDR_IN(13) => '0',\r
- -- Test register\r
- BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
- BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
- BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
- BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), \r
- BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
- BUS_TIMEOUT_OUT(14) => open,\r
- BUS_DATAREADY_IN(14) => slv_ack(14),\r
- BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
- BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
- BUS_UNKNOWN_ADDR_IN(14) => '0',\r
- -- debug\r
- STAT_DEBUG => stat\r
- );\r
+generic map(\r
+ PORT_NUMBER => 15,\r
+ PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories\r
+ 1 => x"a800", -- threshold memories\r
+ 2 => x"8040", -- I2C master\r
+ 3 => x"c000", -- 1Wire master + memory\r
+ 4 => x"d000", -- SPI master\r
+ 5 => x"d100", -- SPI data memory\r
+ 6 => x"d010", -- ADC0 SPI\r
+ 7 => x"d020", -- ADC1 SPI\r
+ 8 => x"b000", -- APV control / status\r
+ 9 => x"b010", -- ADC level settings\r
+ 10 => x"b020", -- trigger settings\r
+ 11 => x"b030", -- PLL settings\r
+ 12 => x"f000", -- ADC 0 snooper\r
+ 13 => x"f800", -- ADC 1 snooper\r
+ 14 => x"8000", -- test register (busy)\r
+ others => x"0000"),\r
+ PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories\r
+ 1 => 11, -- threshold memories\r
+ 2 => 0, -- I2C master\r
+ 3 => 6, -- 1Wire master + memory\r
+ 4 => 1, -- SPI master\r
+ 5 => 6, -- SPI data memory\r
+ 6 => 0, -- ADC0 SPI\r
+ 7 => 0, -- ADC1 SPI\r
+ 8 => 4, -- APV control / status\r
+ 9 => 0, -- ADC level settings\r
+ 10 => 0, -- trigger settings\r
+ 11 => 0, -- PLL settings\r
+ 12 => 10, -- ADC 0 snooper\r
+ 13 => 10, -- ADC 1 snooper\r
+ 14 => 0, -- test register (normal)\r
+ others => 0)\r
+)\r
+port map(\r
+ CLK => clk_in,\r
+ RESET => reset_in,\r
+ DAT_ADDR_IN => regio_addr_in,\r
+ DAT_DATA_IN => regio_data_in,\r
+ DAT_DATA_OUT => regio_data_out,\r
+ DAT_READ_ENABLE_IN => regio_read_enable_in,\r
+ DAT_WRITE_ENABLE_IN => regio_write_enable_in,\r
+ DAT_TIMEOUT_IN => regio_timeout_in,\r
+ DAT_DATAREADY_OUT => regio_dataready_out,\r
+ DAT_WRITE_ACK_OUT => regio_write_ack_out,\r
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_out,\r
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out,\r
+ -- pedestal memories\r
+ BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
+ BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
+ BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
+ BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),\r
+ BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_DATAREADY_IN(0) => slv_ack(0),\r
+ BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
+ BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
+ BUS_UNKNOWN_ADDR_IN(0) => '0',\r
+ -- threshold memories\r
+ BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
+ BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
+ BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
+ BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),\r
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_DATAREADY_IN(1) => slv_ack(1),\r
+ BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
+ BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ -- I2C master\r
+ BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
+ BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
+ BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
+ BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),\r
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_DATAREADY_IN(2) => slv_ack(2),\r
+ BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
+ BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
+ BUS_UNKNOWN_ADDR_IN(2) => '0',\r
+ -- OneWire master\r
+ BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
+ BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
+ BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
+ BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),\r
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
+ BUS_TIMEOUT_OUT(3) => open,\r
+ BUS_DATAREADY_IN(3) => slv_ack(3),\r
+ BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
+ BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
+ BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+ -- SPI control registers\r
+ BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
+ BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
+ BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
+ BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),\r
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
+ BUS_TIMEOUT_OUT(4) => open,\r
+ BUS_DATAREADY_IN(4) => slv_ack(4),\r
+ BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
+ BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
+ BUS_UNKNOWN_ADDR_IN(4) => '0',\r
+ -- SPI data memory\r
+ BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
+ BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
+ BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
+ BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),\r
+ BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
+ BUS_TIMEOUT_OUT(5) => open,\r
+ BUS_DATAREADY_IN(5) => slv_ack(5),\r
+ BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
+ BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
+ BUS_UNKNOWN_ADDR_IN(5) => '0',\r
+ -- ADC 0 SPI control registers\r
+ BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
+ BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
+ BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
+ BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32),\r
+ BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
+ BUS_TIMEOUT_OUT(6) => open,\r
+ BUS_DATAREADY_IN(6) => slv_ack(6),\r
+ BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
+ BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
+ BUS_UNKNOWN_ADDR_IN(6) => '0',\r
+ -- ADC 1 SPI control registers\r
+ BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
+ BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
+ BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
+ BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32),\r
+ BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
+ BUS_TIMEOUT_OUT(7) => open,\r
+ BUS_DATAREADY_IN(7) => slv_ack(7),\r
+ BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
+ BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
+ BUS_UNKNOWN_ADDR_IN(7) => '0',\r
+ -- APV control / status registers\r
+ BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
+ BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
+ BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
+ BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32),\r
+ BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
+ BUS_TIMEOUT_OUT(8) => open,\r
+ BUS_DATAREADY_IN(8) => slv_ack(8),\r
+ BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
+ BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
+ BUS_UNKNOWN_ADDR_IN(8) => '0',\r
+ -- ADC / PLL / trigger ctrl register\r
+ BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
+ BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
+ BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
+ BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32),\r
+ BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
+ BUS_TIMEOUT_OUT(11 downto 9) => open,\r
+ BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
+ BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
+ -- ADC0 snooper\r
+ BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
+ BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
+ BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
+ BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32),\r
+ BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
+ BUS_TIMEOUT_OUT(12) => open,\r
+ BUS_DATAREADY_IN(12) => slv_ack(12),\r
+ BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
+ BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
+ BUS_UNKNOWN_ADDR_IN(12) => '0',\r
+ -- ADC1 snooper\r
+ BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
+ BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
+ BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
+ BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32),\r
+ BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
+ BUS_TIMEOUT_OUT(13) => open,\r
+ BUS_DATAREADY_IN(13) => slv_ack(13),\r
+ BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
+ BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
+ BUS_UNKNOWN_ADDR_IN(13) => '0',\r
+ -- Test register\r
+ BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
+ BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
+ BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
+ BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32),\r
+ BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
+ BUS_TIMEOUT_OUT(14) => open,\r
+ BUS_DATAREADY_IN(14) => slv_ack(14),\r
+ BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
+ BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
+ BUS_UNKNOWN_ADDR_IN(14) => '0',\r
+ -- debug\r
+ STAT_DEBUG => stat\r
+);\r
\r
\r
------------------------------------------------------------------------------------\r
-- pedestal memories (16x128 = 2048, 18bit)\r
------------------------------------------------------------------------------------\r
THE_PED_MEM: slv_ped_thr_mem\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16),\r
- SLV_READ_IN => slv_read(0),\r
- SLV_WRITE_IN => slv_write(0),\r
- SLV_ACK_OUT => slv_ack(0),\r
- SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),\r
- SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),\r
- -- backplane identifier\r
- BACKPLANE_IN => backplane_in,\r
- -- I/O to the backend\r
- MEM_CLK_IN => clk_in,\r
- MEM_ADDR_IN => ped_addr_in,\r
- MEM_0_D_OUT => ped_data_0_out,\r
- MEM_1_D_OUT => ped_data_1_out,\r
- MEM_2_D_OUT => ped_data_2_out,\r
- MEM_3_D_OUT => ped_data_3_out,\r
- MEM_4_D_OUT => ped_data_4_out,\r
- MEM_5_D_OUT => ped_data_5_out,\r
- MEM_6_D_OUT => ped_data_6_out,\r
- MEM_7_D_OUT => ped_data_7_out,\r
- MEM_8_D_OUT => ped_data_8_out,\r
- MEM_9_D_OUT => ped_data_9_out,\r
- MEM_10_D_OUT => ped_data_10_out,\r
- MEM_11_D_OUT => ped_data_11_out,\r
- MEM_12_D_OUT => ped_data_12_out,\r
- MEM_13_D_OUT => ped_data_13_out,\r
- MEM_14_D_OUT => ped_data_14_out,\r
- MEM_15_D_OUT => ped_data_15_out,\r
- -- Status lines\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16),\r
+ SLV_READ_IN => slv_read(0),\r
+ SLV_WRITE_IN => slv_write(0),\r
+ SLV_ACK_OUT => slv_ack(0),\r
+ SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),\r
+ SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => backplane_in,\r
+ -- I/O to the backend\r
+ MEM_CLK_IN => clk_in,\r
+ MEM_ADDR_IN => ped_addr_in,\r
+ MEM_0_D_OUT => ped_data_0_out,\r
+ MEM_1_D_OUT => ped_data_1_out,\r
+ MEM_2_D_OUT => ped_data_2_out,\r
+ MEM_3_D_OUT => ped_data_3_out,\r
+ MEM_4_D_OUT => ped_data_4_out,\r
+ MEM_5_D_OUT => ped_data_5_out,\r
+ MEM_6_D_OUT => ped_data_6_out,\r
+ MEM_7_D_OUT => ped_data_7_out,\r
+ MEM_8_D_OUT => ped_data_8_out,\r
+ MEM_9_D_OUT => ped_data_9_out,\r
+ MEM_10_D_OUT => ped_data_10_out,\r
+ MEM_11_D_OUT => ped_data_11_out,\r
+ MEM_12_D_OUT => ped_data_12_out,\r
+ MEM_13_D_OUT => ped_data_13_out,\r
+ MEM_14_D_OUT => ped_data_14_out,\r
+ MEM_15_D_OUT => ped_data_15_out,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(0) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- threshold memories (16x128 = 2048, 18bit)\r
------------------------------------------------------------------------------------\r
THE_THR_MEM: slv_ped_thr_mem\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16),\r
- SLV_READ_IN => slv_read(1),\r
- SLV_WRITE_IN => slv_write(1),\r
- SLV_ACK_OUT => slv_ack(1),\r
- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),\r
- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),\r
- -- backplane identifier\r
- BACKPLANE_IN => backplane_in,\r
- -- I/O to the backend\r
- MEM_CLK_IN => clk_in,\r
- MEM_ADDR_IN => thr_addr_in,\r
- MEM_0_D_OUT => thr_data_0_out,\r
- MEM_1_D_OUT => thr_data_1_out,\r
- MEM_2_D_OUT => thr_data_2_out,\r
- MEM_3_D_OUT => thr_data_3_out,\r
- MEM_4_D_OUT => thr_data_4_out,\r
- MEM_5_D_OUT => thr_data_5_out,\r
- MEM_6_D_OUT => thr_data_6_out,\r
- MEM_7_D_OUT => thr_data_7_out,\r
- MEM_8_D_OUT => thr_data_8_out,\r
- MEM_9_D_OUT => thr_data_9_out,\r
- MEM_10_D_OUT => thr_data_10_out,\r
- MEM_11_D_OUT => thr_data_11_out,\r
- MEM_12_D_OUT => thr_data_12_out,\r
- MEM_13_D_OUT => thr_data_13_out,\r
- MEM_14_D_OUT => thr_data_14_out,\r
- MEM_15_D_OUT => thr_data_15_out,\r
- -- Status lines\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16),\r
+ SLV_READ_IN => slv_read(1),\r
+ SLV_WRITE_IN => slv_write(1),\r
+ SLV_ACK_OUT => slv_ack(1),\r
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),\r
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => backplane_in,\r
+ -- I/O to the backend\r
+ MEM_CLK_IN => clk_in,\r
+ MEM_ADDR_IN => thr_addr_in,\r
+ MEM_0_D_OUT => thr_data_0_out,\r
+ MEM_1_D_OUT => thr_data_1_out,\r
+ MEM_2_D_OUT => thr_data_2_out,\r
+ MEM_3_D_OUT => thr_data_3_out,\r
+ MEM_4_D_OUT => thr_data_4_out,\r
+ MEM_5_D_OUT => thr_data_5_out,\r
+ MEM_6_D_OUT => thr_data_6_out,\r
+ MEM_7_D_OUT => thr_data_7_out,\r
+ MEM_8_D_OUT => thr_data_8_out,\r
+ MEM_9_D_OUT => thr_data_9_out,\r
+ MEM_10_D_OUT => thr_data_10_out,\r
+ MEM_11_D_OUT => thr_data_11_out,\r
+ MEM_12_D_OUT => thr_data_12_out,\r
+ MEM_13_D_OUT => thr_data_13_out,\r
+ MEM_14_D_OUT => thr_data_14_out,\r
+ MEM_15_D_OUT => thr_data_15_out,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(1) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- I2C master block for accessing APVs\r
------------------------------------------------------------------------------------\r
THE_I2C_MASTER: i2c_master\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(2),\r
- SLV_WRITE_IN => slv_write(2),\r
- SLV_BUSY_OUT => slv_busy(2),\r
- SLV_ACK_OUT => slv_ack(2),\r
- SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),\r
- SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),\r
- -- I2C connections\r
- SDA_IN => sda_in,\r
- SDA_OUT => sda_out,\r
- SCL_IN => scl_in,\r
- SCL_OUT => scl_out,\r
- -- Status lines\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(2),\r
+ SLV_WRITE_IN => slv_write(2),\r
+ SLV_BUSY_OUT => slv_busy(2),\r
+ SLV_ACK_OUT => slv_ack(2),\r
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),\r
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),\r
+ -- I2C connections\r
+ SDA_IN => sda_in,\r
+ SDA_OUT => sda_out,\r
+ SCL_IN => scl_in,\r
+ SCL_OUT => scl_out,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
\r
------------------------------------------------------------------------------------\r
-- 1Wire master including status memory\r
------------------------------------------------------------------------------------\r
THE_ONEWIRE_MEMORY: slv_onewire_memory\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16),\r
- SLV_READ_IN => slv_read(3),\r
- SLV_WRITE_IN => slv_write(3),\r
- SLV_ACK_OUT => slv_ack(3),\r
- SLV_BUSY_OUT => open, \r
- SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),\r
- -- backplane identifier\r
- BACKPLANE_IN => backplane_in,\r
- -- 1Wire lines\r
- ONEWIRE_START_IN => onewire_start_in, -- not used yet\r
- ONEWIRE_INOUT => onewire_inout,\r
- BP_ONEWIRE_INOUT => bp_onewire_inout,\r
- -- Status lines\r
- STAT => onewire_debug --open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16),\r
+ SLV_READ_IN => slv_read(3),\r
+ SLV_WRITE_IN => slv_write(3),\r
+ SLV_ACK_OUT => slv_ack(3),\r
+ SLV_BUSY_OUT => open,\r
+ SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => backplane_in,\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN => onewire_start_in, -- not used yet\r
+ ONEWIRE_INOUT => onewire_inout,\r
+ BP_ONEWIRE_INOUT => bp_onewire_inout,\r
+ -- Status lines\r
+ STAT => onewire_debug --open\r
+);\r
slv_busy(3) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- SPI master\r
------------------------------------------------------------------------------------\r
THE_SPI_MASTER: spi_master\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- BUS_READ_IN => slv_read(4),\r
- BUS_WRITE_IN => slv_write(4),\r
- BUS_BUSY_OUT => slv_busy(4),\r
- BUS_ACK_OUT => slv_ack(4),\r
- BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),\r
- BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),\r
- BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),\r
- -- SPI connections\r
- SPI_CS_OUT => spi_cs,\r
- SPI_SDI_IN => spi_sdi,\r
- SPI_SDO_OUT => spi_sdo,\r
- SPI_SCK_OUT => spi_sck,\r
- -- BRAM for read/write data\r
- BRAM_A_OUT => spi_bram_addr,\r
- BRAM_WR_D_IN => spi_bram_wr_d,\r
- BRAM_RD_D_OUT => spi_bram_rd_d,\r
- BRAM_WE_OUT => spi_bram_we,\r
- -- Status lines\r
- STAT => spi_debug --open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ BUS_READ_IN => slv_read(4),\r
+ BUS_WRITE_IN => slv_write(4),\r
+ BUS_BUSY_OUT => slv_busy(4),\r
+ BUS_ACK_OUT => slv_ack(4),\r
+ BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),\r
+ BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),\r
+ BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),\r
+ -- SPI connections\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_SDI_IN => spi_sdi,\r
+ SPI_SDO_OUT => spi_sdo,\r
+ SPI_SCK_OUT => spi_sck,\r
+ -- BRAM for read/write data\r
+ BRAM_A_OUT => spi_bram_addr,\r
+ BRAM_WR_D_IN => spi_bram_wr_d,\r
+ BRAM_RD_D_OUT => spi_bram_rd_d,\r
+ BRAM_WE_OUT => spi_bram_we,\r
+ -- Status lines\r
+ STAT => spi_debug --open\r
+);\r
\r
------------------------------------------------------------------------------------\r
-- data memory for SPI accesses\r
------------------------------------------------------------------------------------\r
THE_SPI_MEMORY: spi_databus_memory\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),\r
- BUS_READ_IN => slv_read(5),\r
- BUS_WRITE_IN => slv_write(5),\r
- BUS_ACK_OUT => slv_ack(5),\r
- BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),\r
- BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),\r
- -- state machine connections\r
- BRAM_ADDR_IN => spi_bram_addr,\r
- BRAM_WR_D_OUT => spi_bram_wr_d,\r
- BRAM_RD_D_IN => spi_bram_rd_d,\r
- BRAM_WE_IN => spi_bram_we, \r
- -- Status lines\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),\r
+ BUS_READ_IN => slv_read(5),\r
+ BUS_WRITE_IN => slv_write(5),\r
+ BUS_ACK_OUT => slv_ack(5),\r
+ BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),\r
+ BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),\r
+ -- state machine connections\r
+ BRAM_ADDR_IN => spi_bram_addr,\r
+ BRAM_WR_D_OUT => spi_bram_wr_d,\r
+ BRAM_RD_D_IN => spi_bram_rd_d,\r
+ BRAM_WE_IN => spi_bram_we,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(5) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- ADC0 SPI master\r
------------------------------------------------------------------------------------\r
THE_SPI_ADC0_MASTER: spi_adc_master\r
-generic map( RESET_VALUE_CTRL => x"60" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(6),\r
- SLV_WRITE_IN => slv_write(6),\r
- SLV_BUSY_OUT => slv_busy(6),\r
- SLV_ACK_OUT => slv_ack(6),\r
- SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),\r
- SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),\r
- -- SPI connections\r
- SPI_CS_OUT => spi_adc0_cs_out,\r
- SPI_SDO_OUT => spi_adc0_sdo_out,\r
- SPI_SCK_OUT => spi_adc0_sck_out,\r
- -- ADC connections\r
- ADC_LOCKED_IN => adc0_pll_locked_in,\r
- ADC_PD_OUT => adc0_pd_out,\r
- ADC_RST_OUT => adc0_rst_out,\r
- ADC_DEL_OUT => adc0_del_out,\r
- -- APV connections\r
- APV_RST_OUT => apv0_rst_out,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE_CTRL => x"60"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(6),\r
+ SLV_WRITE_IN => slv_write(6),\r
+ SLV_BUSY_OUT => slv_busy(6),\r
+ SLV_ACK_OUT => slv_ack(6),\r
+ SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),\r
+ SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),\r
+ -- SPI connections\r
+ SPI_CS_OUT => spi_adc0_cs_out,\r
+ SPI_SDO_OUT => spi_adc0_sdo_out,\r
+ SPI_SCK_OUT => spi_adc0_sck_out,\r
+ -- ADC connections\r
+ ADC_LOCKED_IN => adc0_pll_locked_in,\r
+ ADC_PD_OUT => adc0_pd_out,\r
+ ADC_RST_OUT => adc0_rst_out,\r
+ ADC_DEL_OUT => adc0_del_out,\r
+ -- APV connections\r
+ APV_RST_OUT => apv0_rst_out,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
\r
------------------------------------------------------------------------------------\r
-- ADC1 SPI master\r
------------------------------------------------------------------------------------\r
THE_SPI_ADC1_MASTER: spi_adc_master\r
-generic map( RESET_VALUE_CTRL => x"60" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(7),\r
- SLV_WRITE_IN => slv_write(7),\r
- SLV_BUSY_OUT => slv_busy(7),\r
- SLV_ACK_OUT => slv_ack(7),\r
- SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),\r
- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
- -- SPI connections\r
- SPI_CS_OUT => spi_adc1_cs_out,\r
- SPI_SDO_OUT => spi_adc1_sdo_out,\r
- SPI_SCK_OUT => spi_adc1_sck_out,\r
- -- ADC connections\r
- ADC_LOCKED_IN => adc1_pll_locked_in,\r
- ADC_PD_OUT => adc1_pd_out,\r
- ADC_RST_OUT => adc1_rst_out,\r
- ADC_DEL_OUT => adc1_del_out,\r
- -- APV connections\r
- APV_RST_OUT => apv1_rst_out,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE_CTRL => x"60"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(7),\r
+ SLV_WRITE_IN => slv_write(7),\r
+ SLV_BUSY_OUT => slv_busy(7),\r
+ SLV_ACK_OUT => slv_ack(7),\r
+ SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),\r
+ SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
+ -- SPI connections\r
+ SPI_CS_OUT => spi_adc1_cs_out,\r
+ SPI_SDO_OUT => spi_adc1_sdo_out,\r
+ SPI_SCK_OUT => spi_adc1_sck_out,\r
+ -- ADC connections\r
+ ADC_LOCKED_IN => adc1_pll_locked_in,\r
+ ADC_PD_OUT => adc1_pd_out,\r
+ ADC_RST_OUT => adc1_rst_out,\r
+ ADC_DEL_OUT => adc1_del_out,\r
+ -- APV connections\r
+ APV_RST_OUT => apv1_rst_out,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
\r
------------------------------------------------------------------------------------\r
-- APV control / status registers\r
------------------------------------------------------------------------------------\r
THE_SLV_REGISTER_BANK: slv_register_bank\r
-generic map( RESET_VALUE => x"0001" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16),\r
- SLV_READ_IN => slv_read(8),\r
- SLV_WRITE_IN => slv_write(8),\r
- SLV_ACK_OUT => slv_ack(8),\r
- SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),\r
- SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),\r
- -- I/O to the backend\r
- BACKPLANE_IN => backplane_in,\r
- CTRL_0_OUT => ctrl_0_out,\r
- CTRL_1_OUT => ctrl_1_out,\r
- CTRL_2_OUT => ctrl_2_out,\r
- CTRL_3_OUT => ctrl_3_out,\r
- CTRL_4_OUT => ctrl_4_out,\r
- CTRL_5_OUT => ctrl_5_out,\r
- CTRL_6_OUT => ctrl_6_out,\r
- CTRL_7_OUT => ctrl_7_out,\r
- CTRL_8_OUT => ctrl_8_out,\r
- CTRL_9_OUT => ctrl_9_out,\r
- CTRL_10_OUT => ctrl_10_out,\r
- CTRL_11_OUT => ctrl_11_out,\r
- CTRL_12_OUT => ctrl_12_out,\r
- CTRL_13_OUT => ctrl_13_out,\r
- CTRL_14_OUT => ctrl_14_out,\r
- CTRL_15_OUT => ctrl_15_out,\r
- STAT_0_IN => stat_0_in,\r
- STAT_1_IN => stat_1_in,\r
- STAT_2_IN => stat_2_in,\r
- STAT_3_IN => stat_3_in,\r
- STAT_4_IN => stat_4_in,\r
- STAT_5_IN => stat_5_in,\r
- STAT_6_IN => stat_6_in,\r
- STAT_7_IN => stat_7_in,\r
- STAT_8_IN => stat_8_in,\r
- STAT_9_IN => stat_9_in,\r
- STAT_10_IN => stat_10_in,\r
- STAT_11_IN => stat_11_in,\r
- STAT_12_IN => stat_12_in,\r
- STAT_13_IN => stat_13_in,\r
- STAT_14_IN => stat_14_in,\r
- STAT_15_IN => stat_15_in,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE => x"0001"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16),\r
+ SLV_READ_IN => slv_read(8),\r
+ SLV_WRITE_IN => slv_write(8),\r
+ SLV_ACK_OUT => slv_ack(8),\r
+ SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),\r
+ SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),\r
+ -- I/O to the backend\r
+ BACKPLANE_IN => backplane_in,\r
+ CTRL_0_OUT => ctrl_0_out,\r
+ CTRL_1_OUT => ctrl_1_out,\r
+ CTRL_2_OUT => ctrl_2_out,\r
+ CTRL_3_OUT => ctrl_3_out,\r
+ CTRL_4_OUT => ctrl_4_out,\r
+ CTRL_5_OUT => ctrl_5_out,\r
+ CTRL_6_OUT => ctrl_6_out,\r
+ CTRL_7_OUT => ctrl_7_out,\r
+ CTRL_8_OUT => ctrl_8_out,\r
+ CTRL_9_OUT => ctrl_9_out,\r
+ CTRL_10_OUT => ctrl_10_out,\r
+ CTRL_11_OUT => ctrl_11_out,\r
+ CTRL_12_OUT => ctrl_12_out,\r
+ CTRL_13_OUT => ctrl_13_out,\r
+ CTRL_14_OUT => ctrl_14_out,\r
+ CTRL_15_OUT => ctrl_15_out,\r
+ STAT_0_IN => stat_0_in,\r
+ STAT_1_IN => stat_1_in,\r
+ STAT_2_IN => stat_2_in,\r
+ STAT_3_IN => stat_3_in,\r
+ STAT_4_IN => stat_4_in,\r
+ STAT_5_IN => stat_5_in,\r
+ STAT_6_IN => stat_6_in,\r
+ STAT_7_IN => stat_7_in,\r
+ STAT_8_IN => stat_8_in,\r
+ STAT_9_IN => stat_9_in,\r
+ STAT_10_IN => stat_10_in,\r
+ STAT_11_IN => stat_11_in,\r
+ STAT_12_IN => stat_12_in,\r
+ STAT_13_IN => stat_13_in,\r
+ STAT_14_IN => stat_14_in,\r
+ STAT_15_IN => stat_15_in,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(8) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- ADC level register\r
------------------------------------------------------------------------------------\r
THE_ADC_LVL_REG: slv_register\r
-generic map( RESET_VALUE => x"d0_20_78_88" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
- BUSY_IN => '0',\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(9),\r
- SLV_WRITE_IN => slv_write(9),\r
- SLV_BUSY_OUT => slv_busy(9),\r
- SLV_ACK_OUT => slv_ack(9),\r
- SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),\r
- SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),\r
- -- I/O to the backend\r
- REG_DATA_IN => ctrl_lvl,\r
- REG_DATA_OUT => ctrl_lvl,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE => x"d0_20_78_88"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(9),\r
+ SLV_WRITE_IN => slv_write(9),\r
+ SLV_BUSY_OUT => slv_busy(9),\r
+ SLV_ACK_OUT => slv_ack(9),\r
+ SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),\r
+ SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),\r
+ -- I/O to the backend\r
+ REG_DATA_IN => ctrl_lvl,\r
+ REG_DATA_OUT => ctrl_lvl,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
\r
------------------------------------------------------------------------------------\r
-- trigger control register\r
------------------------------------------------------------------------------------\r
THE_TRG_CTRL_REG: slv_register\r
-generic map( RESET_VALUE => x"10_10_10_10" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
- BUSY_IN => '0',\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(10),\r
- SLV_WRITE_IN => slv_write(10),\r
- SLV_BUSY_OUT => slv_busy(10),\r
- SLV_ACK_OUT => slv_ack(10),\r
- SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32),\r
- SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),\r
- -- I/O to the backend\r
- REG_DATA_IN => ctrl_trg,\r
- REG_DATA_OUT => ctrl_trg,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE => x"10_10_10_10"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(10),\r
+ SLV_WRITE_IN => slv_write(10),\r
+ SLV_BUSY_OUT => slv_busy(10),\r
+ SLV_ACK_OUT => slv_ack(10),\r
+ SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32),\r
+ SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),\r
+ -- I/O to the backend\r
+ REG_DATA_IN => ctrl_trg,\r
+ REG_DATA_OUT => ctrl_trg,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
\r
------------------------------------------------------------------------------------\r
-- PLL control register\r
------------------------------------------------------------------------------------\r
THE_PLL_CTRL_REG: slv_half_register\r
-generic map( RESET_VALUE => x"00_02" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(11),\r
- SLV_WRITE_IN => slv_write(11),\r
- SLV_ACK_OUT => slv_ack(11),\r
- SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),\r
- SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),\r
- -- I/O to the backend\r
- STATUS_REG_IN => status_pll_in,\r
- CTRL_REG_OUT => ctrl_pll,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE => x"00_02"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(11),\r
+ SLV_WRITE_IN => slv_write(11),\r
+ SLV_ACK_OUT => slv_ack(11),\r
+ SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),\r
+ SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),\r
+ -- I/O to the backend\r
+ STATUS_REG_IN => status_pll_in,\r
+ CTRL_REG_OUT => ctrl_pll,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(11) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- ADC0 snooper\r
------------------------------------------------------------------------------------\r
THE_ADC0_SNOOPER: slv_adc_snoop\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16),\r
- SLV_READ_IN => slv_read(12),\r
- SLV_WRITE_IN => slv_write(12),\r
- SLV_ACK_OUT => slv_ack(12),\r
- SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32),\r
- SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32),\r
- -- I/O to the backend\r
- ADC_SEL_OUT => adc0_sel_out,\r
- ADC_CLK_IN => adc0_clk_in,\r
- ADC_DATA_IN => adc0_data_in,\r
- -- Status lines\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16),\r
+ SLV_READ_IN => slv_read(12),\r
+ SLV_WRITE_IN => slv_write(12),\r
+ SLV_ACK_OUT => slv_ack(12),\r
+ SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32),\r
+ SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32),\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT => adc0_sel_out,\r
+ ADC_CLK_IN => adc0_clk_in,\r
+ ADC_DATA_IN => adc0_data_in,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(12) <= '0';\r
\r
\r
-- ADC1 snooper\r
------------------------------------------------------------------------------------\r
THE_ADC1_SNOOPER: slv_adc_snoop\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16),\r
- SLV_READ_IN => slv_read(13),\r
- SLV_WRITE_IN => slv_write(13),\r
- SLV_ACK_OUT => slv_ack(13),\r
- SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32),\r
- SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32),\r
- -- I/O to the backend\r
- ADC_SEL_OUT => adc1_sel_out,\r
- ADC_CLK_IN => adc1_clk_in,\r
- ADC_DATA_IN => adc1_data_in,\r
- -- Status lines\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16),\r
+ SLV_READ_IN => slv_read(13),\r
+ SLV_WRITE_IN => slv_write(13),\r
+ SLV_ACK_OUT => slv_ack(13),\r
+ SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32),\r
+ SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32),\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT => adc1_sel_out,\r
+ ADC_CLK_IN => adc1_clk_in,\r
+ ADC_DATA_IN => adc1_data_in,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
slv_busy(13) <= '0';\r
\r
- \r
+\r
------------------------------------------------------------------------------------\r
-- test register (normal)\r
------------------------------------------------------------------------------------\r
THE_GOOD_TEST_REG: slv_register\r
-generic map( RESET_VALUE => x"dead_beef" )\r
-port map( CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
- BUSY_IN => '0',\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(14),\r
- SLV_WRITE_IN => slv_write(14),\r
- SLV_BUSY_OUT => slv_busy(14),\r
- SLV_ACK_OUT => slv_ack(14),\r
- SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32),\r
- SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32),\r
- -- I/O to the backend\r
- REG_DATA_IN => test_reg_in, --x"5a3c_87e1",\r
- REG_DATA_OUT => test_reg_out,\r
- -- Status lines\r
- STAT => open\r
- );\r
+generic map(\r
+ RESET_VALUE => x"dead_beef"\r
+)\r
+port map(\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(14),\r
+ SLV_WRITE_IN => slv_write(14),\r
+ SLV_BUSY_OUT => slv_busy(14),\r
+ SLV_ACK_OUT => slv_ack(14),\r
+ SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32),\r
+ SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32),\r
+ -- I/O to the backend\r
+ REG_DATA_IN => test_reg_in, --x"5a3c_87e1",\r
+ REG_DATA_OUT => test_reg_out,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
\r
\r
\r
\r
\r
entity slv_adc_la is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
- ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
- ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_adc_la is\r
\r
-- Signals\r
+type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- slave bus signals\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
+\r
+signal arm_x : std_logic;\r
+signal trg_x : std_logic;\r
+\r
+signal ctrl_reg : std_logic_vector(15 downto 0);\r
+signal status_reg : std_logic_vector(31 downto 0);\r
+\r
+signal rd_data : std_logic_vector(15 downto 0);\r
+\r
+-- 40MHz clock domain!!!\r
+signal wr_data : std_logic_vector(15 downto 0);\r
+signal wr_addr : std_logic_vector(9 downto 0);\r
+signal wr_we : std_logic;\r
+signal reset_40mhz : std_logic;\r
+signal arm_40mhz : std_logic;\r
+signal trg_40mhz : std_logic;\r
+\r
+signal sm_clear : std_logic;\r
+signal sm_run : std_logic;\r
+signal sm_sample : std_logic;\r
+signal sm_ready : std_logic;\r
+signal sm_last : std_logic;\r
+signal sm_bsm : std_logic_vector(3 downto 0);\r
\r
- type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- slave bus signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal arm_x : std_logic;\r
- signal trg_x : std_logic;\r
-\r
- signal ctrl_reg : std_logic_vector(15 downto 0);\r
- signal status_reg : std_logic_vector(31 downto 0);\r
-\r
- signal rd_data : std_logic_vector(15 downto 0);\r
-\r
- -- 40MHz clock domain!!!\r
- signal wr_data : std_logic_vector(15 downto 0);\r
- signal wr_addr : std_logic_vector(9 downto 0);\r
- signal wr_we : std_logic;\r
- signal reset_40mhz : std_logic;\r
- signal arm_40mhz : std_logic;\r
- signal trg_40mhz : std_logic;\r
-\r
- signal sm_clear : std_logic;\r
- signal sm_run : std_logic;\r
- signal sm_sample : std_logic;\r
- signal sm_ready : std_logic;\r
- signal sm_last : std_logic;\r
- signal sm_bsm : std_logic_vector(3 downto 0);\r
- \r
begin\r
\r
-- Fake\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( slv_read_in = '1' ) then\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
NEXT_STATE <= RD_DEL0;\r
store_rd_x <= '1';\r
elsif( slv_write_in = '1' ) then\r
NEXT_STATE <= WR_DEL0;\r
store_wr_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
- when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
- when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
---------------------------------------------------------\r
\r
THE_RST_SYNC: state_sync\r
-port map( STATE_A_IN => reset_in,\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => reset_40mhz\r
- );\r
+port map(\r
+ STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset_40mhz\r
+);\r
\r
arm_x <= slv_data_in(30) and store_wr;\r
\r
THE_ARM_PULSE_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => arm_x,\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset_40mhz,\r
- PULSE_B_OUT => arm_40mhz\r
- );\r
+port map(\r
+ CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => arm_x,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset_40mhz,\r
+ PULSE_B_OUT => arm_40mhz\r
+);\r
\r
trg_x <= slv_data_in(31) and store_wr;\r
\r
THE_TRG_PULSE_SYNC: pulse_sync\r
-port map( CLK_A_IN => clk_in,\r
- RESET_A_IN => reset_in,\r
- PULSE_A_IN => trg_x,\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset_40mhz,\r
- PULSE_B_OUT => trg_40mhz\r
- );\r
+port map(\r
+ CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => trg_x,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset_40mhz,\r
+ PULSE_B_OUT => trg_40mhz\r
+);\r
\r
THE_LOGIC_ANALYZER: logic_analyzer\r
-port map( CLK_IN => adc_clk_in,\r
- RESET_IN => reset_40mhz,\r
- -- control signals\r
- ARM_IN => arm_40mhz, -- BUGBUGBUG\r
- TRG_IN => trg_40mhz, -- BUGBUGBUG\r
- MAX_SAMPLE_IN => ctrl_reg(9 downto 0),\r
- -- status signals\r
- SM_ADDR_OUT => wr_addr,\r
- SM_CE_OUT => open,\r
- SM_WE_OUT => wr_we,\r
- CLEAR_OUT => sm_clear,\r
- RUN_OUT => sm_run,\r
- SAMPLE_OUT => sm_sample,\r
- READY_OUT => sm_ready,\r
- LAST_OUT => sm_last,\r
- -- Status lines\r
- BSM_OUT => sm_bsm,\r
- STAT => open\r
- );\r
+port map(\r
+ CLK_IN => adc_clk_in,\r
+ RESET_IN => reset_40mhz,\r
+ -- control signals\r
+ ARM_IN => arm_40mhz, -- BUGBUGBUG\r
+ TRG_IN => trg_40mhz, -- BUGBUGBUG\r
+ MAX_SAMPLE_IN => ctrl_reg(9 downto 0),\r
+ -- status signals\r
+ SM_ADDR_OUT => wr_addr,\r
+ SM_CE_OUT => open,\r
+ SM_WE_OUT => wr_we,\r
+ CLEAR_OUT => sm_clear,\r
+ RUN_OUT => sm_run,\r
+ SAMPLE_OUT => sm_sample,\r
+ READY_OUT => sm_ready,\r
+ LAST_OUT => sm_last,\r
+ -- Status lines\r
+ BSM_OUT => sm_bsm,\r
+ STAT => open\r
+);\r
\r
wr_data(15) <= sm_clear;\r
wr_data(14) <= sm_run;\r
wr_data(11 downto 0) <= adc_data_in;\r
\r
THE_ADC0_SNOOP_MEM: adc_snoop_mem\r
-port map( WRADDRESS => wr_addr,\r
- DATA => wr_data,\r
- WE => wr_we,\r
- WRCLOCK => adc_clk_in,\r
- WRCLOCKEN => '1',\r
- RDADDRESS => slv_addr_in, \r
- RDCLOCK => clk_in,\r
- RDCLOCKEN => '1',\r
- RESET => reset_in,\r
- Q => rd_data\r
- );\r
+port map(\r
+ WRADDRESS => wr_addr,\r
+ DATA => wr_data,\r
+ WE => wr_we,\r
+ WRCLOCK => adc_clk_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => slv_addr_in,\r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => rd_data\r
+);\r
\r
-- register write\r
THE_WRITE_REG_PROC: process( clk_in )\r
\r
\r
entity slv_adc_snoop is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
- ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
- ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_adc_snoop is\r
\r
-- Signals\r
+type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+-- slave bus signals\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
\r
- -- slave bus signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
+signal ctrl_reg : std_logic_vector(15 downto 0);\r
+signal status_reg : std_logic_vector(31 downto 0);\r
\r
- signal ctrl_reg : std_logic_vector(15 downto 0);\r
- signal status_reg : std_logic_vector(31 downto 0);\r
+signal rd_data : std_logic_vector(15 downto 0);\r
\r
- signal rd_data : std_logic_vector(15 downto 0);\r
-\r
- -- 40MHz clock domain!!!\r
- signal wr_data : std_logic_vector(15 downto 0);\r
- signal wr_ctr : std_logic_vector(9 downto 0);\r
- signal rst_wr_ctr : std_logic;\r
- signal ce_wr_ctr : std_logic;\r
- signal reset : std_logic;\r
+-- 40MHz clock domain!!!\r
+signal wr_data : std_logic_vector(15 downto 0);\r
+signal wr_ctr : std_logic_vector(9 downto 0);\r
+signal rst_wr_ctr : std_logic;\r
+signal ce_wr_ctr : std_logic;\r
+signal reset : std_logic;\r
\r
begin\r
\r
stat(17) <= rst_wr_ctr;\r
stat(16) <= ce_wr_ctr;\r
stat(15 downto 0) <= ctrl_reg;\r
- \r
+\r
---------------------------------------------------------\r
-- Statemachine --\r
---------------------------------------------------------\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( slv_read_in = '1' ) then\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
NEXT_STATE <= RD_DEL0;\r
store_rd_x <= '1';\r
elsif( slv_write_in = '1' ) then\r
NEXT_STATE <= WR_DEL0;\r
store_wr_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
- when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
- when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
---------------------------------------------------------\r
\r
THE_RESET_SYNC: state_sync\r
-port map( STATE_A_IN => reset_in,\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => '0',\r
- STATE_B_OUT => reset\r
- );\r
+port map(\r
+ STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+);\r
\r
THE_RST_SYNC: state_sync\r
-port map( STATE_A_IN => ctrl_reg(15),\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset,\r
- STATE_B_OUT => rst_wr_ctr\r
- );\r
+port map(\r
+ STATE_A_IN => ctrl_reg(15),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => rst_wr_ctr\r
+);\r
\r
THE_CE_SYNC: state_sync\r
-port map( STATE_A_IN => ctrl_reg(14),\r
- CLK_B_IN => adc_clk_in,\r
- RESET_B_IN => reset,\r
- STATE_B_OUT => ce_wr_ctr\r
- );\r
+port map(\r
+ STATE_A_IN => ctrl_reg(14),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => ce_wr_ctr\r
+);\r
\r
THE_WR_CTR_PROC: process( adc_clk_in )\r
begin\r
wr_data <= x"0" & adc_data_in;\r
\r
THE_ADC0_SNOOP_MEM: adc_snoop_mem\r
-port map( WRADDRESS => wr_ctr,\r
- DATA => wr_data,\r
- WE => ce_wr_ctr,\r
- WRCLOCK => adc_clk_in,\r
- WRCLOCKEN => '1',\r
- RDADDRESS => slv_addr_in, \r
- RDCLOCK => clk_in,\r
- RDCLOCKEN => '1',\r
- RESET => reset_in,\r
- Q => rd_data\r
- );\r
+port map(\r
+ WRADDRESS => wr_ctr,\r
+ DATA => wr_data,\r
+ WE => ce_wr_ctr,\r
+ WRCLOCK => adc_clk_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => slv_addr_in,\r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => rd_data\r
+);\r
\r
-- register write\r
THE_WRITE_REG_PROC: process( clk_in )\r
\r
\r
entity slv_half_register is\r
-generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" );\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
- CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+generic(\r
+ RESET_VALUE : std_logic_vector(15 downto 0) := x"0000"\r
+);\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
+ CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_half_register is\r
\r
-- Signals\r
+type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+-- slave bus signals\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
\r
- -- slave bus signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
+signal ctrl_reg : std_logic_vector(15 downto 0);\r
\r
- signal ctrl_reg : std_logic_vector(15 downto 0);\r
-\r
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
\r
begin\r
\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( slv_read_in = '1' ) then\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
NEXT_STATE <= RD_RDY;\r
store_rd_x <= '1';\r
elsif( slv_write_in = '1' ) then\r
NEXT_STATE <= WR_RDY;\r
store_wr_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
use work.adcmv3_components.all;\r
\r
entity slv_onewire_memory is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- backplane identifier\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- -- 1Wire lines\r
- ONEWIRE_START_IN : in std_logic;\r
- ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
- BP_ONEWIRE_INOUT : inout std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_onewire_memory is\r
\r
-- Signals\r
- type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- slave bus signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal slv_busy : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- -- for replacing the lost FE with BP data\r
- signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked\r
- signal wr_data_q : std_logic_vector(15 downto 0);\r
- signal wr_we_q : std_logic;\r
-\r
- signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked\r
- signal wr_bp_data : std_logic_vector(15 downto 0);\r
- signal wr_data : std_logic_vector(15 downto 0);\r
- signal wr_we : std_logic;\r
- signal buf_slv_data_out : std_logic_vector(31 downto 0);\r
-\r
- signal read_address : std_logic_vector(5 downto 0);\r
- signal missing_one : std_logic_vector(3 downto 0); -- missing APV FE <-> backplane\r
- signal overlay : std_logic;\r
-\r
- signal onewire_bsm : std_logic_vector(7 downto 0);\r
+type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- slave bus signals\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal slv_busy : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
+\r
+-- for replacing the lost FE with BP data\r
+signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked\r
+signal wr_data_q : std_logic_vector(15 downto 0);\r
+signal wr_we_q : std_logic;\r
+signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked\r
+signal wr_bp_data : std_logic_vector(15 downto 0);\r
+signal wr_data : std_logic_vector(15 downto 0);\r
+signal wr_we : std_logic;\r
+signal buf_slv_data_out : std_logic_vector(31 downto 0);\r
+\r
+signal read_address : std_logic_vector(5 downto 0);\r
+signal missing_one : std_logic_vector(3 downto 0); -- missing APV FE <-> backplane\r
+signal overlay : std_logic;\r
+\r
+signal onewire_bsm : std_logic_vector(7 downto 0);\r
\r
begin\r
\r
\r
-- Remap the 1Wire chips to Luigi's world\r
THE_ADC_ONEWIRE_MAP_MEM: adc_onewire_map_mem\r
-port map( ADDRESS(6 downto 4) => backplane_in,\r
- ADDRESS(3 downto 0) => slv_addr_in(5 downto 2),\r
- Q => read_address(5 downto 2)\r
- );\r
+port map(\r
+ ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in(5 downto 2),\r
+ Q => read_address(5 downto 2)\r
+);\r
read_address(1 downto 0) <= slv_addr_in(1 downto 0);\r
\r
--- One APV FE connector is missing ("Roman's FE"), and replace the \r
+-- One APV FE connector is missing ("Roman's FE"), and replace the\r
-- 1Wire ID by the backplane\r
THE_ONEWIRE_SPARE_ONE: onewire_spare_one\r
-port map( ADDRESS => backplane_in,\r
- Q => missing_one\r
- );\r
+port map(\r
+ ADDRESS => backplane_in,\r
+ Q => missing_one\r
+);\r
\r
-- Check if we need to replace data\r
overlay <= '1' when (wr_addr(6 downto 3) = missing_one) else '0';\r
\r
-\r
---------------------------------------------------------\r
-- Statemachine --\r
---------------------------------------------------------\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( (slv_read_in = '1') ) then\r
+ when SLEEP => if ( (slv_read_in = '1') ) then\r
NEXT_STATE <= RD_RDY;\r
store_rd_x <= '1';\r
elsif( (slv_write_in = '1') ) then\r
NEXT_STATE <= WR_RDY;\r
store_wr_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
-- 1 Wire master --\r
---------------------------------------------------------\r
THE_ONEWIRE_MASTER: onewire_master\r
-generic map( CLK_PERIOD => 10 )\r
-port map( CLK => clk_in,\r
- RESET => reset_in,\r
- READOUT_ENABLE_IN => store_wr,\r
- -- connection to 1-wire interface (16 APV FEs)\r
- ONEWIRE => onewire_inout,\r
- BP_ONEWIRE => bp_onewire_inout,\r
- -- connection to external DPRAM for slow control readout\r
- BP_DATA_OUT => wr_bp_data, \r
- DATA_OUT => wr_data,\r
- ADDR_OUT => wr_addr,\r
- WRITE_OUT => wr_we,\r
- BUSY_OUT => slv_busy, -- could be used...\r
- -- debug\r
- BSM_OUT => onewire_bsm,\r
- STAT => open\r
- );\r
+generic map( CLK_PERIOD => 10 )\r
+port map(\r
+ CLK => clk_in,\r
+ RESET => reset_in,\r
+ READOUT_ENABLE_IN => store_wr,\r
+ -- connection to 1-wire interface (16 APV FEs)\r
+ ONEWIRE => onewire_inout,\r
+ BP_ONEWIRE => bp_onewire_inout,\r
+ -- connection to external DPRAM for slow control readout\r
+ BP_DATA_OUT => wr_bp_data,\r
+ DATA_OUT => wr_data,\r
+ ADDR_OUT => wr_addr,\r
+ WRITE_OUT => wr_we,\r
+ BUSY_OUT => slv_busy, -- could be used...\r
+ -- debug\r
+ BSM_OUT => onewire_bsm,\r
+ STAT => open\r
+);\r
\r
---------------------------------------------------------\r
-- data replacing --\r
-- data handling --\r
---------------------------------------------------------\r
THE_SLV_ONEWIRE_DPRAM: slv_onewire_dpram\r
-port map( WRADDRESS => wr_addr_q,\r
- RDADDRESS => read_address,\r
- DATA => wr_data_q,\r
- WE => wr_we_q,\r
- RDCLOCK => clk_in,\r
- RDCLOCKEN => '1',\r
- RESET => reset_in,\r
- WRCLOCK => clk_in,\r
- WRCLOCKEN => '1',\r
- Q => buf_slv_data_out\r
- );\r
+port map(\r
+ WRADDRESS => wr_addr_q,\r
+ RDADDRESS => read_address,\r
+ DATA => wr_data_q,\r
+ WE => wr_we_q,\r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ WRCLOCK => clk_in,\r
+ WRCLOCKEN => '1',\r
+ Q => buf_slv_data_out\r
+);\r
\r
\r
\r
use work.adcmv3_components.all;\r
\r
entity slv_ped_thr_mem is\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- backplane identifier\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- -- I/O to the backend\r
- MEM_CLK_IN : in std_logic;\r
- MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
- MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_ped_thr_mem is\r
\r
-- Signals\r
- type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
+type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- statemachine signals\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
\r
- -- statemachine signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
+signal block_addr : std_logic_vector(3 downto 0);\r
\r
- signal block_addr : std_logic_vector(3 downto 0);\r
+type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal ped_data : ped_data_t;\r
+signal mem_data : ped_data_t;\r
\r
- type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
- signal ped_data : ped_data_t;\r
- signal mem_data : ped_data_t;\r
+signal mem_wr_x : std_logic_vector(15 downto 0);\r
+signal mem_wr : std_logic_vector(15 downto 0);\r
+signal mem_sel : std_logic_vector(15 downto 0);\r
\r
- signal mem_wr_x : std_logic_vector(15 downto 0);\r
- signal mem_wr : std_logic_vector(15 downto 0);\r
- signal mem_sel : std_logic_vector(15 downto 0);\r
+signal rdback_data : std_logic_vector(17 downto 0);\r
\r
- signal rdback_data : std_logic_vector(17 downto 0);\r
- \r
begin\r
\r
---------------------------------------------------------\r
-- Mapping of backplanes --\r
---------------------------------------------------------\r
THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
-port map( ADDRESS(6 downto 4) => backplane_in,\r
- ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
- Q => block_addr\r
- );\r
+port map(\r
+ ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
+ Q => block_addr\r
+);\r
\r
THE_MEM_SEL_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
case block_addr is\r
- when x"0" => mem_sel <= b"0000_0000_0000_0001";\r
+ when x"0" => mem_sel <= b"0000_0000_0000_0001";\r
rdback_data <= mem_data(0);\r
- when x"1" => mem_sel <= b"0000_0000_0000_0010";\r
+ when x"1" => mem_sel <= b"0000_0000_0000_0010";\r
rdback_data <= mem_data(1);\r
- when x"2" => mem_sel <= b"0000_0000_0000_0100";\r
+ when x"2" => mem_sel <= b"0000_0000_0000_0100";\r
rdback_data <= mem_data(2);\r
- when x"3" => mem_sel <= b"0000_0000_0000_1000";\r
+ when x"3" => mem_sel <= b"0000_0000_0000_1000";\r
rdback_data <= mem_data(3);\r
- when x"4" => mem_sel <= b"0000_0000_0001_0000";\r
+ when x"4" => mem_sel <= b"0000_0000_0001_0000";\r
rdback_data <= mem_data(4);\r
- when x"5" => mem_sel <= b"0000_0000_0010_0000";\r
+ when x"5" => mem_sel <= b"0000_0000_0010_0000";\r
rdback_data <= mem_data(5);\r
- when x"6" => mem_sel <= b"0000_0000_0100_0000";\r
+ when x"6" => mem_sel <= b"0000_0000_0100_0000";\r
rdback_data <= mem_data(6);\r
- when x"7" => mem_sel <= b"0000_0000_1000_0000";\r
+ when x"7" => mem_sel <= b"0000_0000_1000_0000";\r
rdback_data <= mem_data(7);\r
- when x"8" => mem_sel <= b"0000_0001_0000_0000";\r
+ when x"8" => mem_sel <= b"0000_0001_0000_0000";\r
rdback_data <= mem_data(8);\r
- when x"9" => mem_sel <= b"0000_0010_0000_0000";\r
+ when x"9" => mem_sel <= b"0000_0010_0000_0000";\r
rdback_data <= mem_data(9);\r
- when x"a" => mem_sel <= b"0000_0100_0000_0000";\r
+ when x"a" => mem_sel <= b"0000_0100_0000_0000";\r
rdback_data <= mem_data(10);\r
- when x"b" => mem_sel <= b"0000_1000_0000_0000";\r
+ when x"b" => mem_sel <= b"0000_1000_0000_0000";\r
rdback_data <= mem_data(11);\r
- when x"c" => mem_sel <= b"0001_0000_0000_0000";\r
+ when x"c" => mem_sel <= b"0001_0000_0000_0000";\r
rdback_data <= mem_data(12);\r
- when x"d" => mem_sel <= b"0010_0000_0000_0000";\r
+ when x"d" => mem_sel <= b"0010_0000_0000_0000";\r
rdback_data <= mem_data(13);\r
- when x"e" => mem_sel <= b"0100_0000_0000_0000";\r
+ when x"e" => mem_sel <= b"0100_0000_0000_0000";\r
rdback_data <= mem_data(14);\r
- when x"f" => mem_sel <= b"1000_0000_0000_0000";\r
+ when x"f" => mem_sel <= b"1000_0000_0000_0000";\r
rdback_data <= mem_data(15);\r
- when others => mem_sel <= b"0000_0000_0000_0000"; -- never used\r
+ when others => mem_sel <= b"0000_0000_0000_0000"; -- never used\r
rdback_data <= (others => '0');\r
end case;\r
end if;\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( slv_read_in = '1' ) then\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
NEXT_STATE <= RD_DEL0;\r
store_rd_x <= '1';\r
elsif( slv_write_in = '1' ) then\r
NEXT_STATE <= WR_DEL0;\r
store_wr_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
- when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
- when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
---------------------------------------------------------\r
-- block memories --\r
---------------------------------------------------------\r
-GEN_PED_MEM: for i in 0 to 15 generate \r
+GEN_PED_MEM: for i in 0 to 15 generate\r
-- Port A: SLV_BUS\r
-- Port B: state machine\r
- THE_PED_MEM: ped_thr_true \r
- port map( DATAINA => slv_data_in(17 downto 0), \r
- DATAINB => b"00_0000_0000_0000_0000",\r
- ADDRESSA => slv_addr_in(6 downto 0),\r
- ADDRESSB => mem_addr_in,\r
- CLOCKA => clk_in,\r
- CLOCKB => mem_clk_in,\r
- CLOCKENA => '1',\r
- CLOCKENB => '1',\r
- WRA => mem_wr(i), -- BUGBUGBUG\r
- WRB => '0', -- state machine never writes!\r
- RESETA => reset_in,\r
- RESETB => reset_in,\r
- QA => mem_data(i),\r
- QB => ped_data(i)\r
- );\r
+ THE_PED_MEM: ped_thr_true\r
+ port map(\r
+ DATAINA => slv_data_in(17 downto 0),\r
+ DATAINB => b"00_0000_0000_0000_0000",\r
+ ADDRESSA => slv_addr_in(6 downto 0),\r
+ ADDRESSB => mem_addr_in,\r
+ CLOCKA => clk_in,\r
+ CLOCKB => mem_clk_in,\r
+ CLOCKENA => '1',\r
+ CLOCKENB => '1',\r
+ WRA => mem_wr(i), -- BUGBUGBUG\r
+ WRB => '0', -- state machine never writes!\r
+ RESETA => reset_in,\r
+ RESETB => reset_in,\r
+ QA => mem_data(i),\r
+ QB => ped_data(i)\r
+ );\r
-- Write signals\r
mem_wr_x(i) <= '1' when ( (mem_sel(i) = '1') and (store_wr = '1') ) else '0';\r
end generate GEN_PED_MEM;\r
\r
\r
entity slv_register is\r
-generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- BUSY_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- REG_DATA_IN : in std_logic_vector(31 downto 0);\r
- REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+generic(\r
+ RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"\r
+);\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_register is\r
\r
-- Signals\r
-\r
- type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- slave bus signals\r
- signal slv_busy_x : std_logic;\r
- signal slv_busy : std_logic;\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
- signal reg_busy : std_logic;\r
+type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- slave bus signals\r
+signal slv_busy_x : std_logic;\r
+signal slv_busy : std_logic;\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
+\r
+signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
+signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+signal reg_busy : std_logic;\r
\r
begin\r
\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
NEXT_STATE <= RD_RDY;\r
store_rd_x <= '1';\r
elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
NEXT_STATE <= WR_BSY;\r
slv_busy_x <= '1'; -- added 23022009\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when RD_BSY => if( slv_read_in = '0' ) then\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_BSY;\r
slv_busy_x <= '1';\r
end if;\r
- when WR_BSY => if( slv_write_in = '0' ) then\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_BSY;\r
slv_busy_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
use work.adcmv3_components.all;\r
\r
entity slv_register_bank is\r
-generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" );\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
- CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
- CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
- STAT_0_IN : in std_logic_vector(15 downto 0);\r
- STAT_1_IN : in std_logic_vector(15 downto 0);\r
- STAT_2_IN : in std_logic_vector(15 downto 0);\r
- STAT_3_IN : in std_logic_vector(15 downto 0);\r
- STAT_4_IN : in std_logic_vector(15 downto 0);\r
- STAT_5_IN : in std_logic_vector(15 downto 0);\r
- STAT_6_IN : in std_logic_vector(15 downto 0);\r
- STAT_7_IN : in std_logic_vector(15 downto 0);\r
- STAT_8_IN : in std_logic_vector(15 downto 0);\r
- STAT_9_IN : in std_logic_vector(15 downto 0);\r
- STAT_10_IN : in std_logic_vector(15 downto 0);\r
- STAT_11_IN : in std_logic_vector(15 downto 0);\r
- STAT_12_IN : in std_logic_vector(15 downto 0);\r
- STAT_13_IN : in std_logic_vector(15 downto 0);\r
- STAT_14_IN : in std_logic_vector(15 downto 0);\r
- STAT_15_IN : in std_logic_vector(15 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+generic(\r
+ RESET_VALUE : std_logic_vector(15 downto 0) := x"0001"\r
+);\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of slv_register_bank is\r
\r
-- Signals\r
- type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal adc_addr : std_logic_vector(3 downto 0); -- ADC address after mapping\r
- signal reg_sel : std_logic_vector(15 downto 0);\r
- signal reg_wr : std_logic_vector(15 downto 0);\r
- signal reg_wr_x : std_logic_vector(15 downto 0);\r
-\r
- type ctrl_reg_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
- signal ctrl_reg : ctrl_reg_t;\r
-\r
- signal rdback_data : std_logic_vector(31 downto 0);\r
- \r
+type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
+\r
+signal adc_addr : std_logic_vector(3 downto 0); -- ADC address after mapping\r
+signal reg_sel : std_logic_vector(15 downto 0);\r
+signal reg_wr : std_logic_vector(15 downto 0);\r
+signal reg_wr_x : std_logic_vector(15 downto 0);\r
+\r
+type ctrl_reg_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+signal ctrl_reg : ctrl_reg_t;\r
+\r
+signal rdback_data : std_logic_vector(31 downto 0);\r
+\r
begin\r
\r
-- Fake\r
-- Mapping of backplanes --\r
---------------------------------------------------------\r
THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
-port map( ADDRESS(6 downto 4) => backplane_in,\r
- ADDRESS(3 downto 0) => slv_addr_in,\r
- Q => adc_addr\r
- );\r
+port map(\r
+ ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in,\r
+ Q => adc_addr\r
+);\r
\r
THE_REG_SEL_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
case adc_addr is\r
- when x"0" => reg_sel <= b"0000_0000_0000_0001";\r
+ when x"0" => reg_sel <= b"0000_0000_0000_0001";\r
rdback_data <= stat_0_in & ctrl_reg(0);\r
- when x"1" => reg_sel <= b"0000_0000_0000_0010";\r
+ when x"1" => reg_sel <= b"0000_0000_0000_0010";\r
rdback_data <= stat_1_in & ctrl_reg(1);\r
- when x"2" => reg_sel <= b"0000_0000_0000_0100";\r
+ when x"2" => reg_sel <= b"0000_0000_0000_0100";\r
rdback_data <= stat_2_in & ctrl_reg(2);\r
- when x"3" => reg_sel <= b"0000_0000_0000_1000";\r
+ when x"3" => reg_sel <= b"0000_0000_0000_1000";\r
rdback_data <= stat_3_in & ctrl_reg(3);\r
- when x"4" => reg_sel <= b"0000_0000_0001_0000";\r
+ when x"4" => reg_sel <= b"0000_0000_0001_0000";\r
rdback_data <= stat_4_in & ctrl_reg(4);\r
- when x"5" => reg_sel <= b"0000_0000_0010_0000";\r
+ when x"5" => reg_sel <= b"0000_0000_0010_0000";\r
rdback_data <= stat_5_in & ctrl_reg(5);\r
- when x"6" => reg_sel <= b"0000_0000_0100_0000";\r
+ when x"6" => reg_sel <= b"0000_0000_0100_0000";\r
rdback_data <= stat_6_in & ctrl_reg(6);\r
- when x"7" => reg_sel <= b"0000_0000_1000_0000";\r
+ when x"7" => reg_sel <= b"0000_0000_1000_0000";\r
rdback_data <= stat_7_in & ctrl_reg(7);\r
- when x"8" => reg_sel <= b"0000_0001_0000_0000";\r
+ when x"8" => reg_sel <= b"0000_0001_0000_0000";\r
rdback_data <= stat_8_in & ctrl_reg(8);\r
- when x"9" => reg_sel <= b"0000_0010_0000_0000";\r
+ when x"9" => reg_sel <= b"0000_0010_0000_0000";\r
rdback_data <= stat_9_in & ctrl_reg(9);\r
- when x"a" => reg_sel <= b"0000_0100_0000_0000";\r
+ when x"a" => reg_sel <= b"0000_0100_0000_0000";\r
rdback_data <= stat_10_in & ctrl_reg(10);\r
- when x"b" => reg_sel <= b"0000_1000_0000_0000";\r
+ when x"b" => reg_sel <= b"0000_1000_0000_0000";\r
rdback_data <= stat_11_in & ctrl_reg(11);\r
- when x"c" => reg_sel <= b"0001_0000_0000_0000";\r
+ when x"c" => reg_sel <= b"0001_0000_0000_0000";\r
rdback_data <= stat_12_in & ctrl_reg(12);\r
- when x"d" => reg_sel <= b"0010_0000_0000_0000";\r
+ when x"d" => reg_sel <= b"0010_0000_0000_0000";\r
rdback_data <= stat_13_in & ctrl_reg(13);\r
- when x"e" => reg_sel <= b"0100_0000_0000_0000";\r
+ when x"e" => reg_sel <= b"0100_0000_0000_0000";\r
rdback_data <= stat_14_in & ctrl_reg(14);\r
- when x"f" => reg_sel <= b"1000_0000_0000_0000";\r
+ when x"f" => reg_sel <= b"1000_0000_0000_0000";\r
rdback_data <= stat_15_in & ctrl_reg(15);\r
- when others => reg_sel <= b"0000_0000_0000_0000"; -- never used\r
+ when others => reg_sel <= b"0000_0000_0000_0000"; -- never used\r
rdback_data <= x"0000_0000";\r
end case;\r
end if;\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( slv_read_in = '1' ) then\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
NEXT_STATE <= RD_DEL0;\r
store_rd_x <= '1';\r
elsif( slv_write_in = '1' ) then\r
NEXT_STATE <= WR_DEL0;\r
store_wr_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
- when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
- when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
---------------------------------------------------------\r
\r
-- register write\r
-GEN_CTRL_REG: for i in 0 to 15 generate \r
+GEN_CTRL_REG: for i in 0 to 15 generate\r
THE_WR_REG_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
use work.adcmv3_components.all;\r
\r
entity spi_adc_master is\r
-generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" );\r
-port( CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- -- ADC connections\r
- ADC_LOCKED_IN : in std_logic;\r
- ADC_PD_OUT : out std_logic;\r
- ADC_RST_OUT : out std_logic;\r
- ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
- -- APV connections\r
- APV_RST_OUT : out std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+generic(\r
+ RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60"\r
+);\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- ADC connections\r
+ ADC_LOCKED_IN : in std_logic;\r
+ ADC_PD_OUT : out std_logic;\r
+ ADC_RST_OUT : out std_logic;\r
+ ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ -- APV connections\r
+ APV_RST_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
end entity;\r
\r
architecture Behavioral of spi_adc_master is\r
\r
-- Signals\r
- type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- signal status_data : std_logic_vector(31 downto 0);\r
- signal spi_busy : std_logic;\r
- \r
- signal reg_ctrl_data : std_logic_vector(7 downto 0); \r
- signal adc_ctrl_data : std_logic_vector(7 downto 0); \r
- \r
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback\r
- \r
- signal spi_start_x : std_logic;\r
- signal spi_start : std_logic;\r
- \r
- -- State machine signals\r
- signal slv_busy_x : std_logic;\r
- signal slv_busy : std_logic;\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
+type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+signal status_data : std_logic_vector(31 downto 0);\r
+signal spi_busy : std_logic;\r
+\r
+signal reg_ctrl_data : std_logic_vector(7 downto 0);\r
+signal adc_ctrl_data : std_logic_vector(7 downto 0);\r
+\r
+signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback\r
+\r
+signal spi_start_x : std_logic;\r
+signal spi_start : std_logic;\r
+\r
+-- State machine signals\r
+signal slv_busy_x : std_logic;\r
+signal slv_busy : std_logic;\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+signal store_wr_x : std_logic;\r
+signal store_wr : std_logic;\r
+signal store_rd_x : std_logic;\r
+signal store_rd : std_logic;\r
\r
begin\r
\r
---------------------------------------------------------\r
\r
THE_SPI_REAL_SLIM: spi_real_slim\r
-port map( SYSCLK => clk_in,\r
- RESET => reset_in,\r
- -- Command interface\r
- START_IN => spi_start,\r
- BUSY_OUT => spi_busy,\r
- CMD_IN => reg_ctrl_data,\r
- -- SPI interface\r
- SPI_SCK_OUT => spi_sck_out,\r
- SPI_CS_OUT => spi_cs_out,\r
- SPI_SDO_OUT => spi_sdo_out,\r
- -- DEBUG\r
- CLK_EN_OUT => open,\r
- BSM_OUT => open,\r
- DEBUG_OUT => open\r
- );\r
+port map(\r
+ SYSCLK => clk_in,\r
+ RESET => reset_in,\r
+ -- Command interface\r
+ START_IN => spi_start,\r
+ BUSY_OUT => spi_busy,\r
+ CMD_IN => reg_ctrl_data,\r
+ -- SPI interface\r
+ SPI_SCK_OUT => spi_sck_out,\r
+ SPI_CS_OUT => spi_cs_out,\r
+ SPI_SDO_OUT => spi_sdo_out,\r
+ -- DEBUG\r
+ CLK_EN_OUT => open,\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+);\r
\r
---------------------------------------------------------\r
-- Statemachine --\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then\r
+ when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then\r
NEXT_STATE <= RD_RDY;\r
store_rd_x <= '1';\r
elsif( (spi_busy = '0') and (slv_write_in = '1') ) then\r
elsif( (spi_busy = '1') and (slv_write_in = '1') ) then\r
NEXT_STATE <= WR_BSY;\r
slv_busy_x <= '1';\r
- else \r
+ else\r
NEXT_STATE <= SLEEP;\r
end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when RD_BSY => if( slv_read_in = '0' ) then\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= RD_BSY;\r
slv_busy_x <= '1';\r
end if;\r
- when WR_BSY => if( slv_write_in = '0' ) then\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
NEXT_STATE <= DONE;\r
else\r
NEXT_STATE <= WR_BSY;\r
slv_busy_x <= '1';\r
end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
\r
\r
entity spi_real_slim is\r
- port( SYSCLK : in std_logic; -- 100MHz sysclock\r
- RESET : in std_logic; -- synchronous reset\r
- -- Command interface\r
- START_IN : in std_logic; -- one start pulse\r
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
- CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
- -- SPI interface\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- DEBUG\r
- CLK_EN_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
+port(\r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+);\r
end spi_real_slim;\r
\r
architecture Behavioral of spi_real_slim is\r
\r
-- new clock divider\r
-signal div_counter : std_logic_vector(1 downto 0);\r
-signal div_done_x : std_logic;\r
-signal div_done : std_logic; -- same as clk_en\r
-signal clk_en : std_logic; -- same as div_done\r
+signal div_counter : std_logic_vector(1 downto 0);\r
+signal div_done_x : std_logic;\r
+signal div_done : std_logic; -- same as clk_en\r
+signal clk_en : std_logic; -- same as div_done\r
\r
-- Statemachine signals\r
type state_t is (IDLE,CSL,TXCMD,CSH);\r
-signal STATE, NEXT_STATE : state_t;\r
-\r
-signal tx_ena_x : std_logic;\r
-signal tx_ena : std_logic;\r
-signal busy_x : std_logic;\r
-signal busy : std_logic;\r
-signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
-signal spi_cs : std_logic;\r
-signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
-signal spi_sck : std_logic;\r
-signal tx_load_x : std_logic; -- load TX shift register\r
-signal tx_load : std_logic;\r
-\r
-signal last_tx_bit_x : std_logic;\r
-signal last_tx_bit : std_logic;\r
+signal STATE, NEXT_STATE : state_t;\r
+\r
+signal tx_ena_x : std_logic;\r
+signal tx_ena : std_logic;\r
+signal busy_x : std_logic;\r
+signal busy : std_logic;\r
+signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
+signal spi_cs : std_logic;\r
+signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
+signal spi_sck : std_logic;\r
+signal tx_load_x : std_logic; -- load TX shift register\r
+signal tx_load : std_logic;\r
+\r
+signal last_tx_bit_x : std_logic;\r
+signal last_tx_bit : std_logic;\r
\r
-- debug signals\r
-signal bsm_x : std_logic_vector(7 downto 0);\r
-signal debug_x : std_logic_vector(31 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal debug_x : std_logic_vector(31 downto 0);\r
\r
-signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
-signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
+signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
\r
-- transmitter\r
-signal tx_sreg : std_logic_vector(7 downto 0);\r
-signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
-signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
+signal tx_sreg : std_logic_vector(7 downto 0);\r
+signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
+signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
\r
begin\r
\r
debug_x(6) <= '0';\r
debug_x(5) <= tx_load;\r
debug_x(4) <= tx_ena;\r
-debug_x(3) <= '0'; \r
+debug_x(3) <= '0';\r
debug_x(2 downto 0) <= (others => '0');\r
\r
\r
THE_STATEMACHINE_OUT: process( STATE )\r
begin\r
case STATE is\r
- when IDLE => bsm_x <= x"00";\r
- when CSL => bsm_x <= x"01";\r
- when TXCMD => bsm_x <= x"02";\r
- when CSH => bsm_x <= x"03";\r
- when others => bsm_x <= x"ff";\r
+ when IDLE => bsm_x <= x"00";\r
+ when CSL => bsm_x <= x"01";\r
+ when TXCMD => bsm_x <= x"02";\r
+ when CSH => bsm_x <= x"03";\r
+ when others => bsm_x <= x"ff";\r
end case;\r
end process THE_STATEMACHINE_OUT;\r
\r
use work.adcmv3_components.all;\r
\r
entity state_sync is\r
- port( STATE_A_IN : in std_logic;\r
- RESET_B_IN : in std_logic;\r
- CLK_B_IN : in std_logic;\r
- STATE_B_OUT : out std_logic\r
- );\r
+port(\r
+ STATE_A_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ STATE_B_OUT : out std_logic\r
+);\r
end;\r
\r
architecture behavioral of state_sync is\r
\r
- -- normal signals\r
- signal sync_q : std_logic;\r
- signal sync_qq : std_logic;\r
- \r
+-- normal signals\r
+signal sync_q : std_logic;\r
+signal sync_qq : std_logic;\r
+\r
begin\r
\r
-- synchronizing stage for clock domain B\r
TRB_TTAG_IN : IN std_logic_vector(15 downto 0);\r
TRB_TRND_IN : IN std_logic_vector(7 downto 0);\r
TRB_TTYPE_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TINFO_IN : IN std_logic_vector(23 downto 0);\r
TRB_TRGRCVD_IN : IN std_logic;\r
- TRB_RST_COUNTER_IN : IN std_logic;\r
+ TRB_COUNTER_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_LD_COUNTER_IN : IN std_logic;\r
EDS_DONE_IN : IN std_logic; \r
TRG_FOUND_OUT : OUT std_logic;\r
TRB_MISSING_OUT : OUT std_logic;\r
SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0);\r
SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0);\r
SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TINFO_IN : std_logic_vector(23 downto 0);\r
SIGNAL TRB_TRGRCVD_IN : std_logic;\r
SIGNAL TRB_MISSING_OUT : std_logic;\r
SIGNAL TRB_RELEASE_OUT : std_logic;\r
- SIGNAL TRB_RST_COUNTER_IN : std_logic;\r
+ SIGNAL TRB_COUNTER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_LD_COUNTER_IN : std_logic;\r
SIGNAL TRB_COUNTER_OUT : std_logic_vector(15 downto 0);\r
SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0);\r
SIGNAL EDS_AVAIL_OUT : std_logic;\r
TRB_TTAG_IN => TRB_TTAG_IN,\r
TRB_TRND_IN => TRB_TRND_IN,\r
TRB_TTYPE_IN => TRB_TTYPE_IN,\r
+ TRB_TINFO_IN => TRB_TINFO_IN,\r
TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
TRB_MISSING_OUT => TRB_MISSING_OUT,\r
TRB_RELEASE_OUT => TRB_RELEASE_OUT,\r
- TRB_RST_COUNTER_IN => TRB_RST_COUNTER_IN,\r
+ TRB_COUNTER_IN => TRB_COUNTER_IN,\r
+ TRB_LD_COUNTER_IN => TRB_LD_COUNTER_IN,\r
TRB_COUNTER_OUT => TRB_COUNTER_OUT,\r
EDS_DATA_OUT => EDS_DATA_OUT,\r
EDS_AVAIL_OUT => EDS_AVAIL_OUT,\r
trb_ttag_in <= x"0000";\r
trb_trnd_in <= x"00";\r
trb_ttype_in <= x"0";\r
+ trb_tinfo_in <= x"00_00_00";\r
trb_trgrcvd_in <= '0';\r
- trb_rst_counter_in <= '0';\r
+ trb_counter_in <= x"dead";\r
+ trb_ld_counter_in <= '0';\r
eds_done_in <= '0';\r
\r
wait for 20 ns;\r
wait until rising_edge(clk_in);\r
\r
wait for 1 us;\r
+\r
+ -- Set local LVL1 counter to TRBnet value\r
+ wait until rising_edge(clk_in);\r
+ trb_ld_counter_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ trb_ld_counter_in <= '0';\r
\r
-- first trigger\r
-- send in one timing trigger\r
wait for 2.3 us;\r
wait until rising_edge(clk_in);\r
trb_ttype_in <= x"1";\r
- trb_ttag_in <= x"abcd";\r
- trb_trnd_in <= x"ef";\r
+ trb_ttag_in <= x"dead";\r
+ trb_trnd_in <= x"a0";\r
+ trb_tinfo_in <= x"00_00_00"; -- data format = b"000"\r
wait until rising_edge(clk_in);\r
trb_trgrcvd_in <= '1';\r
\r
-- release trigger\r
+ wait until rising_edge(clk_in);\r
wait until rising_edge(trb_release_out);\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
wait for 2.3 us;\r
wait until rising_edge(clk_in);\r
trb_ttype_in <= x"2";\r
- trb_ttag_in <= x"dead";\r
+ trb_ttag_in <= x"deae";\r
trb_trnd_in <= x"42";\r
+ trb_tinfo_in <= x"00_01_00"; -- data format = b"001"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.11 us;\r
+\r
+ -- next trigger (missing timing trigger)\r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"3";\r
+ trb_ttag_in <= x"deaf";\r
+ trb_trnd_in <= x"7c";\r
+ trb_tinfo_in <= x"00_05_00"; -- data format = b"101"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.51 us;\r
+\r
+ -- next trigger (timingtriggerless trigger)\r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"9";\r
+ trb_ttag_in <= x"deb0";\r
+ trb_trnd_in <= x"19";\r
+ trb_tinfo_in <= x"00_00_80"; -- timingtriggerless trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.21 us;\r
+\r
+ -- next trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"4";\r
+ trb_ttag_in <= x"deb1";\r
+ trb_trnd_in <= x"97";\r
+ trb_tinfo_in <= x"00_00_01"; -- data format = b"000", suppress data\r
wait until rising_edge(clk_in);\r
trb_trgrcvd_in <= '1';\r
\r
eds_done_in <= '1';\r
wait until rising_edge(clk_in);\r
eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
\r
- wait for 200 ns;\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
\r
-- release one EDS\r
wait until rising_edge(clk_in);\r
eds_done_in <= '1';\r
wait until rising_edge(clk_in);\r
eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
\r
\r
-- Stay a while, stay forever.... wuhahahahaha\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
-library work;\r
-use work.adcmv3_components.all;\r
-\r
ENTITY testbench IS\r
END testbench;\r
\r
DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0);\r
DHDR_STORE_IN : IN std_logic;\r
FIFO_START_IN : IN std_logic;\r
+ FIFO_SPACE_REQ_IN : IN std_logic_vector(11 downto 0);\r
FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0);\r
FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0);\r
FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0);\r
IPU_READOUT_FINISHED_OUT : OUT std_logic;\r
IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+ LVL2_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
+ DHDR_BUF_FULL_OUT : OUT std_logic;\r
DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
DBG_OUT : OUT std_logic_vector(63 downto 0)\r
);\r
SIGNAL IPU_READ_IN : std_logic;\r
SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0);\r
SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL LVL2_COUNTER_OUT : std_logic_vector(15 downto 0);\r
SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0);\r
SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0);\r
SIGNAL DHDR_STORE_IN : std_logic;\r
+ SIGNAL DHDR_BUF_FULL_OUT : std_logic;\r
SIGNAL FIFO_START_IN : std_logic;\r
+ SIGNAL FIFO_SPACE_REQ_IN : std_logic_vector(11 downto 0);\r
SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0);\r
SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0);\r
SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0);\r
IPU_READ_IN => IPU_READ_IN,\r
IPU_LENGTH_OUT => IPU_LENGTH_OUT,\r
IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,\r
+ LVL2_COUNTER_OUT => LVL2_COUNTER_OUT,\r
DHDR_DATA_IN => DHDR_DATA_IN,\r
DHDR_LENGTH_IN => DHDR_LENGTH_IN,\r
DHDR_STORE_IN => DHDR_STORE_IN,\r
+ DHDR_BUF_FULL_OUT => DHDR_BUF_FULL_OUT,\r
FIFO_START_IN => FIFO_START_IN,\r
+ FIFO_SPACE_REQ_IN => FIFO_SPACE_REQ_IN,\r
FIFO_0_DATA_IN => FIFO_0_DATA_IN,\r
FIFO_1_DATA_IN => FIFO_1_DATA_IN,\r
FIFO_2_DATA_IN => FIFO_2_DATA_IN,\r
dhdr_data_in <= x"01234567";\r
dhdr_length_in <= x"0000";\r
dhdr_store_in <= '0';\r
+-- fifo_space_req_in <= x"082"; -- 128 + 2\r
+ fifo_space_req_in <= x"7f8"; \r
fifo_start_in <= '0';\r
fifo_we_in <= x"0000";\r
fifo_done_in <= '0';\r
-- Fill data buffers\r
wait until rising_edge(clk_in);\r
fifo_we_in <= b"1111_1111_1111_1111";\r
+-- fifo_we_in <= b"1111_1111_0111_1111";\r
fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_1111";\r
fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0001_1110";\r
fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0010_1101";\r
fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1110_0001";\r
fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1111_0000";\r
wait until rising_edge(clk_in);\r
- fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000";\r
- fifo_we_in(0) <= '0';\r
- wait until rising_edge(clk_in);\r
-\r
+-- fifo_we_in <= b"1111_1111_1111_1110";\r
+ fifo_we_in <= b"1111_1111_0111_1110";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0001_1110";\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1100";\r
+ fifo_we_in <= b"1111_1111_0111_1100";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1000";\r
+ fifo_we_in <= b"1111_1111_0111_1000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_0000";\r
+ fifo_we_in <= b"1111_1111_0111_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1110_0000";\r
+ fifo_we_in <= b"1111_1111_0110_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1100_0000";\r
+ fifo_we_in <= b"1111_1111_0100_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1000_0000";\r
+ fifo_we_in <= b"1111_1111_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1111_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1110_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1100_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1110_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1100_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1000_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1111_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"0000_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
wait until rising_edge(clk_in);\r
\r
-- Final stage, counter values setting\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
- fifo_0_data_in(37 downto 27) <= "10000000001"; -- "10000000011"; -- 3\r
- fifo_1_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_2_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_3_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_4_data_in(37 downto 27) <= "10000000001"; -- "10000000101"; -- 5\r
- fifo_5_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_6_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_7_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7\r
- fifo_8_data_in(37 downto 27) <= "10000000001"; -- "10000000001"; -- 1\r
- fifo_9_data_in(37 downto 27) <= "10000000001"; -- "10000000010"; -- 2\r
- fifo_10_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_11_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_12_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
- fifo_13_data_in(37 downto 27) <= "10000000001"; -- "10000001000"; -- 8\r
- fifo_14_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7\r
- fifo_15_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_0_data_in(37 downto 27) <= "10000000001"; -- 1\r
+ fifo_1_data_in(37 downto 27) <= "10000000010"; -- 2\r
+ fifo_2_data_in(37 downto 27) <= "10000000011"; -- 3\r
+ fifo_3_data_in(37 downto 27) <= "10000000100"; -- 4\r
+ fifo_4_data_in(37 downto 27) <= "10000000101"; -- 5\r
+ fifo_5_data_in(37 downto 27) <= "10000000110"; -- 6\r
+ fifo_6_data_in(37 downto 27) <= "10000000111"; -- 7\r
+-- fifo_7_data_in(37 downto 27) <= "10000001000"; -- 8\r
+ fifo_7_data_in(37 downto 27) <= "10000000001"; -- NO DATA\r
+ fifo_8_data_in(37 downto 27) <= "10000001001"; -- 9\r
+ fifo_9_data_in(37 downto 27) <= "10000001010"; -- 10\r
+ fifo_10_data_in(37 downto 27) <= "10000001011"; -- 11\r
+ fifo_11_data_in(37 downto 27) <= "10000001100"; -- 12\r
+ fifo_12_data_in(37 downto 27) <= "10000001101"; -- 13\r
+ fifo_13_data_in(37 downto 27) <= "10000001110"; -- 14\r
+ fifo_14_data_in(37 downto 27) <= "10000001111"; -- 15\r
+ fifo_15_data_in(37 downto 27) <= "10000010000"; -- 16\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
+ wait for 2 us;\r
\r
-- IPU request\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ THE_LOOP: for i in 0 to 1024 loop\r
+ ipu_read_in <= '1';\r
+ wait until (ipu_dataready_out = '1') or (ipu_readout_finished_out = '1');\r
+ if ipu_readout_finished_out = '1' then exit; end if;\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ if ipu_readout_finished_out = '1' then exit; end if;\r
+ wait until rising_edge(clk_in);\r
+ \r
+ end loop THE_LOOP;\r
+\r
+ wait;\r
+\r
+---\r
+-- theloop : for i in 0 to 100 loop\r
+-- ipu_read_in <= '1';\r
+-- wait until ipu_dataready_out = '1' or ipu_readout_finished_out = '1';\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- wait until rising_edge(CLOCK);\r
+-- ipu_read_in <= '0';\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- case i is\r
+-- when 3 => wait for 39 ns;\r
+-- when 4 => wait for 49 ns;\r
+-- when 5 => wait for 29 ns;\r
+-- when others => null;\r
+-- end case;\r
+-- wait until rising_edge(CLOCK);\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- end loop;\r
+---\r
+\r
+\r
+ wait;\r
+\r
\r
ipu_read_in <= '1';\r
wait until rising_edge(clk_in);\r
RESET_IN : IN std_logic;\r
EDS_DATA_IN : IN std_logic_vector(39 downto 0);\r
EDS_AVAIL_IN : IN std_logic;\r
- EVT_TYPE_IN : IN std_logic_vector(2 downto 0);\r
BUF_TICK_IN : IN std_logic_vector(15 downto 0);\r
BUF_START_IN : IN std_logic_vector(15 downto 0);\r
BUF_0_DATA_IN : IN std_logic_vector(37 downto 0);\r
EDS_DONE_OUT : OUT std_logic;\r
DHDR_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
DHDR_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ DHDR_BUF_FULL_IN : IN std_logic;\r
DHDR_STORE_OUT : OUT std_logic;\r
+ FIFO_SPACE_REQ_OUT : OUT std_logic_vector(11 downto 0);\r
PED_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
THR_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
BUF_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
SIGNAL EDS_DONE_OUT : std_logic;\r
SIGNAL DHDR_DATA_OUT : std_logic_vector(31 downto 0);\r
SIGNAL DHDR_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_BUF_FULL_IN : std_logic;\r
SIGNAL DHDR_STORE_OUT : std_logic;\r
- SIGNAL EVT_TYPE_IN : std_logic_vector(2 downto 0);\r
SIGNAL BUF_ADDR_OUT : std_logic_vector(6 downto 0);\r
SIGNAL BUF_DONE_OUT : std_logic;\r
SIGNAL BUF_TICK_IN : std_logic_vector(15 downto 0);\r
SIGNAL BUF_START_IN : std_logic_vector(15 downto 0);\r
SIGNAL BUF_0_DATA_IN : std_logic_vector(37 downto 0);\r
SIGNAL BUF_1_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_2_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_3_DATA_IN : std_logic_vector(37 downto 0);\r
SIGNAL BUF_4_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_5_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_6_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_7_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_8_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_9_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_10_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_11_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_12_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_13_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_14_DATA_IN : std_logic_vector(37 downto 0);\r
- SIGNAL BUF_15_DATA_IN : std_logic_vector(37 downto 0);\r
SIGNAL THR_ADDR_OUT : std_logic_vector(6 downto 0);\r
SIGNAL THR_0_DATA_IN : std_logic_vector(17 downto 0);\r
SIGNAL THR_1_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_2_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_3_DATA_IN : std_logic_vector(17 downto 0);\r
SIGNAL THR_4_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_5_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_6_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_7_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_8_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_9_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_10_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_11_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_12_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_13_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_14_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL THR_15_DATA_IN : std_logic_vector(17 downto 0);\r
SIGNAL PED_ADDR_OUT : std_logic_vector(6 downto 0);\r
SIGNAL PED_0_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_1_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_2_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_3_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_4_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_5_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_6_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_7_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_8_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_9_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_10_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_11_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_12_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_13_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_14_DATA_IN : std_logic_vector(17 downto 0);\r
- SIGNAL PED_15_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL FIFO_SPACE_REQ_OUT : std_logic_vector(11 downto 0);\r
SIGNAL FIFO_START_OUT : std_logic;\r
- SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0);\r
+-- SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL ADC_0_STATUS_OUT : std_logic_vector(25 downto 0);\r
+ SIGNAL ADC_0_DATA_OUT : std_logic_vector(13 downto 0);\r
SIGNAL FIFO_1_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_2_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_3_DATA_OUT : std_logic_vector(39 downto 0);\r
SIGNAL FIFO_4_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_5_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_6_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_7_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_8_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_9_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_10_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_11_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_12_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_13_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_14_DATA_OUT : std_logic_vector(39 downto 0);\r
- SIGNAL FIFO_15_DATA_OUT : std_logic_vector(39 downto 0);\r
SIGNAL FIFO_WE_OUT : std_logic_vector(15 downto 0);\r
SIGNAL FIFO_DONE_OUT : std_logic;\r
SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
EDS_DONE_OUT => EDS_DONE_OUT,\r
DHDR_DATA_OUT => DHDR_DATA_OUT,\r
DHDR_LENGTH_OUT => DHDR_LENGTH_OUT,\r
+ DHDR_BUF_FULL_IN => DHDR_BUF_FULL_IN,\r
DHDR_STORE_OUT => DHDR_STORE_OUT,\r
- EVT_TYPE_IN => EVT_TYPE_IN,\r
BUF_ADDR_OUT => BUF_ADDR_OUT,\r
BUF_DONE_OUT => BUF_DONE_OUT,\r
BUF_TICK_IN => BUF_TICK_IN,\r
BUF_START_IN => BUF_START_IN,\r
BUF_0_DATA_IN => BUF_0_DATA_IN,\r
BUF_1_DATA_IN => BUF_1_DATA_IN,\r
- BUF_2_DATA_IN => BUF_2_DATA_IN,\r
- BUF_3_DATA_IN => BUF_3_DATA_IN,\r
+ BUF_2_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_3_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
BUF_4_DATA_IN => BUF_4_DATA_IN,\r
- BUF_5_DATA_IN => BUF_5_DATA_IN,\r
- BUF_6_DATA_IN => BUF_6_DATA_IN,\r
- BUF_7_DATA_IN => BUF_7_DATA_IN,\r
- BUF_8_DATA_IN => BUF_8_DATA_IN,\r
- BUF_9_DATA_IN => BUF_9_DATA_IN,\r
- BUF_10_DATA_IN => BUF_10_DATA_IN,\r
- BUF_11_DATA_IN => BUF_11_DATA_IN,\r
- BUF_12_DATA_IN => BUF_12_DATA_IN,\r
- BUF_13_DATA_IN => BUF_13_DATA_IN,\r
- BUF_14_DATA_IN => BUF_14_DATA_IN,\r
- BUF_15_DATA_IN => BUF_15_DATA_IN,\r
+ BUF_5_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_6_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_7_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_8_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_9_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_10_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_11_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_12_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_13_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_14_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_15_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
PED_ADDR_OUT => PED_ADDR_OUT,\r
PED_0_DATA_IN => PED_0_DATA_IN,\r
- PED_1_DATA_IN => PED_1_DATA_IN,\r
- PED_2_DATA_IN => PED_2_DATA_IN,\r
- PED_3_DATA_IN => PED_3_DATA_IN,\r
- PED_4_DATA_IN => PED_4_DATA_IN,\r
- PED_5_DATA_IN => PED_5_DATA_IN,\r
- PED_6_DATA_IN => PED_6_DATA_IN,\r
- PED_7_DATA_IN => PED_7_DATA_IN,\r
- PED_8_DATA_IN => PED_8_DATA_IN,\r
- PED_9_DATA_IN => PED_9_DATA_IN,\r
- PED_10_DATA_IN => PED_10_DATA_IN,\r
- PED_11_DATA_IN => PED_11_DATA_IN,\r
- PED_12_DATA_IN => PED_12_DATA_IN,\r
- PED_13_DATA_IN => PED_13_DATA_IN,\r
- PED_14_DATA_IN => PED_14_DATA_IN,\r
- PED_15_DATA_IN => PED_15_DATA_IN,\r
+ PED_1_DATA_IN => b"00" & x"0000",\r
+ PED_2_DATA_IN => b"00" & x"0000",\r
+ PED_3_DATA_IN => b"00" & x"0000",\r
+ PED_4_DATA_IN => b"00" & x"0000",\r
+ PED_5_DATA_IN => b"00" & x"0000",\r
+ PED_6_DATA_IN => b"00" & x"0000",\r
+ PED_7_DATA_IN => b"00" & x"0000",\r
+ PED_8_DATA_IN => b"00" & x"0000",\r
+ PED_9_DATA_IN => b"00" & x"0000",\r
+ PED_10_DATA_IN => b"00" & x"0000",\r
+ PED_11_DATA_IN => b"00" & x"0000",\r
+ PED_12_DATA_IN => b"00" & x"0000",\r
+ PED_13_DATA_IN => b"00" & x"0000",\r
+ PED_14_DATA_IN => b"00" & x"0000",\r
+ PED_15_DATA_IN => b"00" & x"0000",\r
THR_ADDR_OUT => THR_ADDR_OUT,\r
THR_0_DATA_IN => THR_0_DATA_IN,\r
THR_1_DATA_IN => THR_1_DATA_IN,\r
- THR_2_DATA_IN => THR_2_DATA_IN,\r
- THR_3_DATA_IN => THR_3_DATA_IN,\r
+ THR_2_DATA_IN => b"00" & x"0000",\r
+ THR_3_DATA_IN => b"00" & x"0000",\r
THR_4_DATA_IN => THR_4_DATA_IN,\r
- THR_5_DATA_IN => THR_5_DATA_IN,\r
- THR_6_DATA_IN => THR_6_DATA_IN,\r
- THR_7_DATA_IN => THR_7_DATA_IN,\r
- THR_8_DATA_IN => THR_8_DATA_IN,\r
- THR_9_DATA_IN => THR_9_DATA_IN,\r
- THR_10_DATA_IN => THR_10_DATA_IN,\r
- THR_11_DATA_IN => THR_11_DATA_IN,\r
- THR_12_DATA_IN => THR_12_DATA_IN,\r
- THR_13_DATA_IN => THR_13_DATA_IN,\r
- THR_14_DATA_IN => THR_14_DATA_IN,\r
- THR_15_DATA_IN => THR_15_DATA_IN,\r
+ THR_5_DATA_IN => b"00" & x"0000",\r
+ THR_6_DATA_IN => b"00" & x"0000",\r
+ THR_7_DATA_IN => b"00" & x"0000",\r
+ THR_8_DATA_IN => b"00" & x"0000",\r
+ THR_9_DATA_IN => b"00" & x"0000",\r
+ THR_10_DATA_IN => b"00" & x"0000",\r
+ THR_11_DATA_IN => b"00" & x"0000",\r
+ THR_12_DATA_IN => b"00" & x"0000",\r
+ THR_13_DATA_IN => b"00" & x"0000",\r
+ THR_14_DATA_IN => b"00" & x"0000",\r
+ THR_15_DATA_IN => b"00" & x"0000",\r
+ FIFO_SPACE_REQ_OUT => FIFO_SPACE_REQ_OUT,\r
FIFO_START_OUT => FIFO_START_OUT,\r
- FIFO_0_DATA_OUT => FIFO_0_DATA_OUT,\r
+-- FIFO_0_DATA_OUT => FIFO_0_DATA_OUT,\r
+ FIFO_0_DATA_OUT(39 downto 14) => ADC_0_STATUS_OUT,\r
+ FIFO_0_DATA_OUT(13 downto 0) => ADC_0_DATA_OUT,\r
FIFO_1_DATA_OUT => FIFO_1_DATA_OUT,\r
- FIFO_2_DATA_OUT => FIFO_2_DATA_OUT,\r
- FIFO_3_DATA_OUT => FIFO_3_DATA_OUT,\r
- FIFO_4_DATA_OUT => FIFO_4_DATA_OUT,\r
- FIFO_5_DATA_OUT => FIFO_5_DATA_OUT,\r
- FIFO_6_DATA_OUT => FIFO_6_DATA_OUT,\r
- FIFO_7_DATA_OUT => FIFO_7_DATA_OUT,\r
- FIFO_8_DATA_OUT => FIFO_8_DATA_OUT,\r
- FIFO_9_DATA_OUT => FIFO_9_DATA_OUT,\r
- FIFO_10_DATA_OUT => FIFO_10_DATA_OUT,\r
- FIFO_11_DATA_OUT => FIFO_11_DATA_OUT,\r
- FIFO_12_DATA_OUT => FIFO_12_DATA_OUT,\r
- FIFO_13_DATA_OUT => FIFO_13_DATA_OUT,\r
- FIFO_14_DATA_OUT => FIFO_14_DATA_OUT,\r
- FIFO_15_DATA_OUT => FIFO_15_DATA_OUT,\r
+ FIFO_2_DATA_OUT => open,\r
+ FIFO_3_DATA_OUT => open,\r
+ FIFO_4_DATA_OUT => open,\r
+ FIFO_5_DATA_OUT => open,\r
+ FIFO_6_DATA_OUT => open,\r
+ FIFO_7_DATA_OUT => open,\r
+ FIFO_8_DATA_OUT => open,\r
+ FIFO_9_DATA_OUT => open,\r
+ FIFO_10_DATA_OUT => open,\r
+ FIFO_11_DATA_OUT => open,\r
+ FIFO_12_DATA_OUT => open,\r
+ FIFO_13_DATA_OUT => open,\r
+ FIFO_14_DATA_OUT => open,\r
+ FIFO_15_DATA_OUT => open,\r
FIFO_WE_OUT => FIFO_WE_OUT,\r
FIFO_DONE_OUT => FIFO_DONE_OUT,\r
DBG_BSM_OUT => DBG_BSM_OUT,\r
begin\r
-- Setup signal\r
reset_in <= '0';\r
+ dhdr_buf_full_in <= '0';\r
eds_data_in <= (others => '0'); \r
eds_avail_in <= '0';\r
- evt_type_in <= "000";\r
buf_start_in <= (others => '0'); \r
buf_tick_in <= (others => '0');\r
-- Buffer level information: 7 -> good, 6 -> broken, 5 -> ignore, rest LEVEL\r
buf_0_data_in(37 downto 30) <= x"80"; -- good\r
buf_1_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_2_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_3_data_in(37 downto 30) <= x"20"; -- ignore\r
buf_4_data_in(37 downto 30) <= x"40"; -- broken!!!\r
- buf_5_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_6_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_7_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_8_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_9_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_10_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_11_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_12_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_13_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_14_data_in(37 downto 30) <= x"20"; -- ignore\r
- buf_15_data_in(37 downto 30) <= x"20"; -- ignore\r
-- Buffer frame information: 8 -> APV error, [7:0] row\r
buf_0_data_in(29 downto 18) <= x"011"; -- row 0x11, no error\r
buf_1_data_in(29 downto 18) <= x"0ee"; --\r
- buf_2_data_in(29 downto 18) <= x"0ee"; --\r
- buf_3_data_in(29 downto 18) <= x"0ee"; --\r
buf_4_data_in(29 downto 18) <= x"0aa"; --\r
- buf_5_data_in(29 downto 18) <= x"0ee"; --\r
- buf_6_data_in(29 downto 18) <= x"0ee"; --\r
- buf_7_data_in(29 downto 18) <= x"0ee"; --\r
- buf_8_data_in(29 downto 18) <= x"0ee"; --\r
- buf_9_data_in(29 downto 18) <= x"0ee"; --\r
- buf_10_data_in(29 downto 18) <= x"0ee"; --\r
- buf_11_data_in(29 downto 18) <= x"0ee"; --\r
- buf_12_data_in(29 downto 18) <= x"0ee"; --\r
- buf_13_data_in(29 downto 18) <= x"0ee"; --\r
- buf_14_data_in(29 downto 18) <= x"0ee"; --\r
- buf_15_data_in(29 downto 18) <= x"0ee"; --\r
-- Buffer data\r
buf_0_data_in(17 downto 14) <= x"0";\r
buf_1_data_in(17 downto 14) <= x"0"; buf_1_data_in(13 downto 0) <= "00000000000000";\r
- buf_2_data_in(17 downto 14) <= x"0"; buf_2_data_in(13 downto 0) <= "00000000000000";\r
- buf_3_data_in(17 downto 14) <= x"0"; buf_3_data_in(13 downto 0) <= "00000000000000";\r
buf_4_data_in(17 downto 14) <= x"0"; buf_4_data_in(13 downto 0) <= "00000000000000";\r
- buf_5_data_in(17 downto 14) <= x"0"; buf_5_data_in(13 downto 0) <= "00000000000000";\r
- buf_6_data_in(17 downto 14) <= x"0"; buf_6_data_in(13 downto 0) <= "00000000000000";\r
- buf_7_data_in(17 downto 14) <= x"0"; buf_7_data_in(13 downto 0) <= "00000000000000";\r
- buf_8_data_in(17 downto 14) <= x"0"; buf_8_data_in(13 downto 0) <= "00000000000000";\r
- buf_9_data_in(17 downto 14) <= x"0"; buf_9_data_in(13 downto 0) <= "00000000000000";\r
- buf_10_data_in(17 downto 14) <= x"0"; buf_10_data_in(13 downto 0) <= "00000000000000";\r
- buf_11_data_in(17 downto 14) <= x"0"; buf_11_data_in(13 downto 0) <= "00000000000000";\r
- buf_12_data_in(17 downto 14) <= x"0"; buf_12_data_in(13 downto 0) <= "00000000000000";\r
- buf_13_data_in(17 downto 14) <= x"0"; buf_13_data_in(13 downto 0) <= "00000000000000";\r
- buf_14_data_in(17 downto 14) <= x"0"; buf_14_data_in(13 downto 0) <= "00000000000000";\r
- buf_15_data_in(17 downto 14) <= x"0"; buf_15_data_in(13 downto 0) <= "00000000000000";\r
-- Pedestal data\r
--- ped_0_data_in <= "00" & x"0000";\r
- ped_1_data_in <= "00" & x"0000";\r
- ped_2_data_in <= "00" & x"0000";\r
- ped_3_data_in <= "00" & x"0000";\r
- ped_4_data_in <= "00" & x"0000";\r
- ped_5_data_in <= "00" & x"0000";\r
- ped_6_data_in <= "00" & x"0000";\r
- ped_7_data_in <= "00" & x"0000";\r
- ped_8_data_in <= "00" & x"0000";\r
- ped_9_data_in <= "00" & x"0000";\r
- ped_10_data_in <= "00" & x"0000";\r
- ped_11_data_in <= "00" & x"0000";\r
- ped_12_data_in <= "00" & x"0000";\r
- ped_13_data_in <= "00" & x"0000";\r
- ped_14_data_in <= "00" & x"0000";\r
- ped_15_data_in <= "00" & x"0000";\r
-- Threshold data\r
-- thr_0_data_in <= "00" & x"0000";\r
thr_1_data_in <= "00" & x"0000";\r
- thr_2_data_in <= "00" & x"0000";\r
- thr_3_data_in <= "00" & x"0000";\r
thr_4_data_in <= "00" & x"0000";\r
- thr_5_data_in <= "00" & x"0000";\r
- thr_6_data_in <= "00" & x"0000";\r
- thr_7_data_in <= "00" & x"0000";\r
- thr_8_data_in <= "00" & x"0000";\r
- thr_9_data_in <= "00" & x"0000";\r
- thr_10_data_in <= "00" & x"0000";\r
- thr_11_data_in <= "00" & x"0000";\r
- thr_12_data_in <= "00" & x"0000";\r
- thr_13_data_in <= "00" & x"0000";\r
- thr_14_data_in <= "00" & x"0000";\r
- thr_15_data_in <= "00" & x"0000";\r
\r
-- Reset\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
\r
- ----------------------------------------------------------------------------------------\r
- ----------------------------------------------------------------------------------------\r
- ----------------------------------------------------------------------------------------\r
- ----------------------------------------------------------------------------------------\r
\r
+\r
+ -- Tests may start now\r
----------------------------------------------------------------\r
-- "000" -> RAW128\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "000";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee00";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
buf_0_data_in(37 downto 30) <= x"81"; \r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"82"; \r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"83"; \r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
-\r
----------------------------------------------------------------\r
-- "001" -> PED128\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "001";\r
- wait until rising_edge(clk_in);\r
- reset_in <= '0';\r
- wait until rising_edge(clk_in);\r
- wait for 55 ns;\r
- wait until rising_edge(clk_in);\r
-\r
- -- EDS comes in\r
- eds_data_in <= x"01abcdee11";\r
- wait until rising_edge(clk_in);\r
- eds_avail_in <= '1';\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- eds_avail_in <= '0'; \r
- wait until rising_edge(clk_in);\r
- \r
- -- Buffer 0 becomes ready\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"81"; \r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"82"; \r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"83"; \r
- \r
- -- wait for first buffer \r
- wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
- wait until rising_edge(clk_in);\r
-\r
- ----------------------------------------------------------------\r
- -- "010" -> PED128THR\r
- ----------------------------------------------------------------\r
- wait until rising_edge(clk_in);\r
- reset_in <= '1';\r
- evt_type_in <= "010";\r
- wait until rising_edge(clk_in);\r
- reset_in <= '0';\r
- wait until rising_edge(clk_in);\r
- wait for 55 ns;\r
- wait until rising_edge(clk_in);\r
-\r
- -- EDS comes in\r
- eds_data_in <= x"01abcdee21";\r
- wait until rising_edge(clk_in);\r
- eds_avail_in <= '1';\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- eds_avail_in <= '0'; \r
- wait until rising_edge(clk_in);\r
- \r
- -- Buffer 0 becomes ready\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"81"; \r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"82"; \r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- wait until rising_edge(clk_in);\r
- buf_0_data_in(37 downto 30) <= x"83"; \r
- \r
- -- wait for first buffer \r
- wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
- wait until rising_edge(clk_in);\r
-\r
- ----------------------------------------------------------------------------------------\r
- ----------------------------------------------------------------------------------------\r
- ----------------------------------------------------------------------------------------\r
- ----------------------------------------------------------------------------------------\r
- wait; \r
-\r
- -- Tests may start now\r
- ----------------------------------------------------------------\r
- -- "000" -> RAW128\r
- ----------------------------------------------------------------\r
- wait until rising_edge(clk_in);\r
- reset_in <= '1';\r
- evt_type_in <= "000";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
----------------------------------------------------------------\r
- -- "001" -> PED128\r
+ -- "010" -> PED128THR\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "001";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee02";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
----------------------------------------------------------------\r
- -- "010" -> PED128THR\r
+ -- "011" -> RAW64\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "010";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee03";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
----------------------------------------------------------------\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "100";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee04";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
----------------------------------------------------------------\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "101";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee05";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
----------------------------------------------------------------\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "110";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee06";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
----------------------------------------------------------------\r
----------------------------------------------------------------\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
- evt_type_in <= "111";\r
wait until rising_edge(clk_in);\r
reset_in <= '0';\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
-- EDS comes in\r
- eds_data_in <= x"01abcdee01";\r
+ eds_data_in <= x"01abcdee07";\r
wait until rising_edge(clk_in);\r
eds_avail_in <= '1';\r
wait until rising_edge(clk_in);\r
\r
-- wait for first buffer \r
wait until rising_edge(buf_done_out);\r
- wait for 300 ns;\r
+ wait for 600 ns;\r
wait until rising_edge(clk_in);\r
\r
-\r
-\r
-\r
-\r
- \r
-- stay a while, stay forever!\r
wait; \r
+\r
end process TESTBENCH; \r
\r
-- Data faker for "APV 0"...\r
begin\r
if( rising_edge(clk_in) ) then\r
case thr_addr is\r
- when "0000000" => thr_0_data_in <= "00" & x"001e";\r
+-- when "0000000" => thr_0_data_in <= "00" & x"001e";\r
+ when "0000000" => thr_0_data_in <= "00" & x"ffff";\r
when "0000001" => thr_0_data_in <= "00" & x"100f"; \r
when "0000010" => thr_0_data_in <= "00" & x"201e"; \r
when "0000011" => thr_0_data_in <= "00" & x"300f"; \r
COMPONENT real_trg_handler\r
PORT(\r
CLK_IN : IN std_logic;\r
- CLEAR_IN : IN std_logic;\r
RESET_IN : IN std_logic;\r
TIME_TRG_IN : IN std_logic_vector(3 downto 0);\r
TRB_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_SETUP_IN : IN std_logic_vector(7 downto 0);\r
APV_TRGDONE_IN : IN std_logic;\r
TRG_3_TODO_IN : IN std_logic_vector(3 downto 0);\r
TRG_2_TODO_IN : IN std_logic_vector(3 downto 0);\r
TRB_TTAG_IN : IN std_logic_vector(15 downto 0);\r
TRB_TRND_IN : IN std_logic_vector(7 downto 0);\r
TRB_TTYPE_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TINFO_IN : IN std_logic_vector(23 downto 0);\r
TRB_TRGRCVD_IN : IN std_logic;\r
BUSY_RELEASE_IN : IN std_logic; \r
- TRB_MISMATCH_OUT : OUT std_logic;\r
+ LVL1_COUNTER_IN : IN std_logic_vector(15 downto 0);\r
+ LVL1_LD_COUNTER_IN : IN std_logic;\r
LVL1_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
APV_TRGSEL_OUT : OUT std_logic_vector(3 downto 0);\r
APV_TRGSTART_OUT : OUT std_logic;\r
EDS_READY_OUT : OUT std_logic;\r
DBG_FRMCTR_OUT : OUT std_logic_vector(3 downto 0);\r
BSM_OUT : OUT std_logic_vector(7 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ DEBUG_OUT : OUT std_logic_vector(63 downto 0)\r
);\r
END COMPONENT;\r
\r
SIGNAL CLK_IN : std_logic;\r
- SIGNAL CLEAR_IN : std_logic;\r
SIGNAL RESET_IN : std_logic;\r
SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0);\r
SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_SETUP_IN : std_logic_vector(7 downto 0);\r
SIGNAL APV_TRGDONE_IN : std_logic;\r
SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0);\r
SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0);\r
SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0);\r
SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0);\r
SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TINFO_IN : std_logic_vector(23 downto 0);\r
SIGNAL TRB_TRGRCVD_IN : std_logic;\r
- SIGNAL TRB_MISMATCH_OUT : std_logic;\r
+ SIGNAL LVL1_COUNTER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL LVL1_LD_COUNTER_IN : std_logic;\r
SIGNAL LVL1_COUNTER_OUT : std_logic_vector(15 downto 0);\r
SIGNAL BUSY_RELEASE_IN : std_logic;\r
SIGNAL APV_TRGSEL_OUT : std_logic_vector(3 downto 0);\r
SIGNAL EDS_READY_OUT : std_logic;\r
SIGNAL DBG_FRMCTR_OUT : std_logic_vector(3 downto 0);\r
SIGNAL BSM_OUT : std_logic_vector(7 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(63 downto 0);\r
\r
BEGIN\r
\r
-- Please check and add your generic clause manually\r
uut: real_trg_handler PORT MAP(\r
CLK_IN => CLK_IN,\r
- CLEAR_IN => CLEAR_IN,\r
RESET_IN => RESET_IN,\r
TIME_TRG_IN => TIME_TRG_IN,\r
TRB_TRG_IN => TRB_TRG_IN,\r
+ TRG_SETUP_IN => TRG_SETUP_IN,\r
APV_TRGDONE_IN => APV_TRGDONE_IN,\r
TRG_3_TODO_IN => TRG_3_TODO_IN,\r
TRG_2_TODO_IN => TRG_2_TODO_IN,\r
TRB_TRND_IN => TRB_TRND_IN,\r
TRB_TTYPE_IN => TRB_TTYPE_IN,\r
TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
- TRB_MISMATCH_OUT => TRB_MISMATCH_OUT,\r
+ TRB_TINFO_IN => TRB_TINFO_IN,\r
+ LVL1_COUNTER_IN => LVL1_COUNTER_IN,\r
+ LVL1_LD_COUNTER_IN => LVL1_LD_COUNTER_IN,\r
LVL1_COUNTER_OUT => LVL1_COUNTER_OUT,\r
BUSY_RELEASE_IN => BUSY_RELEASE_IN,\r
APV_TRGSEL_OUT => APV_TRGSEL_OUT,\r
THE_TEST_BENCH: process\r
begin\r
-- Setup signals\r
- clear_in <= '0'; \r
reset_in <= '0';\r
time_trg_in <= x"0"; \r
trb_trg_in <= x"0";\r
+ trg_setup_in <= x"00";\r
apv_trgdone_in <= '0';\r
trg_3_todo_in <= x"0";\r
trg_2_todo_in <= x"3";\r
trg_1_todo_in <= x"2";\r
trg_0_todo_in <= x"1";\r
- trb_ttag_in <= x"dead";\r
- trb_trnd_in <= x"fc";\r
- trb_ttype_in <= x"1";\r
+ trb_ttag_in <= x"0000";\r
+ trb_trnd_in <= x"00";\r
+ trb_ttype_in <= x"0";\r
+ trb_tinfo_in <= x"00_00_00";\r
trb_trgrcvd_in <= '0';\r
busy_release_in <= '0';\r
+ lvl1_counter_in <= x"affe";\r
+ lvl1_ld_counter_in <= '0';\r
-- Reset all\r
- clear_in <= '1'; wait for 50 ns;\r
- clear_in <= '0'; wait for 50 ns;\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
reset_in <= '1';\r
wait until rising_edge(clk_in);\r
-- Tests may start here\r
\r
+ -- Load the local counter with TRBnet value\r
+ wait until rising_edge(clk_in);\r
+ lvl1_ld_counter_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ lvl1_ld_counter_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 200 ns;\r
+\r
+ -- Check missing timing trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_ttag_in <= x"affe";\r
+ trb_trnd_in <= x"a0";\r
+ trb_ttype_in <= x"1";\r
+ trb_tinfo_in <= x"ff_00_00";\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
wait until rising_edge(clk_in);\r
+ \r
+ wait until rising_edge(eds_we_out);\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '1';\r
+ \r
+ wait until rising_edge(eds_ready_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ busy_release_in <= '0';\r
wait until rising_edge(clk_in);\r
+ trb_ttag_in <= x"0000";\r
+ trb_trnd_in <= x"00";\r
+ trb_ttype_in <= x"0";\r
+ trb_tinfo_in <= x"00_00_00"; \r
wait until rising_edge(clk_in);\r
\r
+ wait for 400 ns;\r
+\r
+ -- Check timingtriggerless trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_ttag_in <= x"afff";\r
+ trb_trnd_in <= x"c7";\r
+ trb_ttype_in <= x"9";\r
+ trb_tinfo_in <= x"ff_00_80";\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ \r
+ wait until rising_edge(eds_we_out);\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '1';\r
+ \r
+ wait until rising_edge(eds_ready_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ busy_release_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ trb_ttag_in <= x"0000";\r
+ trb_trnd_in <= x"00";\r
+ trb_ttype_in <= x"0";\r
+ trb_tinfo_in <= x"00_00_00"; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ \r
+ wait;\r
\r
-- First sync trigger\r
wait until rising_edge(clk_in);\r
wait until rising_edge(clk_in);\r
\r
\r
+\r
+\r
-- Stay a while, stay forever.\r
wait;\r
\r
package version is
- constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1264600226,32);
+ constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1272371189,32);
end package version;
jspc29 / adcm.git / commitdiff