+++ /dev/null
-#Address # S/N # FPGA #
-###################################################
-#Plane 0, Sector 0
-
- 0x8e00 0 5
- 0x1000 0 0
- 0x1001 0 1
-
- 0x8e01 0 5
- 0x1010 0 0
- 0x1011 0 1
-
- 0x8e02 0 5
- 0x1020 0 0
- 0x1021 0 1
- 0x1022 0 2
-
-
-
-
-
-
-
- OEP FPGA:
-
- 1 digit: 8 (as for all hubs)
- 2 digit: e/f (inner/outer MDC)
- 3 digit: 0..b (chamber number, 0..5 for MDC1/3 6..B for MDC2/4)
- 4 digit: 0..f (MBO number)
-
-TDC FPGA:
-
- 1 digit: 1/2 (inner/outer MDC)
- 2 digit: 0..b (chamber number, 0..5 for MDC1/3 6..B for MDC2/4)
- 3 digit: 0..f (MBO number)
- 4 digit: 0..2 (FPGA number)
-
-Hub FPGA:
-
- 1 digit: 8 (as for all hubs)
- 2 digit: 5
- 3 digit: 0..b (crate number, 0..5 inner MDC, 6..b outer MDC sectors)
- 4 digit FPGA number in crate (0:master & Subevent ID)
#Scripts#
* `generate_pasttrec_settings.pl` prepares data from common baseline database
- * loads settings to FPGA directly
- * writes trbcmd files for later writing to Flash ROM
- * settings are written for boards currently in the system (otherwise serial number / uid can't be matched to addresses)
- * default PASTTREC registers are currently hardcoded (!)
+ * loads settings to FPGA directly
+ * writes trbcmd files for later writing to Flash ROM
+ * settings are written for boards currently in the system (otherwise serial number / uid can't be matched to addresses)
+ * default PASTTREC registers are currently hardcoded (!)
* `merge_and_flash_settings.pl` generates and loads settings from the 'settings' directory to the FPGAs flashes
* `generate_address_settings.pl` makes the files needed to automatically set the board addresses from Flash ROM
+* `pasttrec_set_threshold.pl` sets an identical threshold to all Pasttrec (temporarily)
+
+* `pasttrec_baseline_finder.pl` basic baseline finder script
+
+* `generate_address_list.pl` takes the list of installed MBO serial numbers and generates the address.db file for DAQ
##Notes##
All scripts assume that the daqtool repository is available next to this repository.
--- /dev/null
+#!/usr/bin/perl -w
+use warnings;
+no warnings "portable";
+use FileHandle;
+use Getopt::Long;
+use Data::Dumper;
+
+my $DEBUG = 0; #print debug messages
+
+my $boards;
+my $longs;
+
+
+###############################################################################
+#Read file with list of installed boards & MBO size
+###############################################################################
+open FILE, "../installation/mbo_positions.db" or die $!."\nmbo_positions.db not found.";
+while (my $a = <FILE>) {
+ if(my @values = $a =~ /^\s*(\d)\s+(\d)\s+(\d+)\s+(\d)\s+(\d+)\s*/) {
+ my $p = shift @values;
+ my $s = shift @values;
+ my $b = shift @values;
+ my $long = shift @values;
+ my $id = shift @values;
+
+ $boards->[$p][$s][$b] = $id;
+ $longs->[$p][$s][$b] = $long;
+ }
+ }
+close FILE;
+
+###############################################################################
+#Generate list with all 1236 board addressess
+###############################################################################
+open(FILE, '>', "../settings_oep/auto/addresses_mdc.db") or die $!;
+
+print FILE "\n\n#This file is generated automatically. DO NOT EDIT.\n\n";
+print FILE "#Address # S/N # FPGA #\n";
+print FILE "###################################################\n";
+
+foreach my $p (0..3) {
+ foreach my $s (0..5) {
+ foreach my $b (0..15) {
+
+ my $str;
+
+ my $addr = 0x8000 + ($p<2?0x0e00:0x0f00) + ($p%2 ? $s*16+96 : $s*16) + $b;
+ $str .= sprintf(" 0x%04x %03i %i\n",$addr,$boards->[$p][$s][$b],5);
+
+ $addr = ($p<2?0x1000:0x2000) + ($p%2 ? $s*256+6*256 : $s*256) + $b*16 + 0;
+ $str .= sprintf(" 0x%04x %03i %i\n",$addr,$boards->[$p][$s][$b],0);
+
+ $addr = ($p<2?0x1000:0x2000) + ($p%2 ? $s*256+6*256 : $s*256) + $b*16 + 1;
+ $str .= sprintf(" 0x%04x %03i %i\n",$addr,$boards->[$p][$s][$b],1);
+
+ if($longs->[$p][$s][$b]) {
+ $addr = ($p<2?0x1000:0x2000) + ($p%2 ? $s*256+6*256 : $s*256) + $b*16 + 2;
+ $str .= sprintf(" 0x%04x %03i %i\n",$addr,$boards->[$p][$s][$b],2);
+ };
+
+ print FILE $str;
+ last if $p == 0 && $b == 13;
+ }
+ print FILE "\n";
+ }
+ print FILE "\n";
+ }
+
+close FILE;
+
+
+__END__
+
+
+###############################################################################
+#Addressing scheme
+###############################################################################
+
+ OEP FPGA:
+
+ 1 digit: 8 (as for all hubs)
+ 2 digit: e/f (inner/outer MDC)
+ 3 digit: 0..b (chamber number, 0..5 for MDC1/3 6..B for MDC2/4)
+ 4 digit: 0..f (MBO number)
+
+TDC FPGA:
+
+ 1 digit: 1/2 (inner/outer MDC)
+ 2 digit: 0..b (chamber number, 0..5 for MDC1/3 6..B for MDC2/4)
+ 3 digit: 0..f (MBO number)
+ 4 digit: 0..2 (FPGA number)
+
+Hub FPGA:
+
+ 1 digit: 8 (as for all hubs)
+ 2 digit: 5
+ 3 digit: 0..b (crate number, 0..5 inner MDC, 6..b outer MDC sectors)
+ 4 digit FPGA number in crate (0:master & Subevent ID)
jspc29 / hades_mdc_settings.git / commitdiff