minor changes to get things working :)

diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
index 24dd7f1fce6d4919f23a87f4a94261dca0debaba..9213c98f1ba49173d23d4ef2f797ae893996d878 100644 (file)
--- a/backplanemaster/trb3sc_master.vhd
+++ b/backplanemaster/trb3sc_master.vhd
@@ -198,6 +198,8 @@ architecture trb3sc_arch of trb3sc_master is
   signal send_rst_word_i             : std_logic_vector(7 downto 0);
   signal send_dlm_word_i             : std_logic_vector(7 downto 0);
 
+  signal init_quad         : std_logic;
+
 begin
 
 ---------------------------------------------------------------------------
@@ -225,6 +227,8 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     DEBUG_OUT         => debug_clock_reset
   );
 
+  init_quad <= not GSR_N;
+  
 ---------------------------------------------------------------------------
 -- PCBSB: TrbNet Uplink
 ---------------------------------------------------------------------------
@@ -237,6 +241,7 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS
     CLK_REF_FULL                  => CLK_SUPPL_PCLK,
     SYSCLK                        => clk_sys,
     RESET                         => reset_i,
+    CLEAR                         => init_quad,
     -- Media Interface TX/RX
     MEDIA_MED2INT(0 to 2)         => open,
     MEDIA_MED2INT(3)              => med2int(4),
@@ -305,7 +310,7 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS
 ---------------------------------------------------------------------------
   THE_MAIN_TX_RST: main_tx_reset_RS
   port map (
-    CLEAR                => '0',
+    CLEAR                => init_quad,
     CLK_REF              => CLK_SUPPL_PCLK,
     TX_PLL_LOL_QD_A_IN   => tx_pll_lol_qd_a_i,
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
@@ -330,6 +335,7 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_125M_RS
     CLK_REF_FULL       => CLK_SUPPL_PCLK,
     SYSCLK             => clk_sys,
     RESET              => reset_i,
+    CLEAR              => init_quad,
     -- Media Interface TX/RX
     MEDIA_MED2INT(0)   => med2int(0),
     MEDIA_MED2INT(1)   => med2int(1),

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 2cedc6b2eb64348e3515254d726a75cad76a36fb..eebd87c0d1ea1145c6383b1ba74152289d8a51d8 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -257,7 +257,9 @@ architecture trb3sc_arch of trb3sc_cts is
   signal slv_act_cnt                 : unsigned(15 downto 0);
   signal slave_active_fake           : std_logic;
   signal send_reset_i                : std_logic;
-  
+
+  signal init_quad         : std_logic;
+
 begin
 
   THE_TIME_COUNTER_PROC: process( clk_full_osc )
@@ -292,6 +294,8 @@ begin
     DEBUG_OUT         => debug_clock_reset
   );
 
+  init_quad <= not GSR_N;
+  
 -- Reset by GbE: a minimum delay of 1us is kept before the reset 
 -- pulse is injected into the reset handler.
   PROC_MAKE_RESET : process 
@@ -356,6 +360,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       -- Clocks and reset
       CLK_REF_FULL                => CLK_SUPPL_PCLK,
       SYSCLK                      => clk_sys,
+      CLEAR                       => init_quad,
       RESET                       => reset_i,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0 to 2)       => open, 
@@ -408,7 +413,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
 
   THE_MAIN_TX_RST: main_tx_reset_RS
   port map (
-    CLEAR                => '0', -- DO NOT USE
+    CLEAR                => init_quad,
     CLK_REF              => CLK_SUPPL_PCLK,
     TX_PLL_LOL_QD_A_IN   => '0',
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,

diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd
index 3bf1e27ba43d34358ffc1cd8126de0d2b2dd1fde..d2189a8b38e1deb5515e9ff050fc85322ec95d68 100644 (file)
--- a/hub/trb3sc_hub.vhd
+++ b/hub/trb3sc_hub.vhd
@@ -180,7 +180,9 @@ architecture trb3sc_arch of trb3sc_hub is
   signal send_rst_i                  : std_logic;
   signal send_rst_word_i             : std_logic_vector(7 downto 0);
   signal send_dlm_word_i             : std_logic_vector(7 downto 0);
-  
+
+  signal init_quad         : std_logic;
+
 begin
 ---------------------------------------------------------------------------
 -- Clock & Reset Handling
@@ -207,7 +209,8 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     DEBUG_OUT         => debug_clock_reset
   );
 
-
+  init_quad <= not GSR_N;
+  
 ---------------------------------------------------------------------------
 -- PCSA: Uplink when backplane is used
 ---------------------------------------------------------------------------    
@@ -221,6 +224,7 @@ gen_PCSA : if USE_BACKPLANE = c_YES generate
       CLK_REF_FULL                  => CLK_SUPPL_PCLK,
       SYSCLK                        => clk_sys,
       RESET                         => reset_i,
+      CLEAR                         => init_quad,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)              => med2int(INTERFACE_NUM-1),
       MEDIA_MED2INT(1 to 3)         => open,
@@ -282,6 +286,7 @@ gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate
       CLK_REF_FULL       => CLK_SUPPL_PCLK,
       SYSCLK             => clk_sys,
       RESET              => reset_i,
+      CLEAR              => init_quad,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => med2int(4),
       MEDIA_MED2INT(1)   => med2int(5),
@@ -354,6 +359,7 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate
       CLK_REF_FULL       => CLK_SUPPL_PCLK,
       SYSCLK             => clk_sys,
       RESET              => reset_i,
+      CLEAR              => init_quad,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => med2int(4),
       MEDIA_MED2INT(1)   => med2int(5),
@@ -419,7 +425,7 @@ end generate;
 
   THE_MAIN_TX_RST: main_tx_reset_RS
   port map (
-    CLEAR                => '0',
+    CLEAR                => init_quad,
     CLK_REF              => CLK_SUPPL_PCLK,
     TX_PLL_LOL_QD_A_IN   => tx_pll_lol_qd_a_i,
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
@@ -444,6 +450,7 @@ end generate;
       CLK_REF_FULL       => CLK_SUPPL_PCLK,
       SYSCLK             => clk_sys,
       RESET              => reset_i,
+      CLEAR              => init_quad,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => med2int(2),
       MEDIA_MED2INT(1)   => med2int(3),
@@ -512,6 +519,7 @@ gen_PCSD : if INCLUDE_GBE = c_NO generate
       CLK_REF_FULL       => CLK_SUPPL_PCLK,
       SYSCLK             => clk_sys,
       RESET              => reset_i,
+      CLEAR              => init_quad,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => med2int(8),
       MEDIA_MED2INT(1)   => med2int(7),

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index 02e5249bf38a2dea55e4c5c39e25cd2f3125cc04..73a35e46e9aaf080307228ea0317672e0f773c70 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -162,7 +162,7 @@ architecture trb3sc_arch of trb3sc_tdctemplate is
   signal send_rst_word_i   : std_logic_vector(7 downto 0);
   signal send_dlm_word_i   : std_logic_vector(7 downto 0);
 
-  signal kill_quad         : std_logic;
+  signal init_quad         : std_logic;
 
 begin
 
@@ -191,7 +191,7 @@ begin
       DEBUG_OUT         => debug_clock_reset
     );
 
-    kill_quad <= not GSR_N;
+    init_quad <= not GSR_N;
     
 gen_cal125 : if (USE_CALIBRATION_200MHZ = c_NO) generate  
   pll_calibration : entity work.pll_in125_out33
@@ -222,7 +222,7 @@ end generate;
       -- Clocks and reset
       CLK_REF_FULL       => CLK_SUPPL_PCLK,
       SYSCLK             => clk_sys,
-      CLEAR              => kill_quad,
+      CLEAR              => init_quad,
       RESET              => reset_i,
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => open, 
@@ -285,7 +285,7 @@ end generate;
 
   THE_MAIN_TX_RST: main_tx_reset_RS
   port map (
-    CLEAR                => kill_quad, --'0',
+    CLEAR                => init_quad,
     CLK_REF              => CLK_SUPPL_PCLK,
     TX_PLL_LOL_QD_A_IN   => '0',
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,