<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 27 11:44:02.265" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 03 15:52:30.411" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 08 27 11:44:00.000"/>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 12 03 15:52:28.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2014 12 03 15:52:28.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2014 12 03 15:52:29.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2014 12 03 15:52:28.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 12 03 15:52:28.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 12 03 15:52:28.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PCS
-CoreRevision=8.1
+CoreRevision=8.2
ModuleName=serdes_sync_upstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=08/27/2014
-Time=11:44:00
+Date=12/03/2014
+Time=15:52:28
[Parameters]
Verilog=0
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "sfp_1_125_int.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+--THIS MODULE IS INSTANTIATED PER RX CHANNEL
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity sfp_1_125_intrx_reset_sm is
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end sfp_1_125_intrx_reset_sm ;
+
+architecture rx_reset_sm_arch of sfp_1_125_intrx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+
+signal tx_pll_lol_qd_s_int: std_logic;
+signal rx_los_low_int: std_logic;
+signal plol_los_int: std_logic;
+signal rx_lol_los : std_logic;
+signal rx_lol_los_int: std_logic;
+signal rx_lol_los_del: std_logic;
+signal rx_pcs_rst_ch_c_int: std_logic;
+signal rx_serdes_rst_ch_c_int: std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(1 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2 : std_logic;
+signal rstn_m1: std_logic;
+signal rstn_m2: std_logic;
+signal sync_rst_n: std_logic;
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ rstn_m1 <= '0';
+ rstn_m2 <= '0';
+ else if rising_edge(refclkdiv2) then
+ rstn_m1 <= '1';
+ rstn_m2 <= rstn_m1;
+ end if;
+ end if;
+end process;
+
+ sync_rst_n <= rstn_m2;
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2, sync_rst_n)
+begin
+ if sync_rst_n = '0' then
+ cs <= WAIT_FOR_PLOL;
+ rx_lol_los_int <= '1';
+ rx_lol_los_del <= '1';
+ tx_pll_lol_qd_s_int <= '1';
+ rx_pcs_rst_ch_c <= '1';
+ rx_serdes_rst_ch_c <= '0';
+ rx_los_low_int <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ rx_lol_los_del <= rx_lol_los;
+ rx_lol_los_int <= rx_lol_los_del;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+ rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+ rx_los_low_int <= rx_los_low_ch_s;
+ end if;
+ end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "00";
+ TIMER1 <= '0';
+ else
+ if counter1(1) = '1' then
+ TIMER1 <='1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(count_index) = '1' then
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+ when WAIT_FOR_PLOL =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
+ ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
+ else
+ ns <= RX_SERDES_RESET;
+ end if;
+
+ when RX_SERDES_RESET =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+
+ when WAIT_FOR_TIMER1 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_LOL_LOS;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_LOL_LOS =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
+ if TIMER2 = '1' then
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+ else
+ ns <= CHECK_LOL_LOS; --RESET TIMER2
+ end if;
+
+ when NORMAL =>
+ rx_pcs_rst_ch_c_int <= '0';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= WAIT_FOR_PLOL;
+
+ end case;
+
+end process;
+
+
+end rx_reset_sm_arch;
+
+--THIS MODULE IS INSTANTIATED PER TX QUAD
+--TX Reset Sequence state machine--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity sfp_1_125_inttx_reset_sm is
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rst_qd_c : out std_logic;
+ tx_pcs_rst_ch_c : out std_logic
+ );
+end sfp_1_125_inttx_reset_sm;
+
+architecture tx_reset_sm_arch of sfp_1_125_inttx_reset_sm is
+
+type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+
+signal tx_pll_lol_qd_s_int : std_logic;
+signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
+signal rst_qd_c_int : std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(2 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2: std_logic;
+
+signal rstn_m1: std_logic;
+signal rstn_m2: std_logic;
+signal sync_rst_n: std_logic;
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ rstn_m1 <= '0';
+ rstn_m2 <= '0';
+ else if rising_edge(refclkdiv2) then
+ rstn_m1 <= '1';
+ rstn_m2 <= rstn_m1;
+ end if;
+ end if;
+end process;
+
+ sync_rst_n <= rstn_m2;
+process (refclkdiv2, sync_rst_n)
+begin
+ if sync_rst_n = '0' then
+ cs <= QUAD_RESET;
+ tx_pll_lol_qd_s_int <= '1';
+ tx_pcs_rst_ch_c <= '1';
+ rst_qd_c <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
+ rst_qd_c <= rst_qd_c_int;
+ end if;
+ end if;
+end process;
+--TIMER1 = 20ns;
+--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
+-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
+
+
+process (refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "000";
+ TIMER1 <= '0';
+ else
+ if counter1(2) = '1' then
+ TIMER1 <= '1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+--TIMER2 = 1,400,000 UI;
+--WORST CASE CYCLES is with smallest multipier factor.
+-- This would be with X8 clock multiplier in DIV2 mode
+-- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
+-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
+-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(count_index) = '1' then
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
+begin
+
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+
+ when QUAD_RESET =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+ when WAIT_FOR_TIMER1 =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_PLOL;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_PLOL =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '0';
+ if TIMER2 = '1' then
+ if tx_pll_lol_qd_s_int = '1' then
+ ns <= QUAD_RESET;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+
+ when NORMAL =>
+ tx_pcs_rst_ch_c_int <= "0000";
+ rst_qd_c_int <= '0';
+ if tx_pll_lol_qd_s_int = '1' then
+ ns <= QUAD_RESET;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= QUAD_RESET;
+
+ end case;
+
+end process;
+
+end tx_reset_sm_arch;
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity sfp_1_125_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_1_125_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end sfp_1_125_int;
+
+
+architecture sfp_1_125_int_arch of sfp_1_125_int is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+component sfp_1_125_intrx_reset_sm
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end component ;
+
+component sfp_1_125_inttx_reset_sm
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rst_qd_c : out std_logic;
+ tx_pcs_rst_ch_c : out std_logic
+ );
+end component;
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch1_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+signal rx_serdes_rst_ch1_c : std_logic;
+signal rx_pcs_rst_ch1_c : std_logic;
+
+-- reset sequence for rx
+signal refclkdiv2_rx_ch1 : std_logic;
+
+signal refclkdiv2_tx_ch : std_logic;
+signal tx_pcs_rst_ch_c : std_logic;
+signal rst_qd_c : std_logic;
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ refclk2fpga <= refclk2fpga_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpsc_vlo,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => open,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+ HDOUTP1 => hdoutp_ch1,
+ HDOUTN1 => hdoutn_ch1,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => sci_sel_ch1,
+ SCIENCH1 => fpsc_vhi,
+ FF_RXI_CLK_1 => rxiclk_ch1,
+ FF_TXI_CLK_1 => txiclk_ch1,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+ FF_TX_H_CLK_1 => tx_half_clk_ch1,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => txdata_ch1(0),
+ FF_TX_D_1_1 => txdata_ch1(1),
+ FF_TX_D_1_2 => txdata_ch1(2),
+ FF_TX_D_1_3 => txdata_ch1(3),
+ FF_TX_D_1_4 => txdata_ch1(4),
+ FF_TX_D_1_5 => txdata_ch1(5),
+ FF_TX_D_1_6 => txdata_ch1(6),
+ FF_TX_D_1_7 => txdata_ch1(7),
+ FF_TX_D_1_8 => tx_k_ch1(0),
+ FF_TX_D_1_9 => tx_force_disp_ch1(0),
+ FF_TX_D_1_10 => tx_disp_sel_ch1(0),
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => txdata_ch1(8),
+ FF_TX_D_1_13 => txdata_ch1(9),
+ FF_TX_D_1_14 => txdata_ch1(10),
+ FF_TX_D_1_15 => txdata_ch1(11),
+ FF_TX_D_1_16 => txdata_ch1(12),
+ FF_TX_D_1_17 => txdata_ch1(13),
+ FF_TX_D_1_18 => txdata_ch1(14),
+ FF_TX_D_1_19 => txdata_ch1(15),
+ FF_TX_D_1_20 => tx_k_ch1(1),
+ FF_TX_D_1_21 => tx_force_disp_ch1(1),
+ FF_TX_D_1_22 => tx_disp_sel_ch1(1),
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1(0),
+ FF_RX_D_1_9 => rx_disp_err_ch1(0),
+ FF_RX_D_1_10 => rx_cv_err_ch1(0),
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => rxdata_ch1(8),
+ FF_RX_D_1_13 => rxdata_ch1(9),
+ FF_RX_D_1_14 => rxdata_ch1(10),
+ FF_RX_D_1_15 => rxdata_ch1(11),
+ FF_RX_D_1_16 => rxdata_ch1(12),
+ FF_RX_D_1_17 => rxdata_ch1(13),
+ FF_RX_D_1_18 => rxdata_ch1(14),
+ FF_RX_D_1_19 => rxdata_ch1(15),
+ FF_RX_D_1_20 => rx_k_ch1(1),
+ FF_RX_D_1_21 => rx_disp_err_ch1(1),
+ FF_RX_D_1_22 => rx_cv_err_ch1(1),
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+ FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
+ FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ HDINP3 => fpsc_vlo,
+ HDINN3 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => fpsc_vlo,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => open,
+ FF_RX_H_CLK_3 => open,
+ FF_TX_F_CLK_3 => open,
+ FF_TX_H_CLK_3 => open,
+ FFC_CK_CORE_RX_3 => fpsc_vlo,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => open,
+ FF_RX_D_3_1 => open,
+ FF_RX_D_3_2 => open,
+ FF_RX_D_3_3 => open,
+ FF_RX_D_3_4 => open,
+ FF_RX_D_3_5 => open,
+ FF_RX_D_3_6 => open,
+ FF_RX_D_3_7 => open,
+ FF_RX_D_3_8 => open,
+ FF_RX_D_3_9 => open,
+ FF_RX_D_3_10 => open,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => fpsc_vlo,
+ FFC_RXPWDNB_3 => fpsc_vlo,
+ FFS_RLOS_LO_3 => open,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => open,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => open,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => fpsc_vlo,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => fpsc_vlo,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+-- reset sequence for rx
+
+ P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch1 <= '0';
+ ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
+ refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch1 : sfp_1_125_intrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch1,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
+ rx_los_low_ch_s => rx_los_low_ch1_sig,
+ tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
+
+
+
+
+ P5 : PROCESS(fpga_txrefclk, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_tx_ch <= '0';
+ ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
+ refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
+ END IF;
+ END PROCESS;
+
+-- reset sequence for tx
+tx_reset_sm_ch : sfp_1_125_inttx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ rst_n => rst_n,
+ refclkdiv2 => refclkdiv2_tx_ch,
+ tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+ rst_qd_c => rst_qd_c,
+ tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
+ );
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end sfp_1_125_int_arch ;
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "sfp_1_200_int.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+--THIS MODULE IS INSTANTIATED PER RX CHANNEL
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity sfp_1_200_intrx_reset_sm is
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end sfp_1_200_intrx_reset_sm ;
+
+architecture rx_reset_sm_arch of sfp_1_200_intrx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+
+signal tx_pll_lol_qd_s_int: std_logic;
+signal rx_los_low_int: std_logic;
+signal plol_los_int: std_logic;
+signal rx_lol_los : std_logic;
+signal rx_lol_los_int: std_logic;
+signal rx_lol_los_del: std_logic;
+signal rx_pcs_rst_ch_c_int: std_logic;
+signal rx_serdes_rst_ch_c_int: std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(1 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2 : std_logic;
+signal rstn_m1: std_logic;
+signal rstn_m2: std_logic;
+signal sync_rst_n: std_logic;
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ rstn_m1 <= '0';
+ rstn_m2 <= '0';
+ else if rising_edge(refclkdiv2) then
+ rstn_m1 <= '1';
+ rstn_m2 <= rstn_m1;
+ end if;
+ end if;
+end process;
+
+ sync_rst_n <= rstn_m2;
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2, sync_rst_n)
+begin
+ if sync_rst_n = '0' then
+ cs <= WAIT_FOR_PLOL;
+ rx_lol_los_int <= '1';
+ rx_lol_los_del <= '1';
+ tx_pll_lol_qd_s_int <= '1';
+ rx_pcs_rst_ch_c <= '1';
+ rx_serdes_rst_ch_c <= '0';
+ rx_los_low_int <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ rx_lol_los_del <= rx_lol_los;
+ rx_lol_los_int <= rx_lol_los_del;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+ rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+ rx_los_low_int <= rx_los_low_ch_s;
+ end if;
+ end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "00";
+ TIMER1 <= '0';
+ else
+ if counter1(1) = '1' then
+ TIMER1 <='1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(count_index) = '1' then
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+ when WAIT_FOR_PLOL =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
+ ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
+ else
+ ns <= RX_SERDES_RESET;
+ end if;
+
+ when RX_SERDES_RESET =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+
+ when WAIT_FOR_TIMER1 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_LOL_LOS;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_LOL_LOS =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
+ if TIMER2 = '1' then
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+ else
+ ns <= CHECK_LOL_LOS; --RESET TIMER2
+ end if;
+
+ when NORMAL =>
+ rx_pcs_rst_ch_c_int <= '0';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= WAIT_FOR_PLOL;
+
+ end case;
+
+end process;
+
+
+end rx_reset_sm_arch;
+
+--THIS MODULE IS INSTANTIATED PER TX QUAD
+--TX Reset Sequence state machine--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity sfp_1_200_inttx_reset_sm is
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rst_qd_c : out std_logic;
+ tx_pcs_rst_ch_c : out std_logic
+ );
+end sfp_1_200_inttx_reset_sm;
+
+architecture tx_reset_sm_arch of sfp_1_200_inttx_reset_sm is
+
+type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+
+signal tx_pll_lol_qd_s_int : std_logic;
+signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
+signal rst_qd_c_int : std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(2 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2: std_logic;
+
+signal rstn_m1: std_logic;
+signal rstn_m2: std_logic;
+signal sync_rst_n: std_logic;
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ rstn_m1 <= '0';
+ rstn_m2 <= '0';
+ else if rising_edge(refclkdiv2) then
+ rstn_m1 <= '1';
+ rstn_m2 <= rstn_m1;
+ end if;
+ end if;
+end process;
+
+ sync_rst_n <= rstn_m2;
+process (refclkdiv2, sync_rst_n)
+begin
+ if sync_rst_n = '0' then
+ cs <= QUAD_RESET;
+ tx_pll_lol_qd_s_int <= '1';
+ tx_pcs_rst_ch_c <= '1';
+ rst_qd_c <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
+ rst_qd_c <= rst_qd_c_int;
+ end if;
+ end if;
+end process;
+--TIMER1 = 20ns;
+--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
+-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
+
+
+process (refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "000";
+ TIMER1 <= '0';
+ else
+ if counter1(2) = '1' then
+ TIMER1 <= '1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+--TIMER2 = 1,400,000 UI;
+--WORST CASE CYCLES is with smallest multipier factor.
+-- This would be with X8 clock multiplier in DIV2 mode
+-- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
+-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
+-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(count_index) = '1' then
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
+begin
+
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+
+ when QUAD_RESET =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+ when WAIT_FOR_TIMER1 =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_PLOL;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_PLOL =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '0';
+ if TIMER2 = '1' then
+ if tx_pll_lol_qd_s_int = '1' then
+ ns <= QUAD_RESET;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+
+ when NORMAL =>
+ tx_pcs_rst_ch_c_int <= "0000";
+ rst_qd_c_int <= '0';
+ if tx_pll_lol_qd_s_int = '1' then
+ ns <= QUAD_RESET;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= QUAD_RESET;
+
+ end case;
+
+end process;
+
+end tx_reset_sm_arch;
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity sfp_1_200_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_1_200_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end sfp_1_200_int;
+
+
+architecture sfp_1_200_int_arch of sfp_1_200_int is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+component sfp_1_200_intrx_reset_sm
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end component ;
+
+component sfp_1_200_inttx_reset_sm
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rst_qd_c : out std_logic;
+ tx_pcs_rst_ch_c : out std_logic
+ );
+end component;
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch1_sig : std_logic;
+signal tx_full_clk_ch3_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+signal rx_serdes_rst_ch1_c : std_logic;
+signal rx_serdes_rst_ch3_c : std_logic;
+signal rx_pcs_rst_ch1_c : std_logic;
+signal rx_pcs_rst_ch3_c : std_logic;
+
+-- reset sequence for rx
+signal refclkdiv2_rx_ch1 : std_logic;
+signal refclkdiv2_rx_ch3 : std_logic;
+
+signal refclkdiv2_tx_ch : std_logic;
+signal tx_pcs_rst_ch_c : std_logic;
+signal rst_qd_c : std_logic;
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ refclk2fpga <= refclk2fpga_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpsc_vlo,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => open,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+ HDOUTP1 => hdoutp_ch1,
+ HDOUTN1 => hdoutn_ch1,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => sci_sel_ch1,
+ SCIENCH1 => fpsc_vhi,
+ FF_RXI_CLK_1 => rxiclk_ch1,
+ FF_TXI_CLK_1 => txiclk_ch1,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+ FF_TX_H_CLK_1 => tx_half_clk_ch1,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => txdata_ch1(0),
+ FF_TX_D_1_1 => txdata_ch1(1),
+ FF_TX_D_1_2 => txdata_ch1(2),
+ FF_TX_D_1_3 => txdata_ch1(3),
+ FF_TX_D_1_4 => txdata_ch1(4),
+ FF_TX_D_1_5 => txdata_ch1(5),
+ FF_TX_D_1_6 => txdata_ch1(6),
+ FF_TX_D_1_7 => txdata_ch1(7),
+ FF_TX_D_1_8 => tx_k_ch1(0),
+ FF_TX_D_1_9 => tx_force_disp_ch1(0),
+ FF_TX_D_1_10 => tx_disp_sel_ch1(0),
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => txdata_ch1(8),
+ FF_TX_D_1_13 => txdata_ch1(9),
+ FF_TX_D_1_14 => txdata_ch1(10),
+ FF_TX_D_1_15 => txdata_ch1(11),
+ FF_TX_D_1_16 => txdata_ch1(12),
+ FF_TX_D_1_17 => txdata_ch1(13),
+ FF_TX_D_1_18 => txdata_ch1(14),
+ FF_TX_D_1_19 => txdata_ch1(15),
+ FF_TX_D_1_20 => tx_k_ch1(1),
+ FF_TX_D_1_21 => tx_force_disp_ch1(1),
+ FF_TX_D_1_22 => tx_disp_sel_ch1(1),
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1(0),
+ FF_RX_D_1_9 => rx_disp_err_ch1(0),
+ FF_RX_D_1_10 => rx_cv_err_ch1(0),
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => rxdata_ch1(8),
+ FF_RX_D_1_13 => rxdata_ch1(9),
+ FF_RX_D_1_14 => rxdata_ch1(10),
+ FF_RX_D_1_15 => rxdata_ch1(11),
+ FF_RX_D_1_16 => rxdata_ch1(12),
+ FF_RX_D_1_17 => rxdata_ch1(13),
+ FF_RX_D_1_18 => rxdata_ch1(14),
+ FF_RX_D_1_19 => rxdata_ch1(15),
+ FF_RX_D_1_20 => rx_k_ch1(1),
+ FF_RX_D_1_21 => rx_disp_err_ch1(1),
+ FF_RX_D_1_22 => rx_cv_err_ch1(1),
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+ FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
+ FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => sci_sel_ch3,
+ SCIENCH3 => fpsc_vhi,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => txiclk_ch3,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => tx_force_disp_ch3,
+ FF_TX_D_3_10 => tx_disp_sel_ch3,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => tx_sync_qd_c,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+-- reset sequence for rx
+
+ P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch1 <= '0';
+ ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
+ refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch1 : sfp_1_200_intrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch1,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
+ rx_los_low_ch_s => rx_los_low_ch1_sig,
+ tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
+
+
+ P4 : PROCESS(fpga_rxrefclk_ch3, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch3 <= '0';
+ ELSIF (fpga_rxrefclk_ch3'event and fpga_rxrefclk_ch3 = '1') THEN
+ refclkdiv2_rx_ch3 <= not refclkdiv2_rx_ch3;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch3 : sfp_1_200_intrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch3,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch3_sig,
+ rx_los_low_ch_s => rx_los_low_ch3_sig,
+ tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch3_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch3_c);
+
+
+ P5 : PROCESS(fpga_txrefclk, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_tx_ch <= '0';
+ ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
+ refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
+ END IF;
+ END PROCESS;
+
+-- reset sequence for tx
+tx_reset_sm_ch : sfp_1_200_inttx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ rst_n => rst_n,
+ refclkdiv2 => refclkdiv2_tx_ch,
+ tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+ rst_qd_c => rst_qd_c,
+ tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
+ );
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end sfp_1_200_int_arch ;
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "sfp_2_200_int.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_EXT";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity sfp_2_200_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_2_200_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_serdes_rst_ch1_c : in std_logic;
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pcs_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pcs_rst_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ rst_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end sfp_2_200_int;
+
+
+architecture sfp_2_200_int_arch of sfp_2_200_int is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch1_sig : std_logic;
+signal tx_full_clk_ch3_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ refclk2fpga <= refclk2fpga_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpsc_vlo,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => open,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+ HDOUTP1 => hdoutp_ch1,
+ HDOUTN1 => hdoutn_ch1,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => sci_sel_ch1,
+ SCIENCH1 => fpsc_vhi,
+ FF_RXI_CLK_1 => rxiclk_ch1,
+ FF_TXI_CLK_1 => txiclk_ch1,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+ FF_TX_H_CLK_1 => tx_half_clk_ch1,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => txdata_ch1(0),
+ FF_TX_D_1_1 => txdata_ch1(1),
+ FF_TX_D_1_2 => txdata_ch1(2),
+ FF_TX_D_1_3 => txdata_ch1(3),
+ FF_TX_D_1_4 => txdata_ch1(4),
+ FF_TX_D_1_5 => txdata_ch1(5),
+ FF_TX_D_1_6 => txdata_ch1(6),
+ FF_TX_D_1_7 => txdata_ch1(7),
+ FF_TX_D_1_8 => tx_k_ch1(0),
+ FF_TX_D_1_9 => tx_force_disp_ch1(0),
+ FF_TX_D_1_10 => tx_disp_sel_ch1(0),
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => txdata_ch1(8),
+ FF_TX_D_1_13 => txdata_ch1(9),
+ FF_TX_D_1_14 => txdata_ch1(10),
+ FF_TX_D_1_15 => txdata_ch1(11),
+ FF_TX_D_1_16 => txdata_ch1(12),
+ FF_TX_D_1_17 => txdata_ch1(13),
+ FF_TX_D_1_18 => txdata_ch1(14),
+ FF_TX_D_1_19 => txdata_ch1(15),
+ FF_TX_D_1_20 => tx_k_ch1(1),
+ FF_TX_D_1_21 => tx_force_disp_ch1(1),
+ FF_TX_D_1_22 => tx_disp_sel_ch1(1),
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1(0),
+ FF_RX_D_1_9 => rx_disp_err_ch1(0),
+ FF_RX_D_1_10 => rx_cv_err_ch1(0),
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => rxdata_ch1(8),
+ FF_RX_D_1_13 => rxdata_ch1(9),
+ FF_RX_D_1_14 => rxdata_ch1(10),
+ FF_RX_D_1_15 => rxdata_ch1(11),
+ FF_RX_D_1_16 => rxdata_ch1(12),
+ FF_RX_D_1_17 => rxdata_ch1(13),
+ FF_RX_D_1_18 => rxdata_ch1(14),
+ FF_RX_D_1_19 => rxdata_ch1(15),
+ FF_RX_D_1_20 => rx_k_ch1(1),
+ FF_RX_D_1_21 => rx_disp_err_ch1(1),
+ FF_RX_D_1_22 => rx_cv_err_ch1(1),
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+ FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+ FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => sci_sel_ch3,
+ SCIENCH3 => fpsc_vhi,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => txiclk_ch3,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => tx_force_disp_ch3,
+ FF_TX_D_3_10 => tx_disp_sel_ch3,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => tx_sync_qd_c,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end sfp_2_200_int_arch ;
signal clk_200_osc : std_logic;
signal clk_200_txdata : std_logic;
-signal clk_200_rxdn : std_logic_vector(3 downto 0);
-signal clk_200_i : std_logic_vector(3 downto 0);
+--signal clk_200_rxdn : std_logic_vector(3 downto 0);
+--signal clk_200_i : std_logic_vector(3 downto 0);
signal rx_full_clk : std_logic_vector(3 downto 0);
signal rx_half_clk : std_logic_vector(3 downto 0);
signal tx_full_clk : std_logic_vector(3 downto 0);
-- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
end generate;
-end med_ecp3_sfp_4_soda_arch;
+end med_ecp3_sfp_4_soda_arch;
\ No newline at end of file
--Media interface for Lattice ECP3 using PCS at 2GHz
-
+-- TAB=3
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.all;
entity med_ecp3_sfp_sync_up is
generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_YES); --select slave mode
+ IS_SYNC_SLAVE : integer := c_YES); --select slave mode
port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
--Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic := '0';
--Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic := '0';
+ MED_READ_IN : in std_logic;
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
--Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
LINK_PHASE_OUT : out std_logic := '0'; --PL!
LINK_READY_OUT : out std_logic := '0'; --PL!
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
-- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end entity;
end component;
---signal clk_200_i : std_logic;
---signal clk_200_internal : std_logic;
-signal clk_200_osc : std_logic;
+signal clk_200_osc : std_logic;
signal rx_full_clk : std_logic;
signal rx_half_clk : std_logic;
signal tx_full_clk : std_logic;
RX_HALF_CLK_OUT <= rx_half_clk;
RX_FULL_CLK_OUT <= rx_full_clk;
TX_HALF_CLK_OUT <= tx_half_clk;
-TX_FULL_CLK_OUT <= tx_full_clk;\r
+TX_FULL_CLK_OUT <= tx_full_clk;
RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
RX_CDR_LOL_CH_S => rx_cdr_lol,
RX_LOS_LOW_CH_S => rx_los_low,
RX_PCS_RST_CH_C => rx_pcs_rst,
- WA_POSITION => wa_position_rx(3 downto 0),
+ WA_POSITION => wa_position_rx(15 downto 12),
STATE_OUT => rx_fsm_state
);
CLK_EN : in std_logic;
SODA_BURST_PULSE_IN : in std_logic := '0'; --
-
+ SODA_CYCLE_IN : in std_logic := '0'; --
-- MULTIPLE DUPLEX DOWN-LINKS
RX_DLM_IN : in t_HUB_BIT;
RX_DLM_WORD_IN : in t_HUB_BYTE;
architecture Behavioral of soda_4source is
--SODA
--- signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
--- signal soda_cmd_valid_S : std_logic := '0';
--- signal soda_cmd_strobe_S : std_logic := '0'; -- for commands sent in a SODA package
--- signal soda_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent in a SODA package
signal trb_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
--- signal trb_cmd_valid_S : std_logic := '0';
signal trb_cmd_strobe_S : std_logic := '0'; -- for commands sent over trbnet
signal trb_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent over trbnet
signal trb_cmd_pending_S : std_logic := '0';
signal soda_cmd_window_S : std_logic := '0';
signal start_of_superburst_S : std_logic := '0';
signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal crc_data_S : std_logic_vector(7 downto 0) := (others => '0');
- signal crc_valid_S : std_logic := '0';
+-- signal soda_40mhz_cycle_S : std_logic := '0';
-- Signals
type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
signal TXsoda_cmd_valid_S : t_HUB_BIT_ARRAY;
signal TXsoda_cmd_word_S : t_HUB_LWORD_ARRAY;
-
--- signal channel_status_S : t_HUB_BIT_ARRAY;
--- signal status_register : std_logic_vector(31 downto 0) := (others => '0');
-
-- slave bus signals
signal bus_ack_x : std_logic;
signal bus_ack : std_logic;
signal store_rd_x : std_logic;
signal store_rd : std_logic;
signal buf_bus_data_out : std_logic_vector(31 downto 0) := (others => '0');
- signal ledregister_i : std_logic_vector(31 downto 0) := (others => '0');
- signal txup_dlm_out_S : std_logic;
-- debug
-- signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0');
SUPER_BURST_NR_OUT => super_burst_nr_S,
SODA_CMD_WINDOW_OUT => soda_cmd_window_S
);\r
+\r
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
TXsoda_cmd_valid_S(i) <= trb_cmd_strobe_S; --trb_cmd_valid_S;
TXstart_of_superburst_S(i) <= start_of_superburst_S;
TXsoda_cmd_word_S(i) <= '0' & trb_cmd_word_S;
- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;
- \r
+ TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;\r
start_calibration_S(i) <= send_start_calibration_S(i);
SODACLK => SODACLK,
RESET => RESET,
--Internal Connection
- LINK_PHASE_IN => LINK_PHASE_IN(i), --link_phase_S, PL!
+ LINK_PHASE_IN => LINK_PHASE_IN(i), --link_phase_S, PL!\r
+ SODA_CYCLE_IN => SODA_CYCLE_IN,
+
SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i),
START_OF_SUPERBURST => TXstart_of_superburst_S(i),
SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0),
--debug_status_S(31 downto 3) <= LINK_DEBUG_IN(31 downto 3);
-- TXUP_DLM_OUT <= txup_dlm_out_S;
-- output signals
- LEDS_OUT <= LEDregister_i(3 downto 0);
+ LEDS_OUT <= (others => '0'); --LEDregister_i(3 downto 0);
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
constant c_HUB_CHILDREN : natural range 1 to 4 := 4; -- number of children per soda-hub
constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns
constant cSYS_CLOCK_PERIOD : natural range 1 to 20 := 10; -- soda clock-period in ns
+ constant cSODA_CYCLE_PERIOD : natural range 1 to 50 := 25; -- cycle-period at which soda transmits, in ns
constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns
constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns
constant cSODA_CALIBRATION_TIMEOUT : natural range 100 to 5000 := 250; -- soda clock-period in ns
constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles
constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles
- constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH;
- constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH;
- constant c_QUAD_MUX_WIDTH : integer := 3; --!!!
+ constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH;
+ constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH;
+ constant c_QUAD_MUX_WIDTH : integer := 3; --!!!
subtype t_HUB_BIT is std_logic_vector(c_HUB_CHILDREN-1 downto 0);
type t_HUB_NUM is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0);
RESET : in std_logic; -- synchronous reset
--Internal Connection
LINK_PHASE_IN : in std_logic := '0';
+ SODA_CYCLE_IN : in std_logic := '0';
SODA_CMD_STROBE_IN : in std_logic := '0'; --
START_OF_SUPERBURST : in std_logic := '0';
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
- SODA_BURST_PULSE_IN : in std_logic := '0'; --
-
+ SODA_BURST_PULSE_IN : in std_logic := '0';
+ SODA_CYCLE_IN : in std_logic := '0';
-- MULTIPLE DUPLEX DOWN-LINKS
RX_DLM_IN : in t_HUB_BIT;
- RX_DLM_WORD_IN : in t_HUB_BYTE;
+ RX_DLM_WORD_IN : in t_HUB_BYTE;
TX_DLM_OUT : out t_HUB_BIT;
TX_DLM_WORD_OUT : out t_HUB_BYTE;
TX_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL!
- LINK_PHASE_IN : in t_HUB_BIT; --PL!
+ LINK_PHASE_IN : in t_HUB_BIT; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
SODA_READ_IN : in std_logic := '0';
- SODA_WRITE_IN : in std_logic := '0';
+ SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);
- LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
+ LEDS_OUT : out std_logic_vector(3 downto 0);
+ LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
);
end component;
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);
+ LEDS_OUT : out std_logic_vector(3 downto 0);
LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
);
end component;
SODA_BURST_PULSE_OUT : out std_logic := '0'
);
end component;
-
+\r
+ component soda_start_of_burst_control is
+ generic(
+ CLOCK_PERIOD : natural range 1 to 25 := cSODA_CLOCK_PERIOD; -- clock-period in ns
+ CYCLE_PERIOD : natural range 5 to 50 := cSODA_CYCLE_PERIOD; -- cycle-period in ns
+ BURST_PERIOD : natural := cBURST_PERIOD -- burst-period in ns
+ );
+ port(
+ SODA_CLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ SODA_BURST_PULSE_OUT : out std_logic := '0';
+ SODA_40MHZ_CYCLE_OUT : out std_logic := '0'
+ );
+ end component;
+\r
component posedge_to_pulse
port (
IN_CLK : in std_logic;
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
- -- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes
- -- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes
+ -- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes
+ -- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes
--Internal Connection TX
MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
component med_ecp3_sfp_4_sync_down is
generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode
port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
+ OSC_CLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
---------------------------------------------------------------------------------------------------------------------------------------------------------
--Internal Connection TX
- MED_DATA_IN : in t_HUB_WORD; --std_logic_vector(c_QUAD_DATA_WIDTH-1 downto 0);
+ MED_DATA_IN : in t_HUB_WORD; --std_logic_vector(c_QUAD_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(c_QUAD_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0');
--Internal Connection RX
- MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
- MED_READ_IN : in std_logic_vector(3 downto 0);
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ MED_READ_IN : in std_logic_vector(3 downto 0);
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
SD_RXD_N_IN : in t_HUB_BIT; --std_logic;
SD_TXD_P_OUT : out t_HUB_BIT; --std_logic;
SD_TXD_N_OUT : out t_HUB_BIT; --std_logic;
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
SCI_ACK : out std_logic := '0';
SCI_NACK : out std_logic := '0';
-- Status and control port
STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end component;
component med_ecp3_sfp_4_sync_down_EP is
generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode
port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
+ OSC_CLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
SD_RXD_N_IN : in t_HUB_BIT; --std_logic;
SD_TXD_P_OUT : out t_HUB_BIT; --std_logic;
SD_TXD_N_OUT : out t_HUB_BIT; --std_logic;
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
SCI_ACK : out std_logic := '0';
SCI_NACK : out std_logic := '0';
-- Status and control port
-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end component;
IS_SYNC_SLAVE : integer := c_YES --select slave mode
);
port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
+ OSCCLK : in std_logic; -- 200 MHz reference clock
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
MED_READ_IN : in std_logic;
RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz
- TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz
RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
--Sync operation
RX_DLM : out std_logic := '0';
component soda_only_ecp3_sfp_sync_up
generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_YES); --select slave mode
+ IS_SYNC_SLAVE : integer := c_YES); --select slave mode
port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
-
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
--Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
LINK_PHASE_OUT : out std_logic := '0'; --PL!
LINK_READY_OUT : out std_logic := '0'; --PL!
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0'
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0'
);
end component;
\r
component med_ecp3_sfp_4_soda is
generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
+ IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
+ OSC_CLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
---------------------------------------------------------------------------------------------------------------------------------------------------------
--- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+-- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
SCI_ACK : out std_logic := '0';
SCI_NACK : out std_logic := '0';
-- Status and control port
-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end component;
+\r
+ component Cu_trb_net16_soda_sync_ecp3_sfp
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 0;
+ EXT_CLOCK : integer range 0 to 1 := c_NO;
+ USE_200_MHZ : integer range 0 to 1 := c_YES;
+ USE_125_MHZ : integer range 0 to 1 := c_NO;
+ USE_CTC : integer range 0 to 1 := c_YES;
+ USE_SLAVE : integer range 0 to 1 := c_NO;
+ SODA_IS_SYNC_SLAVE : integer range 0 to 1 := c_YES
+ );
+ port(
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic := '0';
+ --Internal Connection RX
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic := '0';
+ MED_READ_IN : in std_logic;
+ -- sync clocks
+ SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+
+ --Copper SFP Connection
+ CU_RXD_P_IN : in std_logic;
+ CU_RXD_N_IN : in std_logic;
+ CU_TXD_P_OUT : out std_logic;
+ CU_TXD_N_OUT : out std_logic;
+ CU_REFCLK_P_IN : in std_logic; --not used
+ CU_REFCLK_N_IN : in std_logic; --not used
+ CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+ end component;\r
component soda_tx_control
port(
- CLK_200 : in std_logic;
- CLK_100 : in std_logic;
+ CLK_200 : in std_logic;
+ CLK_100 : in std_logic;
RESET_IN : in std_logic;
- TX_DATA_IN : in std_logic_vector(15 downto 0);
- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
+ TX_DATA_IN : in std_logic_vector(15 downto 0);
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
TX_WRITE_IN : in std_logic;
TX_READ_OUT : out std_logic;
TX_DATA_OUT : out std_logic_vector( 7 downto 0);
TX_K_OUT : out std_logic;
- REQUEST_RETRANSMIT_IN : in std_logic := '0';
- REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
+ REQUEST_RETRANSMIT_IN : in std_logic := '0';
+ REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
- START_RETRANSMIT_IN : in std_logic := '0';
+ START_RETRANSMIT_IN : in std_logic := '0';
START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
TX_DLM_PREVIEW_IN : in std_logic := '0';
SEND_DLM : in std_logic := '0';
- SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');
+ SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');
- SEND_LINK_RESET_IN : in std_logic := '0';
+ SEND_LINK_RESET_IN : in std_logic := '0';
TX_ALLOW_IN : in std_logic := '0';
RX_ALLOW_IN : in std_logic := '0';
LINK_PHASE_OUT : out std_logic := '0';
- DEBUG_OUT : out std_logic_vector(31 downto 0);
- STAT_REG_OUT : out std_logic_vector(31 downto 0)
+ DEBUG_OUT : out std_logic_vector(31 downto 0);
+ STAT_REG_OUT : out std_logic_vector(31 downto 0)
);
end component;
end component;\r
\r
component DCS
- -- synthesis translate_off
- generic
- (
- DCSMODE : string :=“POS”
+ -- synthesis translate_off
+ generic
+ (
+ DCSMODE : string :=“POS”
+ );
+ -- synthesis translate_on
+ port (
+ CLK0 : in std_logic ;
+ CLK1 : in std_logic ;
+ SEL : in std_logic ;
+ DCSOUT : out std_logic\r
);
- -- synthesis translate_on
- port (
- CLK0 : in std_logic ;
- CLK1 : in std_logic ;
- SEL : in std_logic ;
- DCSOUT : out std_logic) ;
end component;
\r
component dff_re
Port (\r
- rst : in STD_LOGIC;
- clk : in STD_LOGIC;
- enable : in STD_LOGIC;
- d : in STD_LOGIC_VECTOR;
- q : out STD_LOGIC_VECTOR;
- data_valid : out STD_LOGIC
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ enable : in STD_LOGIC;
+ d : in STD_LOGIC_VECTOR;
+ q : out STD_LOGIC_VECTOR;
+ data_valid : out STD_LOGIC
);
end component;\r
);
end soda_d8crc8;
-architecture behavioral of soda_d8crc8 is
+architecture behavioral of soda_d8crc8 is\r
+ \r
+ constant crc_const: std_logic_vector(7 downto 0) := (others => '0');\r
+
signal crc_r : std_logic_vector(7 downto 0);
signal crc_c : std_logic_vector(7 downto 0);
signal crc_i : std_logic_vector(7 downto 0);
- signal crc_const : std_logic_vector(7 downto 0) := "00000000";
+-- signal crc_const : std_logic_vector(7 downto 0) := "00000000";
signal crc_valid_out_S : std_logic :='0';
begin
-------------------------------------------------
-- Serdes
-------------------------------------------------
-THE_SERDES : entity work.serdes_sync_upstream
+THE_SERDES : sfp_2_200_int
port map(
hdinp_ch3 => SD_RXD_P_IN,
hdinn_ch3 => SD_RXD_N_IN,
SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
--Internal Connection\r
- LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0');
- SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
+ LINK_PHASE_IN : in std_logic := '0'; -- even/odd fase needed to match 16-bit link stuff in trb
+ SODA_CYCLE_IN : in std_logic := '0'; -- 40MHz cycle for soda transmissions
+ SODA_CMD_STROBE_IN : in std_logic := '0'; \r
START_OF_SUPERBURST : in std_logic := '0';\r
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
architecture Behavioral of soda_packet_builder is\r
signal soda_cmd_window_S : std_logic;
--- signal soda_cmd_strobe_S : std_logic;
--- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator\r
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol\r
signal soda_pkt_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
signal soda_pkt_valid_S : std_logic;\r
signal eoc_S : std_logic;\r
signal crc_data_valid_S : std_logic;\r
signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal crc_tmp_S : std_logic_vector(7 downto 0) := (others => '0');\r
signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0');\r
signal crc_valid_S : std_logic;\r
\r
signal packet_state_S : packet_state_type := c_IDLE;\r
\r
signal soda_dlm_preview_S : std_logic;
--- signal soda_cmd_reg_full_S : std_logic;
--- signal soda_cmd_reg_S : std_logic_vector(31 downto 0) := (others => '0'); -- from super-burst-nr-generator
\r
begin\r
\r
- tx_crc8: soda_d8crc8
+ tx_crc8: soda_d8crc8
port map(
CLOCK => SODACLK,
RESET => RESET,
CRC_VALID_OUT => crc_valid_S
);
--- soda_cmd_strobe_S <= SODA_CMD_STROBE_IN;
soda_cmd_word_S <= SODA_CMD_WORD_IN;\r
--- super_burst_nr_S <= SUPER_BURST_NR_IN;
\r
TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or\r
((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) \r
else '0';
--- TX_DLM_PREVIEW_OUT <= soda_dlm_preview_S;
TX_DLM_OUT <= soda_pkt_valid_S;\r
TX_DLM_WORD_OUT <= soda_pkt_word_S;
\r
end if;\r
elsif (SODA_CMD_STROBE_IN='1') then\r
soda_dlm_preview_S <= '1';
- if (LINK_PHASE_IN = c_PHASE_H) then\r
+ if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then\r
packet_state_S <= c_CMD1;\r
soda_pkt_valid_S <= '1';
soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_WAIT4CMD1 =>\r
- packet_state_S <= c_CMD1;\r
- soda_dlm_preview_S <= '1';
- soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
+ if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then\r
+ packet_state_S <= c_CMD1;
+ soda_dlm_preview_S <= '1';
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
+ else\r
+ packet_state_S <= c_WAIT4CMD1;
+ soda_dlm_preview_S <= '0';
+ soda_pkt_valid_S <= '0';
+-- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);\r
+ end if;
when c_CMD1 =>\r
packet_state_S <= c_CMD2;\r
soda_dlm_preview_S <= '1';
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.soda_components.all;
+
+entity soda_start_of_burst_control is
+ generic(
+ CLOCK_PERIOD : natural range 1 to 50 := cSODA_CLOCK_PERIOD; -- clock-period in ns
+ CYCLE_PERIOD : natural range 5 to 50 := cSODA_CYCLE_PERIOD; -- cycle-period in ns
+ BURST_PERIOD : natural := cBURST_PERIOD -- burst-period in ns
+ );
+ port(
+ SODA_CLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ SODA_BURST_PULSE_OUT : out std_logic := '0';
+ SODA_40MHZ_CYCLE_OUT : out std_logic := '0'
+ );
+end soda_start_of_burst_control;
+
+architecture Behavioral of soda_start_of_burst_control is
+
+ constant cCLOCKS_PER_CYCLE : std_logic_vector(15 downto 0) := conv_std_logic_vector((CYCLE_PERIOD / CLOCK_PERIOD) - 1, 16);
+ constant cCYCLES_PER_BURST : std_logic_vector(15 downto 0) := conv_std_logic_vector((BURST_PERIOD / CYCLE_PERIOD) - 1, 16);
+
+ signal cycle_counter_S : std_logic_vector(15 downto 0) := (others => '0');
+ signal burst_counter_S : std_logic_vector(15 downto 0) := (others => '0');
+
+
+begin
+
+ cycle_n_burst_pulse_proc : process(SODA_CLK)
+ begin
+ if rising_edge(SODA_CLK) then
+ if (RESET='1') then
+ cycle_counter_S <= cCLOCKS_PER_CYCLE;
+ burst_counter_S <= cCYCLES_PER_BURST;
+ SODA_40MHZ_CYCLE_OUT <= '0';
+ SODA_BURST_PULSE_OUT <= '0';
+ elsif (cycle_counter_S=0) then\r
+ cycle_counter_S <= cCLOCKS_PER_CYCLE;
+ SODA_40MHZ_CYCLE_OUT <= '1';
+ if (burst_counter_S=0) then
+ burst_counter_S <= cCYCLES_PER_BURST;
+ SODA_BURST_PULSE_OUT <= '1';
+ else
+ burst_counter_S <= burst_counter_S - 1;
+ SODA_BURST_PULSE_OUT <= '0';
+ end if;\r
+ else\r
+ cycle_counter_S <= cycle_counter_S - 1;
+ SODA_40MHZ_CYCLE_OUT <= '0';
+ end if;
+ end if;
+ end process;
+
+
+end Behavioral;
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
use work.soda_components.all;
entity soda_superburst_generator is
constant cBURST_COUNT : std_logic_vector(7 downto 0) := conv_std_logic_vector(BURST_COUNT - 1,8);
signal soda_burst_pulse_S : std_logic := '0';
- signal start_of_superburst_S : std_logic := '0';
signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
signal burst_counter_S : std_logic_vector(7 downto 0) := (others => '0'); -- from super-burst-nr-generator
end if;
end if;
end process;
-\r
+
soda_cmd_window_proc : process(SODACLK)
begin
if rising_edge(SODACLK) then
if (RESET='1') then
SODA_CMD_WINDOW_OUT <= '0';
- elsif (burst_counter_S = (cBURST_COUNT - 1)) then\r
+ elsif (burst_counter_S = (cBURST_COUNT - 1)) then
SODA_CMD_WINDOW_OUT <= '1';
elsif (burst_counter_S = 2) then
SODA_CMD_WINDOW_OUT <= '0';
end if;
end if;
- end process;\r
+ end process;
-end Behavioral;
+end Behavioral;
\ No newline at end of file
+---------------
+-- TOP LEVEL --
+---------------
+-- TAB=3 !!
+-- 24/11/2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use ieee.std_logic_unsigned.all;
library work;
use work.trb_net_std.all;
use work.med_sync_define.all;
use work.version.all;
-entity trb3_periph_EP_soda4source is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_TRB_INTERFACES : integer := 1
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --serdes I/O - connect as you like, no real use
+entity trb3_periph_ep_soda4source is \r
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
+ USE_125_MHZ : integer := c_NO;
+ CLOCK_FREQUENCY : integer := 100;
+ NUM_TRB_INTERFACES : integer := 1
+ );
+ port (
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ \r
+ --serdes I/O - connect as you like, no real use
SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --SFP_MOD1 : inout std_logic_vector(6 downto 1);
- --SFP_MOD2 : inout std_logic_vector(6 downto 1);
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ LED_LINKOK : out std_logic_vector(6 downto 1);
+ LED_RX : out std_logic_vector(6 downto 1);
+ LED_TX : out std_logic_vector(6 downto 1);
+ SFP_MOD0 : in std_logic_vector(6 downto 1);
+ SFP_TXDIS : out std_logic_vector(6 downto 1);
+ SFP_LOS : in std_logic_vector(6 downto 1);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;\r
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0) := (others => '0')
+ );\r
+ attribute syn_useioff : boolean;
--no IO-FF for LEDs relaxes timing constraints
attribute syn_useioff of LED_GREEN : signal is false;
attribute syn_useioff of LED_ORANGE : signal is false;
attribute syn_useioff of LED_RED : signal is false;
attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
+-- attribute syn_useioff of LED_LINKOK : signal is false;
+-- attribute syn_useioff of LED_TX : signal is false;
+-- attribute syn_useioff of LED_RX : signal is false;
+-- attribute syn_useioff of SFP_MOD0 : signal is false;
+-- attribute syn_useioff of SFP_TXDIS : signal is false;
+-- attribute syn_useioff of SFP_LOS : signal is false;
attribute syn_useioff of TEST_LINE : signal is false;
-
--important signals _with_ IO-FF
attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
attribute syn_useioff of FLASH_DIN : signal is true;
attribute syn_useioff of FLASH_DOUT : signal is true;
attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
+end trb3_periph_EP_soda4source;
architecture trb3_periph_EP_soda4source_arch of trb3_periph_EP_soda4source is
--Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
--Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
-
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
- signal time_counter : unsigned(31 downto 0);
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic := '1';
+ signal reset_i : std_logic := '1';
+ signal GSR_N : std_logic := '0';
+
+ signal clk_100_osc : std_logic;
+ signal clk_200_osc : std_logic;
+ signal time_counter_S : std_logic_vector(31 downto 0);
--Media Interface
- signal med_stat_op : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
--- signal med_ctrl_debug : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_stat_op : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector(NUM_TRB_INTERFACES*64-1 downto 0);
+-- signal med_ctrl_debug : std_logic_vector(NUM_TRB_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector(NUM_TRB_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector(NUM_TRB_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
--Slow Control channel
-- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
--RegIO
--- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
+-- signal my_address : std_logic_vector(15 downto 0);
+ signal regio_addr_out : std_logic_vector(15 downto 0);
signal regio_read_enable_out : std_logic;
signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_data_out : std_logic_vector(31 downto 0);
+ signal regio_data_in : std_logic_vector(31 downto 0);
signal regio_dataready_in : std_logic;
signal regio_no_more_data_in : std_logic;
signal regio_write_ack_in : std_logic;
signal spimem_write_ack_out : std_logic;
-- SCI for the uplink
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
-- SCI for the downlink
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
+ signal sci2_ack : std_logic;
+ signal sci2_nack : std_logic;
+ signal sci2_write : std_logic;
+ signal sci2_read : std_logic;
+ signal sci2_data_in : std_logic_vector(7 downto 0);
+ signal sci2_data_out : std_logic_vector(7 downto 0);
+ signal sci2_addr : std_logic_vector(8 downto 0);
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
--SODA
signal soda_ack : std_logic;
--SODA
signal SOB_S : std_logic := '0';
+ signal soda_40mhz_cycle_S : std_logic := '0';
+
-- fix signal names for constraining
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
attribute syn_keep of tx_dlm_i : signal is true;
attribute syn_preserve of rx_dlm_i : signal is true;
attribute syn_keep of rx_dlm_i : signal is true;
+ attribute syn_preserve of soda_40mhz_cycle_S : signal is true;
+ attribute syn_keep of soda_40mhz_cycle_S : signal is true;
-
+\r
begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
---------------------------------------------------------------------------
-- Clock Handling
---------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
+gen_200_PLL : if USE_125_MHZ = c_NO generate
THE_MAIN_PLL : pll_in200_out100
port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_100_osc,
+ CLKOK => clk_200_osc,
+ LOCK => pll_lock
);
---end generate;
-
---gen_125 : if USE_125_MHZ = c_YES generate
--- clk_100_osc <= CLK_GPLL_LEFT;
--- clk_200_osc <= CLK_GPLL_LEFT;
---end generate;
+end generate;
+-- GSR_N <= pll_lock;
+\r
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => '0', --med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
---------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
- USE_125_MHZ => USE_125_MHZ,
- USE_CTC => c_NO,
- USE_SLAVE => SYNC_MODE
- )
- port map(
- CLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => open,
- CLK_RX_FULL_OUT => open,
-
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(4),
- SD_RXD_N_IN => SERDES_ADDON_RX(5),
- SD_TXD_P_OUT => SERDES_ADDON_TX(4),
- SD_TXD_N_OUT => SERDES_ADDON_TX(5),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
+THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
+ USE_125_MHZ => USE_125_MHZ,
+ USE_CTC => c_NO,
+ USE_SLAVE => SYNC_MODE
+ )
+ port map(
+ CLK => clk_200_osc,
+ SYSCLK => clk_100_osc,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => open,
+ CLK_RX_FULL_OUT => open,
+
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(4),
+ SD_RXD_N_IN => SERDES_ADDON_RX(5),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ -- Status and control port
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => (others => '0')
+ );
---------------------------------------------------------------------------
-- Endpoint
---------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
--- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f358",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"45",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"9100b000",
+ REGIO_INIT_ADDRESS => x"f358",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 9, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 256,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 256
+ )
+ port map(
+ CLK => clk_100_osc,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out(0),
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
+ MED_READ_IN => med_read_in(0),
+ MED_DATAREADY_IN => med_dataready_in(0),
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out(0),
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
--Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
+ TRG_TIMING_TRG_RECEIVED_IN => '0',
--LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
+ LVL1_TRG_DATA_VALID_OUT => open,
+ LVL1_VALID_TIMING_TRG_OUT => open,
+ LVL1_VALID_NOTIMING_TRG_OUT => open,
+ LVL1_INVALID_TRG_OUT => open,
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
+ LVL1_TRG_TYPE_OUT => open,
+ LVL1_TRG_NUMBER_OUT => open,
+ LVL1_TRG_CODE_OUT => open,
+ LVL1_TRG_INFORMATION_OUT => open,
+ LVL1_INT_TRG_NUMBER_OUT => open,
--Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
+ TRG_MULTIPLE_TRG_OUT => open,
+ TRG_TIMEOUT_DETECTED_OUT => open,
+ TRG_SPURIOUS_TRG_OUT => open,
+ TRG_MISSING_TMG_TRG_OUT => open,
+ TRG_SPIKE_DETECTED_OUT => open,
--Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
+ FEE_TRG_RELEASE_IN(0) => '1',
+ FEE_TRG_STATUSBITS_IN => (others => '0'),
+ FEE_DATA_IN => (others => '0'),
+ FEE_DATA_WRITE_IN(0) => '0',
+ FEE_DATA_FINISHED_IN(0) => '1',
+ FEE_DATA_ALMOST_FULL_OUT(0) => open,
-- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
+ REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
);
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_READ_ENABLE_OUT(3) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_WRITE_ENABLE_OUT(3) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
+ )
+ port map(
+ CLK => clk_100_osc,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,
+ BUS_READ_ENABLE_OUT(1) => sci1_read,
+ BUS_READ_ENABLE_OUT(2) => sci2_read,
+ BUS_READ_ENABLE_OUT(3) => soda_read,
+
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => sci1_write,
+ BUS_WRITE_ENABLE_OUT(2) => sci2_write,
+ BUS_WRITE_ENABLE_OUT(3) => soda_write,
+
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
+ BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
+
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(2*32+31 downto 2*32+8) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_DATAREADY_IN(3) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(3) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
- STAT_DEBUG => open
+ BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
+ BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
+
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
+ BUS_DATA_IN(2*32+31 downto 2*32+8) => open,
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
+
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,
+ BUS_DATAREADY_IN(1) => sci1_ack,
+ BUS_DATAREADY_IN(2) => sci2_ack,
+ BUS_DATAREADY_IN(3) => soda_ack,
+
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
+ BUS_WRITE_ACK_IN(1) => sci1_ack,
+ BUS_WRITE_ACK_IN(2) => sci2_ack,
+ BUS_WRITE_ACK_IN(3) => soda_ack,
+
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+
+ STAT_DEBUG => open
);
---------------------------------------------------------------------------
-- SPI / Flash
---------------------------------------------------------------------------
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
+THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
+ port map(
+ CLK_IN => clk_100_osc,
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_DATAREADY_OUT => spimem_dataready_out,
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+\r
---------------------------------------------------------------------------
-- The synchronous quad-downlink interface for Soda
---------------------------------------------------------------------------
- MED_ECP3_SODA_QUAD_SOURCE : med_ecp3_sfp_4_soda
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSC_CLK => clk_200_osc,
- TX_DATACLK => clk_200_osc,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
- RESET => reset_i,
- CLEAR => clear_i,
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
+MED_ECP3_SODA_QUAD_SOURCE : med_ecp3_sfp_4_soda
+ generic map(
+ SERDES_NUM => 0, --number of serdes (for trb) in quad
+ IS_SYNC_SLAVE => c_NO
+ )
+ port map(
+ OSC_CLK => clk_200_osc,
+ TX_DATACLK => clk_200_osc,
+ SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
+ RESET => reset_i,
+ CLEAR => clear_i,
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
-- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT(0) => rx_half_clk(0),
- RX_HALF_CLK_OUT(1) => rx_half_clk(1),
- RX_HALF_CLK_OUT(2) => rx_half_clk(2),
- RX_HALF_CLK_OUT(3) => rx_half_clk(3),
-
- RX_FULL_CLK_OUT(0) => rx_full_clk(0), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(1) => rx_full_clk(1), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(2) => rx_full_clk(2), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(3) => rx_full_clk(3), -- needed for sync replies i.e. calibration
-
- TX_HALF_CLK_OUT(0) => tx_half_clk(0),
- TX_HALF_CLK_OUT(1) => tx_half_clk(1),
- TX_HALF_CLK_OUT(2) => tx_half_clk(2),
- TX_HALF_CLK_OUT(3) => tx_half_clk(3),
-
- TX_FULL_CLK_OUT(0) => tx_full_clk(0),
- TX_FULL_CLK_OUT(1) => tx_full_clk(1),
- TX_FULL_CLK_OUT(2) => tx_full_clk(2),
- TX_FULL_CLK_OUT(3) => tx_full_clk(3),
-
- RX_DLM_OUT(0) => rx_dlm_i(0),
- RX_DLM_OUT(1) => rx_dlm_i(1),
- RX_DLM_OUT(2) => rx_dlm_i(2),
- RX_DLM_OUT(3) => rx_dlm_i(3),
-
- RX_DLM_WORD_OUT(0) => rx_dlm_word(0),
- RX_DLM_WORD_OUT(1) => rx_dlm_word(1),
- RX_DLM_WORD_OUT(2) => rx_dlm_word(2),
- RX_DLM_WORD_OUT(3) => rx_dlm_word(3),
-
- TX_DLM_IN(0) => tx_dlm_i(0),
- TX_DLM_IN(1) => tx_dlm_i(1),
- TX_DLM_IN(2) => tx_dlm_i(2),
- TX_DLM_IN(3) => tx_dlm_i(3),
-
- TX_DLM_WORD_IN(0) => tx_dlm_word(0),
- TX_DLM_WORD_IN(1) => tx_dlm_word(1),
- TX_DLM_WORD_IN(2) => tx_dlm_word(2),
- TX_DLM_WORD_IN(3) => tx_dlm_word(3),
-
- TX_DLM_PREVIEW_IN(0) => tx_dlm_preview_S(0), --PL!
- TX_DLM_PREVIEW_IN(1) => tx_dlm_preview_S(1), --PL!
- TX_DLM_PREVIEW_IN(2) => tx_dlm_preview_S(2), --PL!
- TX_DLM_PREVIEW_IN(3) => tx_dlm_preview_S(3), --PL!
-
- LINK_PHASE_OUT(0) => link_phase_S(0), --PL!
- LINK_PHASE_OUT(1) => link_phase_S(1), --PL!
- LINK_PHASE_OUT(2) => link_phase_S(2), --PL!
- LINK_PHASE_OUT(3) => link_phase_S(3), --PL!
-
- --SFP Connection
- SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
- SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
- SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
- SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
- SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
- SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
- SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
- SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
- SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
- SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
- SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
- SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
- SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
- SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
- SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
- SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
- SD_REFCLK_P_IN => (others => '0'),
- SD_REFCLK_N_IN => ('0','0','0','0'),
- SD_PRSNT_N_IN(0) => SFP_MOD0(1),
- SD_PRSNT_N_IN(1) => SFP_MOD0(6),
- SD_PRSNT_N_IN(2) => SFP_MOD0(2),
- SD_PRSNT_N_IN(3) => SFP_MOD0(4),
- SD_LOS_IN(0) => SFP_LOS(1),
- SD_LOS_IN(1) => SFP_LOS(6),
- SD_LOS_IN(2) => SFP_LOS(2),
- SD_LOS_IN(3) => SFP_LOS(4),
- SD_TXDIS_OUT(0) => sfp_txdis_S(1),
- SD_TXDIS_OUT(1) => sfp_txdis_S(6),
- SD_TXDIS_OUT(2) => sfp_txdis_S(2),
- SD_TXDIS_OUT(3) => sfp_txdis_S(4),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
-
- --Status and control port
--- STAT_OP(0) => med_stat_op(15 downto 0), --med_stat_op(1*16+15 downto 1*16),
--- CTRL_OP(0) => med_ctrl_op(15 downto 0), --med_ctrl_op(0*16+15 downto 0*16),
-
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ RX_HALF_CLK_OUT(0) => rx_half_clk(0),
+ RX_HALF_CLK_OUT(1) => rx_half_clk(1),
+ RX_HALF_CLK_OUT(2) => rx_half_clk(2),
+ RX_HALF_CLK_OUT(3) => rx_half_clk(3),
+
+ RX_FULL_CLK_OUT(0) => rx_full_clk(0), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(1) => rx_full_clk(1), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(2) => rx_full_clk(2), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(3) => rx_full_clk(3), -- needed for sync replies i.e. calibration
+
+ TX_HALF_CLK_OUT(0) => tx_half_clk(0),
+ TX_HALF_CLK_OUT(1) => tx_half_clk(1),
+ TX_HALF_CLK_OUT(2) => tx_half_clk(2),
+ TX_HALF_CLK_OUT(3) => tx_half_clk(3),
+
+ TX_FULL_CLK_OUT(0) => tx_full_clk(0),
+ TX_FULL_CLK_OUT(1) => tx_full_clk(1),
+ TX_FULL_CLK_OUT(2) => tx_full_clk(2),
+ TX_FULL_CLK_OUT(3) => tx_full_clk(3),
+
+ RX_DLM_OUT(0) => rx_dlm_i(0),
+ RX_DLM_OUT(1) => rx_dlm_i(1),
+ RX_DLM_OUT(2) => rx_dlm_i(2),
+ RX_DLM_OUT(3) => rx_dlm_i(3),
+
+ RX_DLM_WORD_OUT(0) => rx_dlm_word(0),
+ RX_DLM_WORD_OUT(1) => rx_dlm_word(1),
+ RX_DLM_WORD_OUT(2) => rx_dlm_word(2),
+ RX_DLM_WORD_OUT(3) => rx_dlm_word(3),
+
+ TX_DLM_IN(0) => tx_dlm_i(0),
+ TX_DLM_IN(1) => tx_dlm_i(1),
+ TX_DLM_IN(2) => tx_dlm_i(2),
+ TX_DLM_IN(3) => tx_dlm_i(3),
+
+ TX_DLM_WORD_IN(0) => tx_dlm_word(0),
+ TX_DLM_WORD_IN(1) => tx_dlm_word(1),
+ TX_DLM_WORD_IN(2) => tx_dlm_word(2),
+ TX_DLM_WORD_IN(3) => tx_dlm_word(3),
+
+ TX_DLM_PREVIEW_IN(0) => tx_dlm_preview_S(0), --PL!
+ TX_DLM_PREVIEW_IN(1) => tx_dlm_preview_S(1), --PL!
+ TX_DLM_PREVIEW_IN(2) => tx_dlm_preview_S(2), --PL!
+ TX_DLM_PREVIEW_IN(3) => tx_dlm_preview_S(3), --PL!
+
+ LINK_PHASE_OUT(0) => link_phase_S(0), --PL!
+ LINK_PHASE_OUT(1) => link_phase_S(1), --PL!
+ LINK_PHASE_OUT(2) => link_phase_S(2), --PL!
+ LINK_PHASE_OUT(3) => link_phase_S(3), --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
+ SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
+ SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
+ SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
+ SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
+ SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
+ SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
+ SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
+ SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
+ SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
+ SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
+ SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
+ SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
+ SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
+ SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
+ SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
+ SD_REFCLK_P_IN => (others => '0'),
+ SD_REFCLK_N_IN => ('0','0','0','0'),
+ SD_PRSNT_N_IN(0) => SFP_MOD0(1),
+ SD_PRSNT_N_IN(1) => SFP_MOD0(6),
+ SD_PRSNT_N_IN(2) => SFP_MOD0(2),
+ SD_PRSNT_N_IN(3) => SFP_MOD0(4),
+ SD_LOS_IN(0) => SFP_LOS(1),
+ SD_LOS_IN(1) => SFP_LOS(6),
+ SD_LOS_IN(2) => SFP_LOS(2),
+ SD_LOS_IN(3) => SFP_LOS(4),
+ SD_TXDIS_OUT(0) => sfp_txdis_S(1),
+ SD_TXDIS_OUT(1) => sfp_txdis_S(6),
+ SD_TXDIS_OUT(2) => sfp_txdis_S(2),
+ SD_TXDIS_OUT(3) => sfp_txdis_S(4),
+
+ SCI_DATA_IN => sci2_data_in,
+ SCI_DATA_OUT => sci2_data_out,
+ SCI_ADDR => sci2_addr,
+ SCI_READ => sci2_read,
+ SCI_WRITE => sci2_write,
+ SCI_ACK => sci2_ack,
+ SCI_NACK => sci2_nack,
+
+ --Status and control port
+-- STAT_OP(0) => med_stat_op(15 downto 0), --med_stat_op(1*16+15 downto 1*16),
+-- CTRL_OP(0) => med_ctrl_op(15 downto 0), --med_ctrl_op(0*16+15 downto 0*16),
+
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+);
+
-\r
SFP_TXDIS <= sfp_txdis_S;
-- SFP_TXDIS(1) <= sfp_txdis_S(1);
---------------------------------------------------------------------------
--- The Soda Central
+-- Burst- and 40MHz cycle generator
---------------------------------------------------------------------------
-THE_SOB_SOURCE : soda_start_of_burst_faker
+THE_SOB_SOURCE : soda_start_of_burst_control
generic map(
- CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns
+ CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns
+ CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns
BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
)
port map(
- SYSCLK => clk_100_osc,
+ SODA_CLK => clk_200_osc,
RESET => reset_i,
- SODA_BURST_PULSE_OUT => SOB_S
+ SODA_BURST_PULSE_OUT => SOB_S,
+ SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S
);
---------------------------------------------------------------------------
CLEAR => clear_i,
CLK_EN => '1',
- SODA_BURST_PULSE_IN => SOB_S,
-
+ SODA_BURST_PULSE_IN => SOB_S,
+ SODA_CYCLE_IN => soda_40mhz_cycle_S,
-- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RX_DLM_IN => rx_dlm_i,
- RX_DLM_WORD_IN => rx_dlm_word,
- TX_DLM_OUT => tx_dlm_i,
- TX_DLM_WORD_OUT => tx_dlm_word,
- TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
- LINK_PHASE_IN => link_phase_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
+ RX_DLM_IN => rx_dlm_i,
+ RX_DLM_WORD_IN => rx_dlm_word,
+ TX_DLM_OUT => tx_dlm_i,
+ TX_DLM_WORD_OUT => tx_dlm_word,
+ TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
+ LINK_PHASE_IN => link_phase_S,
+ SODA_DATA_IN => soda_data_in,
+ SODA_DATA_OUT => soda_data_out,
+ SODA_ADDR_IN => soda_addr,
+ SODA_READ_IN => soda_read,
+ SODA_WRITE_IN => soda_write,
+ SODA_ACK_OUT => soda_ack,
+ LEDS_OUT => soda_leds,
+ LINK_DEBUG_IN => link_debug_in_S
);
--- downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0';
--- downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
- LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
- LED_GREEN <= med_stat_op(12); --tx_pll_lol
- LED_RED <= med_stat_op(11); --rx_cdr_lol
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
--- TEST_LINE(15 downto 0) <= (others => '0');
+ LED_ORANGE <= time_counter_S(27);
+ LED_YELLOW <= time_counter_S(26);
+ LED_GREEN <= time_counter_S(25);
+ LED_RED <= time_counter_S(24);
---------------------------------------------------------------------------
-- Test Circuits
---------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_100_osc);
- time_counter <= time_counter + 1;
- end process;
+ blink_L : process (clk_200_osc)
+ begin
+ if rising_edge(clk_200_osc) then
+ if (time_counter_S(15 downto 0) = x"FFFF") then
+ time_counter_S(15 downto 0) <= x"0000";\r
+ else
+ time_counter_S(15 downto 0) <= time_counter_S(15 downto 0) + 1;
+ end if;
+ end if;
+ end process;
+\r
+ blink_H : process (clk_200_osc)
+ begin
+ if (rising_edge(clk_200_osc) and (time_counter_S(15 downto 0) = x"FFFF"))then
+ if ((time_counter_S(31 downto 16) = x"FFFF") and (time_counter_S(15 downto 0) = x"FFFF")) then
+ time_counter_S(31 downto 16) <= x"0000";
+ else
+ time_counter_S(31 downto 16) <= time_counter_S(31 downto 16) + 1;
+ end if;
+ end if;
+ end process;
+
+
+ TEST_LINE(15 downto 3) <= time_counter_S(31 downto 19); --(others => '0'); -- otherwise it is floating
+ TEST_LINE(2) <= '1';
+ TEST_LINE(1) <= '1';
+ TEST_LINE(0) <= '1';
+-- TEST_LINE(7 downto 0) <= (others => '1'); -- otherwise it is floating
+-- TEST_LINE(15 downto 8) <= (others => '0'); -- otherwise it is floating
end trb3_periph_EP_soda4source_arch;
\ No newline at end of file
---------------
-- TOP LEVEL --
---------------
-
+-- TAB=3 !!
+-- 24/11/2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
);
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of SFP_MOD0 : signal is false;
+ attribute syn_useioff of SFP_TXDIS : signal is false;
+ attribute syn_useioff of SFP_LOS : signal is false;
+ attribute syn_useioff of TEST_LINE : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
end entity;
architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
- --Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
--- signal clk_raw_internal : std_logic;
- signal clk_200_osc : std_logic;
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
+
+ --Clock / Reset
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR : std_logic;
+ signal GSR_N : std_logic;
+\r
signal clk_100_osc : std_logic;
+ signal clk_200_osc : std_logic;
signal rx_full_clk : std_logic;
signal rx_half_clk : std_logic;
signal tx_full_clk : std_logic;
signal tx_half_clk : std_logic;
--- signal clk_tdc : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- --media interface
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci1_nack : std_logic;
+ signal time_counter, time_counter2 : unsigned(31 downto 0);
+ \r
+ --Media Interface
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+ --media interface
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+ signal sci1_nack : std_logic;
signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
--SODA
---signal soda_rx_clock_half : std_logic;
---signal soda_rx_clock_full : std_logic;
-signal tx_dlm_i : std_logic;
-signal rx_dlm_i : std_logic;
-signal tx_dlm_word : std_logic_vector(7 downto 0);
-signal rx_dlm_word : std_logic_vector(7 downto 0);
-signal make_reset : std_logic;
-signal tx_dlm_preview_S : std_logic; --PL!
-signal link_phase_S : std_logic; --PL!
-signal rx_cdr_lol_S : std_logic;
-signal link_locked_S : std_logic; --PL!
+ signal tx_dlm_i : std_logic;
+ signal rx_dlm_i : std_logic;
+ signal tx_dlm_word : std_logic_vector(7 downto 0);
+ signal rx_dlm_word : std_logic_vector(7 downto 0);
+ signal make_reset : std_logic;
+ signal tx_dlm_preview_S : std_logic; --PL!
+ signal link_phase_S : std_logic; --PL!
+ signal rx_cdr_lol_S : std_logic;
+ signal link_locked_S : std_logic; --PL!
-- SODA slow controll
- signal soda_ack : std_logic;
--- signal soda_nack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
+ signal soda_ack : std_logic;
+-- signal soda_nack : std_logic;
+ signal soda_write : std_logic;
+ signal soda_read : std_logic;
+ signal soda_data_in : std_logic_vector(31 downto 0);
+ signal soda_data_out : std_logic_vector(31 downto 0);
+ signal soda_addr : std_logic_vector(3 downto 0);
+ signal soda_leds : std_logic_vector(3 downto 0);
signal link_debug_in_S : std_logic_vector(31 downto 0);
- signal general_reset_i : std_logic := '1';
+ signal general_reset_i : std_logic := '1';
signal soda_counter_i : unsigned(3 downto 0);
- attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
attribute syn_preserve of rx_full_clk : signal is true;
attribute syn_keep of rx_full_clk : signal is true;
attribute syn_preserve of rx_half_clk : signal is true;
attribute syn_keep of tx_dlm_i : signal is true;
attribute syn_preserve of rx_dlm_i : signal is true;
attribute syn_keep of rx_dlm_i : signal is true;
+ attribute syn_keep of GSR : signal is true;
+ attribute syn_preserve of GSR : signal is true;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ attribute syn_keep of soda_counter_i : signal is true;
+ attribute syn_preserve of soda_counter_i : signal is true;
begin
LED_LINKOK <= (others => '0'); -- otherwise it is floating
GSR_N <= pll_lock;\r
+ GSR <= not(pll_lock);
THE_RESET_HANDLER : trb_net_reset_handler
generic map(
port map(
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => rx_half_clk, --clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => rx_half_clk, --clk_100_osc, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', --general_reset_i, --'0', -- general reset signal (SYSCLK) --peter schakel
TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
DEBUG_OUT => open
);
--- process(clk_100_osc)
--- begin
--- if rising_edge(clk_100_osc) then
--- general_reset_i <= not SFP_LOS(1);
--- end if;
--- end process;
+ process(rx_half_clk)
+ begin
+ if rising_edge(rx_half_clk) then
+ general_reset_i <= not SFP_LOS(1);
+ end if;
+ end process;
---------------------------------------------------------------------------
-- Clock Handling
---------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc, --clk_raw_internal,
- LOCK => pll_lock
- );
-end generate;
+--gen_200_PLL : if USE_125_MHZ = c_NO generate
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_100_osc,
+ CLKOK => clk_200_osc,
+ LOCK => pll_lock
+ );
+--end generate;
--gen_125 : if USE_125_MHZ = c_YES generate
-- clk_100_osc <= CLK_GPLL_LEFT;
THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
port map(
- CLK_IN => rx_half_clk, --clk_100_osc,
+ CLK_IN => clk_100_osc, --rx_half_clk,
RESET_IN => reset_i,
BUS_ADDR_IN => spimem_addr,
THE_SYNC_LINK : med_ecp3_sfp_sync_up
generic map(
- SERDES_NUM => 1, --number of serdes in quad
- IS_SYNC_SLAVE => c_YES
+ SERDES_NUM => 1, --number of serdes in quad
+ IS_SYNC_SLAVE => c_YES
)
port map(
- OSCCLK => clk_200_osc, --clk_raw_internal,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
+ OSCCLK => clk_200_osc,
+ SYSCLK => clk_100_osc,
+ RESET => reset_i,
+ CLEAR => clear_i,
--Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
RX_HALF_CLK_OUT => rx_half_clk, --soda_rx_clock_half,
RX_FULL_CLK_OUT => rx_full_clk, --soda_rx_clock_full,
TX_HALF_CLK_OUT => tx_half_clk,
TX_FULL_CLK_OUT => tx_full_clk,
- RX_CDR_LOL_OUT => rx_cdr_lol_S,\r
+ RX_CDR_LOL_OUT => rx_cdr_lol_S,
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
- LINK_PHASE_OUT => link_phase_S, --PL!
+ RX_DLM => rx_dlm_i,
+ RX_DLM_WORD => rx_dlm_word,
+ TX_DLM => tx_dlm_i,
+ TX_DLM_WORD => tx_dlm_word,
+ TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
+ LINK_PHASE_OUT => link_phase_S, --PL!
--SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(4), --(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(5), --(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(4), --(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(5), --(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(3), --(1),
- SD_LOS_IN => SFP_LOS(3), --(1),
- SD_TXDIS_OUT => sfp_txdis_S(3), --(1), --SFP_TXDIS(1),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- SCI_NACK => sci1_nack,
+ SD_RXD_P_IN => SERDES_ADDON_RX(4), --(0),
+ SD_RXD_N_IN => SERDES_ADDON_RX(5), --(1),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4), --(0),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5), --(1),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(3), --(1),
+ SD_LOS_IN => SFP_LOS(3), --(1),
+ SD_TXDIS_OUT => sfp_txdis_S(3), --(1), --SFP_TXDIS(1),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ SCI_NACK => sci1_nack,
-- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );\r
+\r
-
-- SFP_TXDIS(1) <= sfp_txdis_S(1);
SFP_TXDIS <= sfp_txdis_S;
---------------------------------------------------------------------------
-- The Soda Central
----------------------------------------------------------------------------
+---------------------------------------------------------------------------
A_SODA_CLIENT : soda_client
port map(
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);
- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);
- LED_GREEN <= med_stat_op(12); --tx_pll_lol
- LED_RED <= med_stat_op(11); --rx_cdr_lol
+ LED_ORANGE <= '0'; --reset_i; --med_stat_op(8);
+ LED_YELLOW <= '1'; --clear_i; --med_stat_op(10);
+ LED_GREEN <= pll_lock; --tx_pll_lol
+ LED_RED <= time_counter(26); --rx_cdr_lol
-- LED_ORANGE <= not reset_i when rising_edge(clk_100_osc);
-- LED_YELLOW <= soda_leds(0); --'1';
-- LED_GREEN <= not med_stat_op(9);
---------------------------------------------------------------------------
-- Test Circuits
---------------------------------------------------------------------------
- clock_counter_proc : process(clk_100_osc)
+ blink : process (clk_100_osc)
begin
if rising_edge(clk_100_osc) then
- time_counter <= time_counter + 1;
+ if (time_counter = x"FFFFFFFF") then
+ time_counter <= x"00000000";
+ else
+ time_counter <= time_counter + 1;
+ end if;
end if;
- end process;
+ end process;\r
process(rx_full_clk) --soda_rx_clock_full) --clk_soda_i)
begin
soda_counter_i <= soda_counter_i+1;
end if;
end process;
-
- TEST_LINE(0) <= time_counter(1);
- TEST_LINE(1) <= '0';
- TEST_LINE(2) <= '0';
- TEST_LINE(3) <= soda_counter_i(2);
- TEST_LINE(4) <= '0';
- TEST_LINE(5) <= '0';
- TEST_LINE(6) <= rx_half_clk;
- TEST_LINE(7) <= '0';
- TEST_LINE(8) <= '0';
-
- TEST_LINE(15 downto 9) <= (others => '0'); -- otherwise it is floating
-end trb3_periph_sodaclient_arch;
\ No newline at end of file
+end trb3_periph_sodaclient_arch;
--- /dev/null
+--Media interface for Lattice ECP3 using PCS at 2GHz\r
+\r
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.med_sync_define.all;\r
+\r
+entity trb_net16_med_1_2sync_3_ecp3_sfp is\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ CLK_RX_HALF_OUT : out std_logic;\r
+ CLK_RX_FULL_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
+ SCI_NACK : out std_logic := '0';\r
+ -- SODA serdes channel\r
+ SODA_RXD_P_IN : in std_logic;\r
+ SODA_RXD_N_IN : in std_logic;\r
+ SODA_TXD_P_OUT : out std_logic;\r
+ SODA_TXD_N_OUT : out std_logic;\r
+ SODA_DLM_IN : in std_logic;\r
+ SODA_DLM_WORD_IN : in std_logic_vector(7 downto 0);\r
+ SODA_DLM_OUT : out std_logic;\r
+ SODA_DLM_WORD_OUT : out std_logic_vector(7 downto 0);\r
+ SODA_CLOCK_OUT : out std_logic; -- 200MHz\r
+ \r
+ -- Connection to addon interface \r
+ DOUT_TXD_P_OUT : out std_logic;\r
+ DOUT_TXD_N_OUT : out std_logic;\r
+ SFP_MOD0_5 : in std_logic;\r
+ SFP_MOD0_3 : in std_logic; \r
+ SFP_LOS_5 : in std_logic; \r
+ SFP_LOS_3 : in std_logic;\r
+ TX_READY_CH3 : out std_logic;\r
+ TX_DATA_CH3 : in std_logic_vector(7 downto 0);\r
+ TX_K_CH3 : in std_logic;\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is\r
+\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "media_interface_group";\r
+ attribute syn_sharing : string;\r
+ attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";\r
+\r
+ --OJK 29-nov-2013\r
+ component sfp_1_3_200_int\r
+ port(\r
+ hdinp_ch1 : IN std_logic;
+ hdinn_ch1 : IN std_logic;
+ sci_sel_ch1 : IN std_logic;
+ rxiclk_ch1 : IN std_logic;
+ txiclk_ch1 : IN std_logic;
+ fpga_rxrefclk_ch1 : IN std_logic;
+ txdata_ch1 : IN std_logic_vector(15 downto 0);
+ tx_k_ch1 : IN std_logic_vector(1 downto 0);
+ tx_force_disp_ch1 : IN std_logic_vector(1 downto 0);
+ tx_disp_sel_ch1 : IN std_logic_vector(1 downto 0);
+ sb_felb_ch1_c : IN std_logic;
+ sb_felb_rst_ch1_c : IN std_logic;
+ tx_pwrup_ch1_c : IN std_logic;
+ rx_pwrup_ch1_c : IN std_logic;
+ tx_div2_mode_ch1_c : IN std_logic;
+ rx_div2_mode_ch1_c : IN std_logic;
+ sci_sel_ch3 : IN std_logic;
+ txiclk_ch3 : IN std_logic;
+ fpga_rxrefclk_ch3 : IN std_logic;
+ txdata_ch3 : IN std_logic_vector(7 downto 0);
+ tx_k_ch3 : IN std_logic;
+ tx_force_disp_ch3 : IN std_logic;
+ tx_disp_sel_ch3 : IN std_logic;
+ tx_pwrup_ch3_c : IN std_logic;
+ tx_div2_mode_ch3_c : IN std_logic;
+ sci_wrdata : IN std_logic_vector(7 downto 0);
+ sci_addr : IN std_logic_vector(5 downto 0);
+ sci_sel_quad : IN std_logic;
+ sci_rd : IN std_logic;
+ sci_wrn : IN std_logic;
+ fpga_txrefclk : IN std_logic;
+ tx_serdes_rst_c : IN std_logic;
+ tx_sync_qd_c : IN std_logic;
+ rst_n : IN std_logic;
+ serdes_rst_qd_c : IN std_logic;
+ hdoutp_ch1 : OUT std_logic;
+ hdoutn_ch1 : OUT std_logic;
+ rx_full_clk_ch1 : OUT std_logic;
+ rx_half_clk_ch1 : OUT std_logic;
+ tx_full_clk_ch1 : OUT std_logic;
+ tx_half_clk_ch1 : OUT std_logic;
+ rxdata_ch1 : OUT std_logic_vector(15 downto 0);
+ rx_k_ch1 : OUT std_logic_vector(1 downto 0);
+ rx_disp_err_ch1 : OUT std_logic_vector(1 downto 0);
+ rx_cv_err_ch1 : OUT std_logic_vector(1 downto 0);
+ rx_los_low_ch1_s : OUT std_logic;
+ lsm_status_ch1_s : OUT std_logic;
+ rx_cdr_lol_ch1_s : OUT std_logic;
+ hdoutp_ch3 : OUT std_logic;
+ hdoutn_ch3 : OUT std_logic;
+ tx_full_clk_ch3 : OUT std_logic;
+ tx_half_clk_ch3 : OUT std_logic;
+ sci_rddata : OUT std_logic_vector(7 downto 0);
+ tx_pll_lol_qd_s : OUT std_logic;
+ refclk2fpga : OUT std_logic\r
+ );\r
+ end component;\r
+ \r
+-- Peter Schakel 02-12-14\r
+component sfp_1_2sync_3_200_int is\r
+ port (\r
+------------------\r
+-- CH0 --\r
+-- CH1 --\r
+ hdinp_ch1, hdinn_ch1 : in std_logic;\r
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;\r
+ sci_sel_ch1 : in std_logic;\r
+ rxiclk_ch1 : in std_logic;\r
+ txiclk_ch1 : in std_logic;\r
+ rx_full_clk_ch1 : out std_logic;\r
+ rx_half_clk_ch1 : out std_logic;\r
+ tx_full_clk_ch1 : out std_logic;\r
+ tx_half_clk_ch1 : out std_logic;\r
+ fpga_rxrefclk_ch1 : in std_logic;\r
+ txdata_ch1 : in std_logic_vector (15 downto 0);\r
+ tx_k_ch1 : in std_logic_vector (1 downto 0);\r
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);\r
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);\r
+ rxdata_ch1 : out std_logic_vector (15 downto 0);\r
+ rx_k_ch1 : out std_logic_vector (1 downto 0);\r
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);\r
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);\r
+ rx_serdes_rst_ch1_c : in std_logic;\r
+ sb_felb_ch1_c : in std_logic;\r
+ sb_felb_rst_ch1_c : in std_logic;\r
+ tx_pcs_rst_ch1_c : in std_logic;\r
+ tx_pwrup_ch1_c : in std_logic;\r
+ rx_pcs_rst_ch1_c : in std_logic;\r
+ rx_pwrup_ch1_c : in std_logic;\r
+ rx_los_low_ch1_s : out std_logic;\r
+ lsm_status_ch1_s : out std_logic;\r
+ rx_cdr_lol_ch1_s : out std_logic;\r
+ tx_div2_mode_ch1_c : in std_logic;\r
+ rx_div2_mode_ch1_c : in std_logic;\r
+-- CH2 --\r
+ hdinp_ch2, hdinn_ch2 : in std_logic;\r
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;\r
+ sci_sel_ch2 : in std_logic;\r
+ rxiclk_ch2 : in std_logic;\r
+ txiclk_ch2 : in std_logic;\r
+ rx_full_clk_ch2 : out std_logic;\r
+ rx_half_clk_ch2 : out std_logic;\r
+ tx_full_clk_ch2 : out std_logic;\r
+ tx_half_clk_ch2 : out std_logic;\r
+ fpga_rxrefclk_ch2 : in std_logic;\r
+ txdata_ch2 : in std_logic_vector (7 downto 0);\r
+ tx_k_ch2 : in std_logic;\r
+ tx_force_disp_ch2 : in std_logic;\r
+ tx_disp_sel_ch2 : in std_logic;\r
+ rxdata_ch2 : out std_logic_vector (7 downto 0);\r
+ rx_k_ch2 : out std_logic;\r
+ rx_disp_err_ch2 : out std_logic;\r
+ rx_cv_err_ch2 : out std_logic;\r
+ rx_serdes_rst_ch2_c : in std_logic;\r
+ sb_felb_ch2_c : in std_logic;\r
+ sb_felb_rst_ch2_c : in std_logic;\r
+ tx_pcs_rst_ch2_c : in std_logic;\r
+ tx_pwrup_ch2_c : in std_logic;\r
+ rx_pcs_rst_ch2_c : in std_logic;\r
+ rx_pwrup_ch2_c : in std_logic;\r
+ rx_los_low_ch2_s : out std_logic;\r
+ lsm_status_ch2_s : out std_logic;\r
+ rx_cdr_lol_ch2_s : out std_logic;\r
+ tx_div2_mode_ch2_c : in std_logic;\r
+ rx_div2_mode_ch2_c : in std_logic;\r
+-- CH3 --\r
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;\r
+ sci_sel_ch3 : in std_logic;\r
+ txiclk_ch3 : in std_logic;\r
+ tx_full_clk_ch3 : out std_logic;\r
+ tx_half_clk_ch3 : out std_logic;\r
+ txdata_ch3 : in std_logic_vector (7 downto 0);\r
+ tx_k_ch3 : in std_logic;\r
+ tx_force_disp_ch3 : in std_logic;\r
+ tx_disp_sel_ch3 : in std_logic;\r
+ tx_pcs_rst_ch3_c : in std_logic;\r
+ tx_pwrup_ch3_c : in std_logic;\r
+ tx_div2_mode_ch3_c : in std_logic;\r
+---- Miscillaneous ports\r
+ sci_wrdata : in std_logic_vector (7 downto 0);\r
+ sci_addr : in std_logic_vector (5 downto 0);\r
+ sci_rddata : out std_logic_vector (7 downto 0);\r
+ sci_sel_quad : in std_logic;\r
+ sci_rd : in std_logic;\r
+ sci_wrn : in std_logic;\r
+ fpga_txrefclk : in std_logic;\r
+ tx_serdes_rst_c : in std_logic;\r
+ tx_pll_lol_qd_s : out std_logic;\r
+ tx_sync_qd_c : in std_logic;\r
+ rst_qd_c : in std_logic;\r
+ serdes_rst_qd_c : in std_logic);\r
+\r
+end component;\r
+\r
+ \r
+ \r
+ signal refck2core : std_logic;\r
+-- signal clock : std_logic;\r
+ --reset signals\r
+ signal ffc_quad_rst : std_logic;\r
+ signal ffc_lane_tx_rst : std_logic;\r
+ signal ffc_lane_rx_rst : std_logic;\r
+ --serdes connections\r
+ signal tx_data : std_logic_vector(15 downto 0);\r
+ signal tx_k : std_logic_vector(1 downto 0);\r
+ signal rx_data : std_logic_vector(15 downto 0); -- delayed signals\r
+ signal rx_k : std_logic_vector(1 downto 0); -- delayed signals\r
+ signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP\r
+ signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP\r
+ signal link_ok : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits\r
+ signal link_error : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits\r
+ signal ff_txhalfclk : std_logic;\r
+ signal ff_rxhalfclk : std_logic;\r
+ signal ff_rxfullclk : std_logic;\r
+ --rx fifo signals\r
+ signal fifo_rx_rd_en : std_logic;\r
+ signal fifo_rx_wr_en : std_logic;\r
+ signal fifo_rx_reset : std_logic;\r
+ signal fifo_rx_din : std_logic_vector(17 downto 0);\r
+ signal fifo_rx_dout : std_logic_vector(17 downto 0);\r
+ signal fifo_rx_full : std_logic;\r
+ signal fifo_rx_empty : std_logic;\r
+ --tx fifo signals\r
+ signal fifo_tx_rd_en : std_logic;\r
+ signal fifo_tx_wr_en : std_logic;\r
+ signal fifo_tx_reset : std_logic;\r
+ signal fifo_tx_din : std_logic_vector(17 downto 0);\r
+ signal fifo_tx_dout : std_logic_vector(17 downto 0);\r
+ signal fifo_tx_full : std_logic;\r
+ signal fifo_tx_empty : std_logic;\r
+ signal fifo_tx_almost_full : std_logic;\r
+ --rx path\r
+ signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ signal buf_med_dataready_out : std_logic;\r
+ signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ signal last_rx : std_logic_vector(8 downto 0);\r
+ signal last_fifo_rx_empty : std_logic;\r
+ --tx path\r
+ signal last_fifo_tx_empty : std_logic;\r
+ --link status\r
+ signal rx_k_q : std_logic_vector(1 downto 0);\r
+\r
+ signal quad_rst : std_logic;\r
+ signal lane_rst : std_logic;\r
+ signal tx_allow : std_logic;\r
+ signal rx_allow : std_logic;\r
+ signal tx_allow_qtx : std_logic;\r
+\r
+ signal rx_allow_q : std_logic; -- clock domain changed signal\r
+ signal tx_allow_q : std_logic;\r
+ signal swap_bytes : std_logic;\r
+ signal buf_stat_debug : std_logic_vector(31 downto 0);\r
+\r
+ -- status inputs from SFP\r
+ signal sfp_prsnt_n : std_logic; -- synchronized input signals\r
+ signal sfp_los : std_logic; -- synchronized input signals\r
+\r
+ signal buf_STAT_OP : std_logic_vector(15 downto 0);\r
+\r
+ signal led_counter : unsigned(16 downto 0);\r
+ signal rx_led : std_logic;\r
+ signal tx_led : std_logic;\r
+\r
+\r
+ signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion\r
+ signal first_idle : std_logic; -- tag the first IDLE2 after data\r
+\r
+ signal reset_word_cnt : unsigned(4 downto 0);\r
+ signal make_trbnet_reset : std_logic;\r
+ signal make_trbnet_reset_q : std_logic;\r
+ signal send_reset_words : std_logic;\r
+ signal send_reset_words_q : std_logic;\r
+ signal send_reset_in : std_logic;\r
+ signal send_reset_in_qtx : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal reset_i_rx : std_logic;\r
+ signal pwr_up : std_logic;\r
+ signal clear_n : std_logic;\r
+\r
+ signal clk_sys : std_logic;\r
+ signal clk_tx : std_logic;\r
+ signal clk_rx : std_logic;\r
+ signal clk_rxref : std_logic;\r
+ signal clk_txref : std_logic;\r
+\r
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
+signal sci_state : sci_ctrl;\r
+ signal sci_ch_i : std_logic_vector(3 downto 0);\r
+ signal sci_qd_i : std_logic;\r
+ signal sci_reg_i : std_logic;\r
+ signal sci_addr_i : std_logic_vector(8 downto 0);\r
+ signal sci_data_in_i : std_logic_vector(7 downto 0);\r
+ signal sci_data_out_i : std_logic_vector(7 downto 0);\r
+ signal sci_read_i : std_logic;\r
+ signal sci_write_i : std_logic;\r
+-- signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
+-- signal sci_read_shift_i : std_logic_vector(2 downto 0); \r
+ \r
+ --OJK 13-dec-2013\r
+ signal cnt : integer range 0 to 10000;\r
+ signal tx_pll_lol_qd_i : std_logic;\r
+ -- Peter Schakel 3-dec-2014\r
+ \r
+ signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
+ signal reset_n : std_logic;\r
+ signal trb_rx_serdes_rst : std_logic;\r
+ signal trb_rx_cdr_lol : std_logic;\r
+ signal trb_rx_los_low : std_logic;\r
+ signal trb_rx_pcs_rst : std_logic;\r
+ signal trb_tx_pcs_rst : std_logic;\r
+ signal rst_qd : std_logic;\r
+ signal link_OK_S : std_logic;\r
+ signal trb_rx_fsm_state : std_logic_vector(3 downto 0);\r
+ \r
+ signal sync_clk_rx_full : std_logic;\r
+ signal sync_clk_rx_half : std_logic;\r
+ signal sync_clk_tx_full : std_logic;\r
+ signal sync_clk_tx_half : std_logic;\r
+ signal sync_tx_k : std_logic;\r
+ signal sync_tx_data : std_logic_vector(7 downto 0);\r
+\r
+ signal syncfifo_din : std_logic_vector(17 downto 0);\r
+ signal syncfifo_dout : std_logic_vector(17 downto 0);\r
+ \r
+ signal sync_rx_k : std_logic;\r
+ signal sync_rx_data : std_logic_vector(7 downto 0);\r
+ signal sync_rx_serdes_rst : std_logic;\r
+ signal sync_rx_cdr_lol : std_logic;\r
+ signal sync_tx_pcs_rst : std_logic;\r
+ signal sync_rx_pcs_rst : std_logic;\r
+ signal sync_rx_los_low : std_logic;\r
+ signal sync_lsm_status : std_logic;\r
+ signal SD_tx_pcs_rst : std_logic;\r
+ signal DLM_fifo_rd_en : std_logic;\r
+ signal DLM_fifo_empty : std_logic;\r
+ signal DLM_fifo_reading : std_logic := '0'; \r
+ signal SODA_dlm_word_S : std_logic_vector(7 downto 0);\r
+ signal DLM_received_S : std_logic;\r
+ signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
+ signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
+ signal sync_rx_fsm_state : std_logic_vector(3 downto 0);\r
+ signal sync_tx_fsm_state : std_logic_vector(3 downto 0);\r
+ signal CH3_tx_fsm_state : std_logic_vector(3 downto 0);\r
+\r
+ signal CLKdiv100_S : std_logic;\r
+ signal sync_clk_rx_fulldiv100_S : std_logic;\r
+ \r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_keep of led_counter : signal is true;\r
+ attribute syn_keep of send_reset_in : signal is true;\r
+ attribute syn_keep of reset_i : signal is true;\r
+ attribute syn_preserve of reset_i : signal is true;\r
+\r
+begin\r
+\r
+--------------------------------------------------------------------------\r
+-- Select proper clock configuration\r
+--------------------------------------------------------------------------\r
+ clk_sys <= SYSCLK;\r
+ clk_tx <= SYSCLK;\r
+ clk_rx <= ff_rxhalfclk;\r
+ clk_rxref <= CLK;\r
+ clk_txref <= CLK;\r
+\r
+\r
+\r
+\r
+--------------------------------------------------------------------------\r
+-- Internal Lane Resets\r
+--------------------------------------------------------------------------\r
+ clear_n <= not clear;\r
+\r
+\r
+ PROC_RESET : process(clk_sys)\r
+ begin\r
+ if rising_edge(clk_sys) then\r
+ reset_i <= RESET;\r
+ send_reset_in <= ctrl_op(15);\r
+ pwr_up <= '1'; --not CTRL_OP(i*16+14);\r
+ end if;\r
+ end process;\r
+\r
+--------------------------------------------------------------------------\r
+-- Synchronizer stages\r
+--------------------------------------------------------------------------\r
+\r
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)\r
+THE_SFP_STATUS_SYNC: signal_sync\r
+ generic map(\r
+ DEPTH => 3,\r
+ WIDTH => 2\r
+ )\r
+ port map(\r
+ RESET => '0',\r
+ D_IN(0) => sd_prsnt_n_in,\r
+ D_IN(1) => sd_los_in,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_sys,\r
+ D_OUT(0) => sfp_prsnt_n,\r
+ D_OUT(1) => sfp_los\r
+ );\r
+\r
+\r
+THE_RX_K_SYNC: signal_sync\r
+ generic map(\r
+ DEPTH => 1,\r
+ WIDTH => 4\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ D_IN(1 downto 0) => comb_rx_k,\r
+ D_IN(2) => send_reset_words,\r
+ D_IN(3) => make_trbnet_reset,\r
+ CLK0 => clk_rx, -- CHANGED\r
+ CLK1 => clk_sys,\r
+ D_OUT(1 downto 0) => rx_k_q,\r
+ D_OUT(2) => send_reset_words_q,\r
+ D_OUT(3) => make_trbnet_reset_q\r
+ );\r
+\r
+THE_RX_DATA_DELAY: signal_sync\r
+ generic map(\r
+ DEPTH => 2,\r
+ WIDTH => 16\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ D_IN => comb_rx_data,\r
+ CLK0 => clk_rx,\r
+ CLK1 => clk_rx,\r
+ D_OUT => rx_data\r
+ );\r
+\r
+THE_RX_K_DELAY: signal_sync\r
+ generic map(\r
+ DEPTH => 2,\r
+ WIDTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ D_IN => comb_rx_k,\r
+ CLK0 => clk_rx,\r
+ CLK1 => clk_rx,\r
+ D_OUT => rx_k\r
+ );\r
+\r
+THE_RX_RESET: signal_sync\r
+ generic map(\r
+ DEPTH => 1,\r
+ WIDTH => 1\r
+ )\r
+ port map(\r
+ RESET => '0',\r
+ D_IN(0) => reset_i,\r
+ CLK0 => clk_rx,\r
+ CLK1 => clk_rx,\r
+ D_OUT(0) => reset_i_rx\r
+ );\r
+\r
+-- Delay for ALLOW signals\r
+THE_RX_ALLOW_SYNC: signal_sync\r
+ generic map(\r
+ DEPTH => 2,\r
+ WIDTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ D_IN(0) => rx_allow,\r
+ D_IN(1) => tx_allow,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_sys,\r
+ D_OUT(0) => rx_allow_q,\r
+ D_OUT(1) => tx_allow_q\r
+ );\r
+\r
+THE_TX_SYNC: signal_sync\r
+ generic map(\r
+ DEPTH => 1,\r
+ WIDTH => 2\r
+ )\r
+ port map(\r
+ RESET => '0',\r
+ D_IN(0) => send_reset_in,\r
+ D_IN(1) => tx_allow,\r
+ CLK0 => clk_tx,\r
+ CLK1 => clk_tx,\r
+ D_OUT(0) => send_reset_in_qtx,\r
+ D_OUT(1) => tx_allow_qtx\r
+ );\r
+\r
+\r
+--------------------------------------------------------------------------\r
+-- Main control state machine, startup control for SFP\r
+--------------------------------------------------------------------------\r
+\r
+THE_SFP_LSM: trb_net16_lsm_sfp\r
+ generic map (\r
+ HIGHSPEED_STARTUP => c_YES\r
+ )\r
+ port map(\r
+ SYSCLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLEAR => clear,\r
+ SFP_MISSING_IN => sfp_prsnt_n,\r
+ SFP_LOS_IN => sfp_los,\r
+ SD_LINK_OK_IN => link_OK_S, --// ?? link_ok(0),\r
+ SD_LOS_IN => link_error(8),\r
+ SD_TXCLK_BAD_IN => link_error(5),\r
+ SD_RXCLK_BAD_IN => link_error(4),\r
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope\r
+ SD_ALIGNMENT_IN => rx_k_q,\r
+ SD_CV_IN => link_error(7 downto 6),\r
+ FULL_RESET_OUT => quad_rst,\r
+ LANE_RESET_OUT => lane_rst,\r
+ TX_ALLOW_OUT => tx_allow,\r
+ RX_ALLOW_OUT => rx_allow,\r
+ SWAP_BYTES_OUT => swap_bytes,\r
+ STAT_OP => buf_stat_op,\r
+ CTRL_OP => ctrl_op,\r
+ STAT_DEBUG => buf_stat_debug\r
+ );\r
+\r
+sd_txdis_out <= quad_rst or reset_i;\r
+\r
+--------------------------------------------------------------------------\r
+--------------------------------------------------------------------------\r
+\r
+ffc_quad_rst <= quad_rst;\r
+ffc_lane_tx_rst <= lane_rst;\r
+\r
+\r
+ffc_lane_rx_rst <= lane_rst;\r
+\r
+-- SerDes clock output to FPGA fabric\r
+REFCLK2CORE_OUT <= ff_rxhalfclk;\r
+CLK_RX_HALF_OUT <= ff_rxhalfclk;\r
+CLK_RX_FULL_OUT <= ff_rxfullclk;\r
+\r
+THE_SERDES: sfp_1_2sync_3_200_int port map(\r
+------------------\r
+-- CH0 --\r
+-- CH1 --\r
+ hdinp_ch1 => sd_rxd_p_in, \r
+ hdinn_ch1 => sd_rxd_n_in, \r
+ hdoutp_ch1 => sd_txd_p_out, \r
+ hdoutn_ch1 => sd_txd_n_out, \r
+\r
+ sci_sel_ch1 => sci_ch_i(1),\r
+ rxiclk_ch1 => clk_rx, \r
+ txiclk_ch1 => clk_tx, \r
+ rx_full_clk_ch1 => ff_rxfullclk, \r
+ rx_half_clk_ch1 => ff_rxhalfclk, \r
+ tx_full_clk_ch1 => open, \r
+ tx_half_clk_ch1 => ff_txhalfclk, \r
+ fpga_rxrefclk_ch1 => clk_rxref, \r
+ txdata_ch1 => tx_data, \r
+ tx_k_ch1 => tx_k, \r
+ tx_force_disp_ch1 => tx_correct, \r
+ tx_disp_sel_ch1 => "00", \r
+ rxdata_ch1 => comb_rx_data, \r
+ rx_k_ch1 => comb_rx_k, \r
+ rx_disp_err_ch1 => open, \r
+ rx_cv_err_ch1 => link_error(7 downto 6),\r
+ rx_serdes_rst_ch1_c => trb_rx_serdes_rst,\r
+ sb_felb_ch1_c => '0', \r
+ sb_felb_rst_ch1_c => '0', \r
+ tx_pcs_rst_ch1_c => trb_tx_pcs_rst,\r
+ tx_pwrup_ch1_c => '1', \r
+ rx_pcs_rst_ch1_c => trb_rx_pcs_rst,\r
+ rx_pwrup_ch1_c => '1', \r
+ rx_los_low_ch1_s => trb_rx_los_low, -- link_error(8), \r
+ lsm_status_ch1_s => link_ok(0), \r
+ rx_cdr_lol_ch1_s => trb_rx_cdr_lol, -- link_error(4), \r
+ tx_div2_mode_ch1_c => '0', \r
+ rx_div2_mode_ch1_c => '0',\r
+\r
+-- CH2 --\r
+ hdinp_ch2 => SODA_RXD_P_IN,\r
+ hdinn_ch2 => SODA_RXD_N_IN,\r
+ hdoutp_ch2 => SODA_TXD_P_OUT,\r
+ hdoutn_ch2 => SODA_TXD_N_OUT,\r
+ sci_sel_ch2 => sci_ch_i(2),\r
+ rxiclk_ch2 => sync_clk_rx_full, -- ?? CLK,\r
+ txiclk_ch2 => sync_clk_tx_full, -- ??CLK, --????? clk_txref\r
+ rx_full_clk_ch2 => sync_clk_rx_full,\r
+ rx_half_clk_ch2 => sync_clk_rx_half,\r
+ tx_full_clk_ch2 => sync_clk_tx_full,\r
+ tx_half_clk_ch2 => sync_clk_tx_half,\r
+ fpga_rxrefclk_ch2 => CLK,\r
+ txdata_ch2 => sync_tx_data,\r
+ tx_k_ch2 => sync_tx_k,\r
+ tx_force_disp_ch2 => '0',\r
+ tx_disp_sel_ch2 => '0',\r
+ rxdata_ch2 => sync_rx_data,\r
+ rx_k_ch2 => sync_rx_k,\r
+ rx_disp_err_ch2 => open,\r
+ rx_cv_err_ch2 => open,\r
+ rx_serdes_rst_ch2_c => sync_rx_serdes_rst,\r
+ sb_felb_ch2_c => '0',\r
+ sb_felb_rst_ch2_c => '0',\r
+ tx_pcs_rst_ch2_c => sync_tx_pcs_rst,\r
+ tx_pwrup_ch2_c => '1',\r
+ rx_pcs_rst_ch2_c => sync_rx_pcs_rst,\r
+ rx_pwrup_ch2_c => '1',\r
+ rx_los_low_ch2_s => sync_rx_los_low,\r
+ lsm_status_ch2_s => sync_lsm_status,\r
+ rx_cdr_lol_ch2_s => sync_rx_cdr_lol,\r
+ tx_div2_mode_ch2_c => '0',\r
+ rx_div2_mode_ch2_c => '0',\r
+ \r
+-- CH3 --\r
+ hdoutp_ch3 => DOUT_TXD_P_OUT, \r
+ hdoutn_ch3 => DOUT_TXD_N_OUT, \r
+ sci_sel_ch3 => '0', --disable access to channel 3 registers\r
+ txiclk_ch3 => clk_tx, \r
+ tx_full_clk_ch3 => open, \r
+ tx_half_clk_ch3 => open, \r
+--//???? fpga_rxrefclk_ch3 => clk_rxref, \r
+ txdata_ch3 => tx_data_ch3, \r
+ tx_k_ch3 => tx_k_ch3,\r
+ tx_force_disp_ch3 => '0', \r
+ tx_disp_sel_ch3 => '0', \r
+ tx_pcs_rst_ch3_c => SD_tx_pcs_rst,\r
+ tx_pwrup_ch3_c => '1', \r
+ tx_div2_mode_ch3_c => '1', \r
+\r
+---- Miscillaneous ports\r
+ sci_wrdata => sci_data_in_i,\r
+ sci_addr => sci_addr_i(5 downto 0),\r
+ sci_rddata => sci_data_out_i,\r
+ sci_sel_quad => sci_qd_i,\r
+ sci_rd => sci_read_i,\r
+ sci_wrn => sci_write_i,\r
+ fpga_txrefclk => clk_txref, \r
+ tx_serdes_rst_c => CLEAR, \r
+ tx_pll_lol_qd_s => tx_pll_lol_qd_i, \r
+ tx_sync_qd_c => '0', -- Multiple channel transmit synchronization is not needed?\r
+--// refclk2fpga => open, -- Not needed?\r
+ rst_qd_c => rst_qd,\r
+--//?? rst_n => '1', \r
+ serdes_rst_qd_c => ffc_quad_rst \r
+ );\r
+\r
+ syncfifo_din(7 downto 0) <= SODA_DLM_WORD_IN;\r
+ syncfifo_din(17 downto 8) <= (others => '0');\r
+ SODA_dlm_word_S <= syncfifo_dout(7 downto 0);\r
+sync_DLM_tx: trb_net_fifo_16bit_bram_dualport\r
+generic map(\r
+ USE_STATUS_FLAGS => c_NO\r
+ )\r
+port map( read_clock_in => sync_clk_tx_full,\r
+ write_clock_in => sync_clk_rx_full, \r
+ read_enable_in => DLM_fifo_rd_en,\r
+ write_enable_in => SODA_DLM_IN,\r
+ fifo_gsr_in => reset,\r
+ write_data_in => syncfifo_din,\r
+ read_data_out => syncfifo_dout,\r
+ full_out => open,\r
+ empty_out => DLM_fifo_empty\r
+ );\r
+\r
+process(sync_clk_rx_full)\r
+begin\r
+ if rising_edge(sync_clk_rx_full) then\r
+ SODA_DLM_OUT <= '0';\r
+ if DLM_received_S='1' then\r
+ DLM_received_S <= '0';\r
+ SODA_DLM_OUT <= '1';\r
+ SODA_DLM_WORD_OUT <= sync_rx_data;\r
+ elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then\r
+ DLM_received_S <= '1';\r
+ end if;\r
+ end if;\r
+end process; \r
+\r
+process(sync_clk_tx_full)\r
+begin\r
+ if rising_edge(sync_clk_tx_full) then\r
+ if DLM_fifo_rd_en='1' then\r
+ DLM_fifo_rd_en <= '0';\r
+ sync_tx_data <= SODA_dlm_word_S;\r
+ sync_tx_k <= '0';\r
+ elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then\r
+ DLM_fifo_rd_en <= '1';\r
+ sync_tx_data <= x"DC";\r
+ sync_tx_k <= '1';\r
+ elsif DLM_fifo_empty='0' then\r
+ DLM_fifo_reading <= '1';\r
+ DLM_fifo_rd_en <= '0';\r
+ sync_tx_data <= x"BC"; -- idle\r
+ sync_tx_k <= '1'; \r
+ else\r
+ DLM_fifo_reading <= '0';\r
+ DLM_fifo_rd_en <= '0';\r
+ sync_tx_data <= x"BC"; -- idle\r
+ sync_tx_k <= '1';\r
+ end if;\r
+ end if;\r
+end process; \r
+SODA_CLOCK_OUT <= sync_clk_rx_full;\r
+\r
+\r
+link_error(8) <= trb_rx_los_low; -- loss of signal\r
+link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock \r
+link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock\r
+\r
+reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';\r
+\r
+------------------------------------------------- \r
+-- Reset FSM & Link states\r
+------------------------------------------------- \r
+THE_RX_FSM1: rx_reset_fsm\r
+ port map(\r
+ RST_N => reset_n,\r
+ RX_REFCLK => CLK,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
+ RX_SERDES_RST_CH_C => trb_rx_serdes_rst,\r
+ RX_CDR_LOL_CH_S => trb_rx_cdr_lol,\r
+ RX_LOS_LOW_CH_S => trb_rx_los_low,\r
+ RX_PCS_RST_CH_C => trb_rx_pcs_rst,\r
+ WA_POSITION => "0000",\r
+ STATE_OUT => trb_rx_fsm_state\r
+ );\r
+\r
+link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';\r
+THE_TX_FSM1: tx_reset_fsm\r
+ port map(\r
+ RST_N => reset_n,\r
+ TX_REFCLK => CLK,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
+ RST_QD_C => rst_qd,\r
+ TX_PCS_RST_CH_C => trb_tx_pcs_rst,\r
+ STATE_OUT => open\r
+ );\r
+\r
+THE_RX_FSM2: rx_reset_fsm\r
+ port map(\r
+ RST_N => reset_n,\r
+ RX_REFCLK => sync_clk_rx_full, --??CLK,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
+ RX_SERDES_RST_CH_C => sync_rx_serdes_rst,\r
+ RX_CDR_LOL_CH_S => sync_rx_cdr_lol,\r
+ RX_LOS_LOW_CH_S => sync_rx_los_low,\r
+ RX_PCS_RST_CH_C => sync_rx_pcs_rst,\r
+ WA_POSITION => sync_wa_position_rx(11 downto 8),\r
+ STATE_OUT => sync_rx_fsm_state\r
+ );\r
+SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)\r
+begin\r
+ if rising_edge(sync_clk_rx_full) then\r
+ sync_wa_position_rx <= wa_position;\r
+ end if;\r
+end process;\r
+ \r
+THE_TX_FSM2: tx_reset_fsm\r
+ port map(\r
+ RST_N => reset_n,\r
+ TX_REFCLK => CLK,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
+ RST_QD_C => open, --??\r
+ TX_PCS_RST_CH_C => sync_tx_pcs_rst,\r
+ STATE_OUT => sync_tx_fsm_state\r
+ );\r
+ \r
+THE_TX_FSM3 : tx_reset_fsm\r
+ port map(\r
+ RST_N => reset_n,\r
+ TX_REFCLK => CLK,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
+ RST_QD_C => open, --??\r
+ TX_PCS_RST_CH_C => SD_tx_pcs_rst,\r
+ STATE_OUT => CH3_tx_fsm_state\r
+ );\r
+TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';\r
+ \r
+ \r
+-------------------------------------------------------------------------\r
+-- RX Fifo & Data output\r
+-------------------------------------------------------------------------\r
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport\r
+generic map(\r
+ USE_STATUS_FLAGS => c_NO\r
+ )\r
+port map( read_clock_in => clk_sys,\r
+ write_clock_in => clk_rx, -- CHANGED\r
+ read_enable_in => fifo_rx_rd_en,\r
+ write_enable_in => fifo_rx_wr_en,\r
+ fifo_gsr_in => fifo_rx_reset,\r
+ write_data_in => fifo_rx_din,\r
+ read_data_out => fifo_rx_dout,\r
+ full_out => fifo_rx_full,\r
+ empty_out => fifo_rx_empty\r
+ );\r
+\r
+fifo_rx_reset <= reset_i or not rx_allow_q;\r
+fifo_rx_rd_en <= not fifo_rx_empty;\r
+\r
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path\r
+THE_BYTE_SWAP_PROC: process(clk_rx)\r
+ begin\r
+ if rising_edge(clk_rx) then\r
+ last_rx <= rx_k(1) & rx_data(15 downto 8);\r
+ if( swap_bytes = '0' ) then\r
+ fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);\r
+ fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);\r
+ else\r
+ fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);\r
+ fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);\r
+ end if;\r
+ end if;\r
+ end process THE_BYTE_SWAP_PROC;\r
+\r
+buf_med_data_out <= fifo_rx_dout(15 downto 0);\r
+buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;\r
+buf_med_packet_num_out <= rx_counter;\r
+med_read_out <= tx_allow_q and not fifo_tx_almost_full;\r
+\r
+\r
+THE_CNT_RESET_PROC : process(clk_rx)\r
+ begin\r
+ if rising_edge(clk_rx) then\r
+ if reset_i_rx = '1' then\r
+ send_reset_words <= '0';\r
+ make_trbnet_reset <= '0';\r
+ reset_word_cnt <= (others => '0');\r
+ else\r
+ send_reset_words <= '0';\r
+ make_trbnet_reset <= '0';\r
+ if fifo_rx_din = "11" & x"FEFE" then\r
+ if reset_word_cnt(4) = '0' then\r
+ reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);\r
+ else\r
+ send_reset_words <= '1';\r
+ end if;\r
+ else\r
+ reset_word_cnt <= (others => '0');\r
+ make_trbnet_reset <= reset_word_cnt(4);\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+THE_SYNC_PROC: process(clk_rx)\r
+ begin\r
+ if rising_edge(clk_rx) then\r
+ med_dataready_out <= buf_med_dataready_out;\r
+ med_data_out <= buf_med_data_out;\r
+ med_packet_num_out <= buf_med_packet_num_out;\r
+ if reset_i = '1' then\r
+ med_dataready_out <= '0';\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+--rx packet counter\r
+---------------------\r
+THE_RX_PACKETS_PROC: process( clk_sys )\r
+ begin\r
+ if( rising_edge(clk_sys) ) then\r
+ last_fifo_rx_empty <= fifo_rx_empty;\r
+ if reset_i = '1' or rx_allow_q = '0' then\r
+ rx_counter <= c_H0;\r
+ else\r
+ if( buf_med_dataready_out = '1' ) then\r
+ if( rx_counter = c_max_word_number ) then\r
+ rx_counter <= (others => '0');\r
+ else\r
+ rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+--TX Fifo & Data output to Serdes\r
+---------------------\r
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport\r
+ generic map(\r
+ USE_STATUS_FLAGS => c_NO\r
+ )\r
+ port map( read_clock_in => clk_tx,\r
+ write_clock_in => clk_sys,\r
+ read_enable_in => fifo_tx_rd_en,\r
+ write_enable_in => fifo_tx_wr_en,\r
+ fifo_gsr_in => fifo_tx_reset,\r
+ write_data_in => fifo_tx_din,\r
+ read_data_out => fifo_tx_dout,\r
+ full_out => fifo_tx_full,\r
+ empty_out => fifo_tx_empty,\r
+ almost_full_out => fifo_tx_almost_full\r
+ );\r
+\r
+fifo_tx_reset <= reset_i or not tx_allow_q;\r
+fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;\r
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;\r
+fifo_tx_rd_en <= tx_allow_qtx;\r
+\r
+\r
+THE_SERDES_INPUT_PROC: process( clk_tx )\r
+ begin\r
+ if( rising_edge(clk_tx) ) then\r
+ last_fifo_tx_empty <= fifo_tx_empty;\r
+ first_idle <= not last_fifo_tx_empty and fifo_tx_empty;\r
+ if send_reset_in = '1' then\r
+ tx_data <= x"FEFE";\r
+ tx_k <= "11";\r
+ elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then\r
+ tx_data <= x"50bc";\r
+ tx_k <= "01";\r
+ tx_correct <= first_idle & '0';\r
+ else\r
+ tx_data <= fifo_tx_dout(15 downto 0);\r
+ tx_k <= "00";\r
+ tx_correct <= "00";\r
+ end if;\r
+ end if;\r
+ end process THE_SERDES_INPUT_PROC;\r
+\r
+------------------------------------------------- \r
+-- SCI\r
+------------------------------------------------- \r
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
+PROC_SCI_CTRL: process(clk_sys)\r
+ variable cnt : integer range 0 to 4 := 0;\r
+begin\r
+ if( rising_edge(clk_sys) ) then\r
+ SCI_ACK <= '0';\r
+ case sci_state is\r
+ when IDLE =>\r
+ sci_ch_i <= x"0";\r
+ sci_qd_i <= '0';\r
+ sci_reg_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_write_i <= '0';\r
+ sci_timer <= sci_timer + 1;\r
+ if SCI_READ = '1' or SCI_WRITE = '1' then\r
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
+ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
+ sci_addr_i <= SCI_ADDR;\r
+ sci_data_in_i <= SCI_DATA_IN;\r
+ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
+ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
+ sci_state <= SCTRL;\r
+ elsif sci_timer(sci_timer'left) = '1' then\r
+ sci_timer <= (others => '0');\r
+ sci_state <= GET_WA;\r
+ end if; \r
+ when SCTRL =>\r
+ if sci_reg_i = '1' then\r
+--// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
+ SCI_DATA_OUT <= (others => '0');\r
+ SCI_ACK <= '1';\r
+ sci_write_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_state <= IDLE;\r
+ else\r
+ sci_state <= SCTRL_WAIT;\r
+ end if;\r
+ when SCTRL_WAIT =>\r
+ sci_state <= SCTRL_WAIT2;\r
+ when SCTRL_WAIT2 =>\r
+ sci_state <= SCTRL_FINISH;\r
+ when SCTRL_FINISH =>\r
+ SCI_DATA_OUT <= sci_data_out_i;\r
+ SCI_ACK <= '1';\r
+ sci_write_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_state <= IDLE;\r
+ \r
+ when GET_WA =>\r
+ if cnt = 4 then\r
+ cnt := 0;\r
+ sci_state <= IDLE;\r
+ else\r
+ sci_state <= GET_WA_WAIT;\r
+ sci_addr_i <= '0' & x"22";\r
+ sci_ch_i <= x"0";\r
+ sci_ch_i(cnt) <= '1';\r
+ sci_read_i <= '1';\r
+ end if;\r
+ when GET_WA_WAIT =>\r
+ sci_state <= GET_WA_WAIT2;\r
+ when GET_WA_WAIT2 =>\r
+ sci_state <= GET_WA_FINISH;\r
+ when GET_WA_FINISH =>\r
+ wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
+ sci_state <= GET_WA; \r
+ cnt := cnt + 1;\r
+ end case;\r
+ \r
+ if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
+ SCI_NACK <= '1';\r
+ else\r
+ SCI_NACK <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+ \r
+ \r
+\r
+--Generate LED signals\r
+----------------------\r
+process( clk_sys )\r
+ begin\r
+ if rising_edge(clk_sys) then\r
+ led_counter <= led_counter + to_unsigned(1,1);\r
+\r
+ if buf_med_dataready_out = '1' then\r
+ rx_led <= '1';\r
+ elsif led_counter = 0 then\r
+ rx_led <= '0';\r
+ end if;\r
+\r
+ if tx_k(0) = '0' then\r
+ tx_led <= '1';\r
+ elsif led_counter = 0 then\r
+ tx_led <= '0';\r
+ end if;\r
+\r
+ end if;\r
+ end process;\r
+\r
+stat_op(15) <= send_reset_words_q;\r
+stat_op(14) <= buf_stat_op(14);\r
+stat_op(13) <= make_trbnet_reset_q;\r
+stat_op(12) <= '0';\r
+stat_op(11) <= tx_led; --tx led\r
+stat_op(10) <= rx_led; --rx led\r
+stat_op(9 downto 0) <= buf_stat_op(9 downto 0);\r
+\r
+-- Debug output\r
+stat_debug(15 downto 0) <= rx_data;\r
+stat_debug(17 downto 16) <= rx_k;\r
+stat_debug(19 downto 18) <= (others => '0');\r
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);\r
+stat_debug(24) <= fifo_rx_rd_en;\r
+stat_debug(25) <= fifo_rx_wr_en;\r
+stat_debug(26) <= fifo_rx_reset;\r
+stat_debug(27) <= fifo_rx_empty;\r
+stat_debug(28) <= fifo_rx_full;\r
+stat_debug(29) <= last_rx(8);\r
+stat_debug(30) <= rx_allow_q;\r
+stat_debug(41 downto 31) <= (others => '0');\r
+stat_debug(42) <= clk_sys;\r
+stat_debug(43) <= clk_sys;\r
+stat_debug(59 downto 44) <= (others => '0');\r
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);\r
+\r
+--stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits\r
+--stat_debug(4) <= buf_stat_debug(4); -- alignme\r
+--stat_debug(5) <= sfp_prsnt_n;\r
+--stat_debug(6) <= tx_k(0);\r
+--stat_debug(7) <= tx_k(1);\r
+--stat_debug(8) <= rx_k_q(0);\r
+--stat_debug(9) <= rx_k_q(1);\r
+--stat_debug(18 downto 10) <= link_error;\r
+--stat_debug(19) <= '0';\r
+--stat_debug(20) <= link_ok(0);\r
+--stat_debug(38 downto 21) <= fifo_rx_din;\r
+--stat_debug(39) <= swap_bytes;\r
+--stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in\r
+--stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in\r
+--stat_debug(42) <= buf_stat_debug(6); -- resync\r
+--stat_debug(59 downto 43) <= (others => '0');\r
+--stat_debug(63 downto 60) <= link_error(3 downto 0);\r
+\r
+CLKdiv100_process: process(CLK)\r
+variable counter_V : integer range 0 to 99 := 0;\r
+begin\r
+ if (rising_edge(CLK)) then \r
+ if counter_V<49 then -- 99 for 125MHz\r
+ counter_V := counter_V+1;\r
+ else\r
+ counter_V := 0;\r
+ CLKdiv100_S <= not CLKdiv100_S;\r
+ end if;\r
+ end if;\r
+end process;\r
+sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)\r
+variable counter_V : integer range 0 to 99 := 0;\r
+begin\r
+ if (rising_edge(sync_clk_rx_full)) then \r
+ if counter_V<49 then -- 99 for 125MHz\r
+ counter_V := counter_V+1;\r
+ else\r
+ counter_V := 0;\r
+ sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+end architecture;
\ No newline at end of file
--- /dev/null
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity Cu_trb_net16_soda_sync_ecp3_sfp is
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 0;
+ EXT_CLOCK : integer range 0 to 1 := c_NO;
+ USE_200_MHZ : integer range 0 to 1 := c_YES;
+ USE_125_MHZ : integer range 0 to 1 := c_NO;
+ USE_CTC : integer range 0 to 1 := c_NO;
+ USE_SLAVE : integer range 0 to 1 := c_NO;
+ SODA_IS_SYNC_SLAVE : integer range 0 to 1 := c_YES
+ );
+ port(
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic := '0';
+ --Internal Connection RX
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic := '0';
+ MED_READ_IN : in std_logic;
+ -- sync clocks
+ SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+
+ --Copper SFP Connection
+ CU_RXD_P_IN : in std_logic;
+ CU_RXD_N_IN : in std_logic;
+ CU_TXD_P_OUT : out std_logic;
+ CU_TXD_N_OUT : out std_logic;
+ CU_REFCLK_P_IN : in std_logic; --not used
+ CU_REFCLK_N_IN : in std_logic; --not used
+ CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Fiber SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+end entity;
+
+architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3_sfp is
+
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "media_interface_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "off";
+
+ component sfp_2_200_int
+ port
+ (
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (15 downto 0);
+ tx_k_ch1 : in std_logic_vector (1 downto 0);
+ tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
+ tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
+ rxdata_ch1 : out std_logic_vector (15 downto 0);
+ rx_k_ch1 : out std_logic_vector (1 downto 0);
+ rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
+ rx_serdes_rst_ch1_c : in std_logic;
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pcs_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pcs_rst_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+ ---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ rst_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ serdes_rst_qd_c : in std_logic
+ );
+ end component;
+
+ signal refck2core : std_logic;
+ -- signal clock : std_logic;
+ --reset signals
+ signal ffc_quad_rst : std_logic;
+ signal ffc_lane_tx_rst : std_logic;
+ signal ffc_lane_rx_rst : std_logic;
+ --serdes connections
+ signal tx_data : std_logic_vector(15 downto 0);
+ signal tx_k : std_logic_vector(1 downto 0);
+ signal rx_data : std_logic_vector(15 downto 0); -- delayed signals
+ signal rx_k : std_logic_vector(1 downto 0); -- delayed signals
+ signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP
+ signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP
+ signal link_ok : std_logic_vector(0 downto 0);
+ signal link_error : std_logic_vector(8 downto 0);
+ signal ff_txhalfclk : std_logic;
+ signal ff_rxhalfclk : std_logic;
+ signal ff_rxfullclk : std_logic;
+ --rx fifo signals
+ signal fifo_rx_rd_en : std_logic;
+ signal fifo_rx_wr_en : std_logic;
+ signal fifo_rx_reset : std_logic;
+ signal fifo_rx_din : std_logic_vector(17 downto 0);
+ signal fifo_rx_dout : std_logic_vector(17 downto 0);
+ signal fifo_rx_full : std_logic;
+ signal fifo_rx_empty : std_logic;
+ --tx fifo signals
+ signal fifo_tx_rd_en : std_logic;
+ signal fifo_tx_wr_en : std_logic;
+ signal fifo_tx_reset : std_logic;
+ signal fifo_tx_din : std_logic_vector(17 downto 0);
+ signal fifo_tx_dout : std_logic_vector(17 downto 0);
+ signal fifo_tx_full : std_logic;
+ signal fifo_tx_empty : std_logic;
+ signal fifo_tx_almost_full : std_logic;
+ --rx path
+ signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal buf_med_dataready_out : std_logic;
+ signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal last_rx : std_logic_vector(8 downto 0);
+ signal last_fifo_rx_empty : std_logic;
+ --tx path
+ signal last_fifo_tx_empty : std_logic;
+ --link status
+ signal rx_k_q : std_logic_vector(1 downto 0);
+
+ signal quad_rst : std_logic;
+ signal lane_rst : std_logic;
+ signal tx_allow : std_logic;
+ signal rx_allow : std_logic;
+ signal tx_allow_qtx : std_logic;
+
+ signal rx_allow_q : std_logic; -- clock domain changed signal
+ signal tx_allow_q : std_logic;
+ signal swap_bytes : std_logic;
+ signal buf_stat_debug : std_logic_vector(31 downto 0);
+
+ -- status inputs from SFP
+ signal sfp_prsnt_n : std_logic; -- synchronized input signals
+ signal sfp_los : std_logic; -- synchronized input signals
+
+ signal buf_STAT_OP : std_logic_vector(15 downto 0);
+
+ signal led_counter : unsigned(16 downto 0);
+ signal rx_led : std_logic;
+ signal tx_led : std_logic;
+
+
+ signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+ signal first_idle : std_logic; -- tag the first IDLE2 after data
+
+ signal reset_word_cnt : unsigned(4 downto 0);
+ signal make_trbnet_reset : std_logic;
+ signal make_trbnet_reset_q : std_logic;
+ signal send_reset_words : std_logic;
+ signal send_reset_words_q : std_logic;
+ signal send_reset_in : std_logic;
+ signal send_reset_in_qtx : std_logic;
+ signal reset_i : std_logic;
+ signal reset_i_rx : std_logic;
+ signal pwr_up : std_logic;
+ signal clear_n : std_logic;
+
+ signal clk_sys : std_logic;
+ signal clk_tx : std_logic;
+ signal clk_rx : std_logic;
+ signal clk_rxref : std_logic;
+ signal clk_txref : std_logic;
+
+ -- Peter Schakel 3-dec-2014
+
+ signal sci_timer : unsigned(12 downto 0) := (others => '0');
+ signal reset_n : std_logic;
+ signal trb_rx_serdes_rst : std_logic;
+ signal trb_rx_cdr_lol : std_logic;
+ signal trb_rx_los_low : std_logic;
+ signal trb_rx_pcs_rst : std_logic;
+ signal trb_tx_pcs_rst : std_logic;
+ signal rst_qd : std_logic;
+ signal link_OK_S : std_logic;
+ signal trb_rx_fsm_state : std_logic_vector(3 downto 0);
+ signal clk_200_osc : std_logic;
+ signal sync_rx_full_clk : std_logic;
+ signal sync_rx_half_clk : std_logic;
+ signal sync_tx_full_clk : std_logic;
+ signal sync_tx_half_clk : std_logic;
+\r
+ signal rst_n : std_logic;
+ signal rst : std_logic; -- PL!
+ signal sync_tx_data : std_logic_vector(7 downto 0);
+ signal sync_tx_k : std_logic;
+ signal sync_rx_data : std_logic_vector(7 downto 0);
+ signal sync_rx_k : std_logic;
+ signal sync_rx_error : std_logic;
+ signal sync_rx_serdes_rst : std_logic;
+ signal sync_tx_pcs_rst : std_logic;
+ signal sync_rx_pcs_rst : std_logic;
+ signal sync_rx_los_low : std_logic;
+ signal sync_lsm_status : std_logic;
+ signal sync_rx_cdr_lol : std_logic;
+ signal sd_los_i : std_logic; --PL!
+
+ signal sci_ch_i : std_logic_vector(3 downto 0);
+ signal sci_addr_i : std_logic_vector(8 downto 0);
+ signal sci_data_in_i : std_logic_vector(7 downto 0);
+ signal sci_data_out_i : std_logic_vector(7 downto 0);
+ signal sci_read_i : std_logic;
+ signal sci_write_i : std_logic;
+ signal sci_write_shift_i : std_logic_vector(2 downto 0);
+ signal sci_read_shift_i : std_logic_vector(2 downto 0);
+\r
+ signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
+ signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
+ signal sync_tx_allow : std_logic;
+ signal sync_rx_allow : std_logic;
+ signal sync_tx_allow_q : std_logic;
+ signal sync_rx_allow_q : std_logic;
+ signal link_phase_S : std_logic; --PL!
+ signal request_retr_i : std_logic;
+ signal start_retr_i : std_logic;
+ signal request_retr_position_i : std_logic_vector(7 downto 0);
+ signal start_retr_position_i : std_logic_vector(7 downto 0);
+ signal send_link_reset_i : std_logic;
+ signal make_link_reset_i : std_logic;
+ signal got_link_ready_i : std_logic;
+ signal internal_make_link_reset_out : std_logic;
+
+ signal start_timer : unsigned(18 downto 0) := (others => '0');
+ signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
+ signal watchdog_trigger : std_logic :='0';
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+ attribute syn_keep of led_counter : signal is true;
+ attribute syn_keep of send_reset_in : signal is true;
+ attribute syn_keep of reset_i : signal is true;
+ attribute syn_preserve of reset_i : signal is true;
+ attribute syn_preserve of sci_ch_i : signal is true;--
+ attribute syn_keep of sci_ch_i : signal is true;--
+ attribute syn_preserve of sci_addr_i : signal is true;--
+ attribute syn_keep of sci_addr_i : signal is true;--
+ attribute syn_preserve of sci_data_in_i : signal is true;--
+ attribute syn_keep of sci_data_in_i : signal is true;--
+ attribute syn_preserve of sci_data_out_i : signal is true;--
+ attribute syn_keep of sci_data_out_i : signal is true;--
+ attribute syn_preserve of sci_read_i : signal is true;--
+ attribute syn_keep of sci_read_i : signal is true;--
+ attribute syn_preserve of sci_write_i : signal is true;--
+ attribute syn_keep of sci_write_i : signal is true;--
+ attribute syn_preserve of sci_write_shift_i : signal is true;--
+ attribute syn_keep of sci_write_shift_i : signal is true;--
+ attribute syn_preserve of sci_read_shift_i : signal is true;--
+ attribute syn_keep of sci_read_shift_i : signal is true;--
+ attribute syn_preserve of wa_position : signal is true;--
+ attribute syn_keep of wa_position : signal is true;--
+ attribute syn_preserve of wa_position_rx : signal is true;--
+ attribute syn_keep of wa_position_rx : signal is true;--
+
+begin
+
+clk_200_osc <= OSCCLK;
+
+SYNC_RX_HALF_CLK_OUT <= sync_rx_half_clk;
+SYNC_RX_FULL_CLK_OUT <= sync_rx_full_clk;
+SYNC_TX_HALF_CLK_OUT <= sync_tx_half_clk;
+SYNC_TX_FULL_CLK_OUT <= sync_tx_full_clk;
+--RX_CDR_LOL_OUT <= rx_cdr_lol;
+
+clk_sys <= SYSCLK;
+clk_tx <= SYSCLK;
+clk_rx <= ff_rxhalfclk;
+clk_rxref <= OSCCLK;
+clk_txref <= OSCCLK;
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+clear_n <= not clear;
+\r
+internal_make_link_reset_out <= make_link_reset_i when SODA_IS_SYNC_SLAVE = c_YES else '0';
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
+\r
+rst_n <= not(CLEAR or SD_LOS_IN or internal_make_link_reset_out or watchdog_trigger);
+rst <= (CLEAR or SD_LOS_IN or internal_make_link_reset_out or watchdog_trigger);
+
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+ PROC_RESET : process(clk_sys)
+ begin
+ if rising_edge(clk_sys) then
+ reset_i <= RESET;
+ send_reset_in <= ctrl_op(15);
+ pwr_up <= '1'; --not CTRL_OP(i*16+14);
+ end if;
+ end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => sd_prsnt_n_in,
+ D_IN(1) => sd_los_in,
+ CLK0 => clk_sys,
+ CLK1 => clk_sys,
+ D_OUT(0) => sfp_prsnt_n,
+ D_OUT(1) => sfp_los
+ );
+
+
+THE_RX_K_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 4
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(1 downto 0) => comb_rx_k,
+ D_IN(2) => send_reset_words,
+ D_IN(3) => make_trbnet_reset,
+ CLK0 => clk_rx, -- CHANGED
+ CLK1 => clk_sys,
+ D_OUT(1 downto 0) => rx_k_q,
+ D_OUT(2) => send_reset_words_q,
+ D_OUT(3) => make_trbnet_reset_q
+ );
+
+THE_RX_DATA_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 16
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_data,
+ CLK0 => clk_rx,
+ CLK1 => clk_rx,
+ D_OUT => rx_data
+ );
+
+THE_RX_K_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_k,
+ CLK0 => clk_rx,
+ CLK1 => clk_rx,
+ D_OUT => rx_k
+ );
+
+THE_RX_RESET: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => reset_i,
+ CLK0 => clk_rx,
+ CLK1 => clk_rx,
+ D_OUT(0) => reset_i_rx
+ );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(0) => rx_allow,
+ D_IN(1) => tx_allow,
+ CLK0 => clk_sys,
+ CLK1 => clk_sys,
+ D_OUT(0) => rx_allow_q,
+ D_OUT(1) => tx_allow_q
+ );
+
+THE_TX_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => send_reset_in,
+ D_IN(1) => tx_allow,
+ CLK0 => clk_tx,
+ CLK1 => clk_tx,
+ D_OUT(0) => send_reset_in_qtx,
+ D_OUT(1) => tx_allow_qtx
+ );
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+ generic map (
+ HIGHSPEED_STARTUP => c_YES
+ )
+ port map(
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear,
+ SFP_MISSING_IN => sfp_prsnt_n,
+ SFP_LOS_IN => sfp_los,
+ SD_LINK_OK_IN => link_ok(0),
+ SD_LOS_IN => link_error(8),
+ SD_TXCLK_BAD_IN => link_error(5),
+ SD_RXCLK_BAD_IN => link_error(4),
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => rx_k_q,
+ SD_CV_IN => link_error(7 downto 6),
+ FULL_RESET_OUT => quad_rst,
+ LANE_RESET_OUT => lane_rst,
+ TX_ALLOW_OUT => tx_allow,
+ RX_ALLOW_OUT => rx_allow,
+ SWAP_BYTES_OUT => swap_bytes,
+ STAT_OP => buf_stat_op,
+ CTRL_OP => ctrl_op,
+ STAT_DEBUG => buf_stat_debug
+ );
+
+sd_txdis_out <= quad_rst or reset_i;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+ffc_quad_rst <= quad_rst;
+ffc_lane_tx_rst <= lane_rst;
+
+
+ffc_lane_rx_rst <= lane_rst;
+\r
+
+
+-- Instantiation of serdes module
+
+ THE_SERDES: sfp_2_200_int
+ port map(
+ HDINP_CH1 => cu_rxd_p_in,
+ HDINN_CH1 => cu_rxd_n_in,
+ HDOUTP_CH1 => cu_txd_p_out,
+ HDOUTN_CH1 => cu_txd_n_out,
+ SCI_SEL_CH1 => sci_ch_i(1),
+ RXICLK_CH1 => clk_rx,
+ TXICLK_CH1 => clk_tx,
+ RX_FULL_CLK_CH1 => ff_rxfullclk,
+ RX_HALF_CLK_CH1 => ff_rxhalfclk,
+ TX_FULL_CLK_CH1 => open,
+ TX_HALF_CLK_CH1 => ff_txhalfclk,
+ FPGA_RXREFCLK_CH1 => clk_rxref,
+ TXDATA_CH1 => tx_data,
+ TX_K_CH1 => tx_k,
+ TX_FORCE_DISP_CH1 => tx_correct,
+ TX_DISP_SEL_CH1 => "00",
+ RXDATA_CH1 => comb_rx_data,
+ RX_K_CH1 => comb_rx_k,
+ RX_DISP_ERR_CH1 => open,
+ RX_CV_ERR_CH1 => link_error(7 downto 6),
+ RX_SERDES_RST_CH1_C => trb_rx_serdes_rst,
+ SB_FELB_CH1_C => '0', --loopback enable
+ SB_FELB_RST_CH1_C => '0', --loopback reset
+ TX_PCS_RST_CH1_C => trb_tx_pcs_rst, --'1', --tx power up
+ TX_PWRUP_CH1_C => '1', --tx power up
+ RX_PCS_RST_CH1_C => trb_rx_pcs_rst, --'1', --rx power up
+ RX_PWRUP_CH1_C => '1', --rx power up
+ RX_LOS_LOW_CH1_S => trb_rx_los_low, --link_error(8),
+ LSM_STATUS_CH1_S => link_ok(0),
+ RX_CDR_LOL_CH1_S => trb_rx_cdr_lol, --link_error(4),
+ TX_DIV2_MODE_CH1_C => '0', --full rate
+ RX_DIV2_MODE_CH1_C => '0', --full rate
+
+ HDINP_CH3 => sd_rxd_p_in,
+ HDINN_CH3 => sd_rxd_n_in,
+ HDOUTP_CH3 => sd_txd_p_out,
+ HDOUTN_CH3 => sd_txd_n_out,
+ SCI_SEL_CH3 => sci_ch_i(3),
+ TXICLK_CH3 => sync_rx_full_clk,
+ RX_FULL_CLK_CH3 => sync_rx_full_clk,
+ RX_HALF_CLK_CH3 => sync_rx_half_clk,
+ TX_FULL_CLK_CH3 => sync_tx_full_clk,
+ TX_HALF_CLK_CH3 => sync_tx_half_clk,
+ FPGA_RXREFCLK_CH3 => clk_200_osc,
+ TXDATA_CH3 => sync_tx_data,
+ TX_K_CH3 => sync_tx_k,
+ TX_FORCE_DISP_CH3 => '0',
+ TX_DISP_SEL_CH3 => '0',
+ RXDATA_CH3 => sync_rx_data,
+ RX_K_CH3 => sync_rx_k,
+ RX_DISP_ERR_CH3 => open,
+ RX_CV_ERR_CH3 => sync_rx_error,
+ RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
+ SB_FELB_CH3_C => '0', --loopback enable
+ SB_FELB_RST_CH3_C => '0', --loopback reset
+ TX_PCS_RST_CH3_C => sync_tx_pcs_rst,
+ TX_PWRUP_CH3_C => '1',
+ RX_PCS_RST_CH3_C => sync_rx_pcs_rst,
+ RX_PWRUP_CH3_C => '1',
+ RX_LOS_LOW_CH3_S => sync_rx_los_low,
+ LSM_STATUS_CH3_S => sync_lsm_status,
+ RX_CDR_LOL_CH3_S => sync_rx_cdr_lol,
+ TX_DIV2_MODE_CH3_C => '0',
+ RX_DIV2_MODE_CH3_C => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_RDDATA => sci_data_out_i,
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+ FPGA_TXREFCLK => clk_txref,
+-- FPGA_TXREFCLK => rx_full_clk,
+ TX_SERDES_RST_C => CLEAR,
+ TX_PLL_LOL_QD_S => link_error(5),
+ TX_SYNC_QD_C => '0',
+ RST_QD_C => '0',
+ REFCLK2FPGA => open,
+ SERDES_RST_QD_C => ffc_quad_rst
+ );
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+port map( read_clock_in => clk_sys,
+ write_clock_in => clk_rx, -- CHANGED
+ read_enable_in => fifo_rx_rd_en,
+ write_enable_in => fifo_rx_wr_en,
+ fifo_gsr_in => fifo_rx_reset,
+ write_data_in => fifo_rx_din,
+ read_data_out => fifo_rx_dout,
+ full_out => fifo_rx_full,
+ empty_out => fifo_rx_empty
+ );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process
+ begin
+ wait until rising_edge(clk_rx); --CHANGED
+ last_rx <= rx_k(1) & rx_data(15 downto 8);
+ if( swap_bytes = '0' ) then
+ fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+ fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
+ else
+ fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+ fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
+ end if;
+ end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out <= rx_counter;
+med_read_out <= tx_allow_q and not fifo_tx_almost_full;
+
+
+THE_CNT_RESET_PROC : process
+ begin
+ wait until rising_edge(clk_rx); --CHANGED
+ if reset_i_rx = '1' then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ else
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if fifo_rx_din = "11" & x"FEFE" then
+ if reset_word_cnt(4) = '0' then
+ reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= reset_word_cnt(4);
+ end if;
+ end if;
+ end process;
+
+
+THE_SYNC_PROC: process
+ begin
+ wait until rising_edge(clk_sys);
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ if reset_i = '1' then
+ med_dataready_out <= '0';
+ end if;
+ end process;
+
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( clk_sys )
+ begin
+ if( rising_edge(clk_sys) ) then
+ last_fifo_rx_empty <= fifo_rx_empty;
+ if reset_i = '1' or rx_allow_q = '0' then
+ rx_counter <= c_H0;
+ else
+ if( buf_med_dataready_out = '1' ) then
+ if( rx_counter = c_max_word_number ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map( read_clock_in => clk_tx,
+ write_clock_in => clk_sys,
+ read_enable_in => fifo_tx_rd_en,
+ write_enable_in => fifo_tx_wr_en,
+ fifo_gsr_in => fifo_tx_reset,
+ write_data_in => fifo_tx_din,
+ read_data_out => fifo_tx_dout,
+ full_out => fifo_tx_full,
+ empty_out => fifo_tx_empty,
+ almost_full_out => fifo_tx_almost_full
+ );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow_qtx;
+
+
+THE_SERDES_INPUT_PROC: process( clk_tx )
+ begin
+ if( rising_edge(clk_tx) ) then
+ last_fifo_tx_empty <= fifo_tx_empty;
+ first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
+ if send_reset_in = '1' then
+ tx_data <= x"FEFE";
+ tx_k <= "11";
+ elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
+ tx_data <= x"50bc";
+ tx_k <= "01";
+ tx_correct <= first_idle & '0';
+ else
+ tx_data <= fifo_tx_dout(15 downto 0);
+ tx_k <= "00";
+ tx_correct <= "00";
+ end if;
+ end if;
+ end process THE_SERDES_INPUT_PROC;
+
+PROC_START_TIMER : process(sync_rx_full_clk)
+begin
+ if rising_edge(sync_rx_full_clk) then
+ if got_link_ready_i = '1' then
+ watchdog_timer <= (others => '0');
+ if start_timer(start_timer'left) = '0' then
+ start_timer <= start_timer + 1;
+ end if;
+ else
+ start_timer <= (others => '0');
+ if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
+ watchdog_trigger <= '1';
+ else
+ watchdog_trigger <= '0';
+ end if;
+ if watchdog_trigger = '0' then
+ watchdog_timer <= watchdog_timer + 1;
+ else
+ watchdog_timer <= (others => '0');
+ end if;
+ end if;
+ end if;
+end process;
+--SCI
+----------------------
+PROC_SCI : process begin
+ wait until rising_edge(clk_sys);
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ end if;
+ sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ;
+ sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+ SCI_DATA_OUT <= sci_data_out_i;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i <= or_all(sci_read_shift_i);
+SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+
+
+
+
+--Generate LED signals
+----------------------
+process( clk_sys )
+ begin
+ if rising_edge(clk_sys) then
+ led_counter <= led_counter + to_unsigned(1,1);
+
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+
+ if tx_k(0) = '0' then
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+
+ end if;
+ end process;
+\r
+
+stat_op(15) <= send_reset_words_q;
+stat_op(14) <= buf_stat_op(14);
+stat_op(13) <= make_trbnet_reset_q;
+stat_op(12) <= '0';
+stat_op(11) <= tx_led; --tx led
+stat_op(10) <= rx_led; --rx led
+stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0) <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24) <= fifo_rx_rd_en;
+stat_debug(25) <= fifo_rx_wr_en;
+stat_debug(26) <= fifo_rx_reset;
+stat_debug(27) <= fifo_rx_empty;
+stat_debug(28) <= fifo_rx_full;
+stat_debug(29) <= last_rx(8);
+stat_debug(30) <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42) <= clk_sys;
+stat_debug(43) <= clk_sys;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+
+end architecture;
\ No newline at end of file
<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.0" title="soda_client" device="LFE3-150EA-8FN672C" default_implementation="soda_client">
+<BaliProject version="3.2" title="soda_client" device="LFE3-150EA-8FN672C" default_implementation="soda_client">
<Options>
<Option name="HDL type" value="VHDL"/>
</Options>
<Implementation title="soda_client" dir="soda_client" description="soda_client" synthesis="synplify" default_strategy="Strategy1">
- <Options top="trb3_periph_sodaclient"/>
+ <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
<Source name="code/version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Options/>
</Source>
<Source name="code/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
- <Options/>
+ <Options top_module="trb3_periph_sodaclient"/>
</Source>
<Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
<Options/>
<Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
- <Source name="soda_client_probe3.rvl" type="Reveal" type_short="Reveal">
+ <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="trb3_soda_client.xcf" type="Programming Project File" type_short="Programming">
rvl_alias "rx_full_clk" "rx_full_clk";
-RVL_ALIAS "clk_soda_i" "clk_soda_i";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
+BLOCK JTAGPATHS ;
#################################################################
# Basic Settings
#################################################################
# SYSCONFIG MCCLK_FREQ = 2.5;
# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
#################################################################
# Clock I/O
#################################################################
-#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
+#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
+#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
+DEFINE PORT GROUP "CLK_group" "*CLK*" ;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
#################################################################
-# Trigger I/O
-#################################################################
-#Trigger from fan-out
-#LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-#LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
-#IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
-#################################################################
# To central FPGA
#################################################################
#LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
DEFINE PORT GROUP "SFP_group" "SFP*" ;
IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
#################################################################
LOCATE COMP "LED_YELLOW" SITE "A16" ;
DEFINE PORT GROUP "LED_group" "LED*" ;
IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
-# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#################################################################
-# Reset Nets
-#################################################################
-#GSR_NET NET "GSR_N";
#################################################################
# Locate Serdes and media interfaces
#################################################################
#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE; # Uplink is now fiber !
-#REGION "SPI_REGION" "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; No longer present in copper
-#LOCATE UGROUP "THE_SYNC_LINK/media_uplink_group" REGION "UPLINK_REGION" ;
+
MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_raw_internal_c" ;
-USE PRIMARY NET "clk_sys_internal_c" ;
-USE PRIMARY NET "clk_soda_i" ;
MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+
+## IOBUF ALLPORTS ;
+USE PRIMARY NET "clk_200_osc" ;
+USE PRIMARY NET "clk_100_osc" ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+FREQUENCY NET "THE_SYNC_LINK/rx_full_clk" 200.000000 MHz ;
+FREQUENCY NET "THE_SYNC_LINK/rx_half_clk" 100.000000 MHz ;
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-12-03">
+ <IP Version="1_5_062609"/>
+ <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2064047666" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Setting>
+ <Clock SampleClk="rx_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
+ <Capture Mode="0" MinSamplesPerTrig="8"/>
+ <Event CntEnable="0" MaxEventCnt="8"/>
+ <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
+ </Setting>
+ <Dataset Name="Base">
+ <Trace>
+ <Sig Type="SIG" Name="the_sync_link/got_link_ready_i"/>
+ <Sig Type="SIG" Name="the_sync_link/link_phase_out"/>
+ <Bus Name="the_sync_link/rx_data">
+ <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/rx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
+ <Bus Name="the_sync_link/rx_dlm_word">
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
+ </Bus>
+ <Bus Name="the_sync_link/tx_data">
+ <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/tx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
+ <Bus Name="the_sync_link/tx_dlm_word">
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/rx_allow_q"/>
+ <Bus Name="sfp_los">
+ <Sig Type="SIG" Name="sfp_los:1"/>
+ <Sig Type="SIG" Name="sfp_los:2"/>
+ <Sig Type="SIG" Name="sfp_los:3"/>
+ <Sig Type="SIG" Name="sfp_los:4"/>
+ <Sig Type="SIG" Name="sfp_los:5"/>
+ <Sig Type="SIG" Name="sfp_los:6"/>
+ </Bus>
+ <Bus Name="the_sync_link/wa_position_rx">
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:0"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:1"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:2"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:3"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:4"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:5"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:6"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:7"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:8"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:9"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:10"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:11"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:12"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:13"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:14"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position_rx:15"/>
+ </Bus>
+ <Sig Type="SIG" Name="clk_100_osc"/>
+ <Sig Type="SIG" Name="rx_half_clk"/>
+ </Trace>
+ <Trigger>
+ <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_client/start_of_superburst_s,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/soda_cmd_valid_s,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/watchdog_trigger,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="general_reset_i,"/>
+ <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
+ </Trigger>
+ </Dataset>
+ </Core>
+</Project>
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
-<ispXCF version="3.0.0">
+<ispXCF version="3.3.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <Operation>Bypass</Operation>
+ <Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
- <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
</Option>
</Device>
<Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141015.bit</File>
- <FileTime>10/15/14 15:08:51</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141204.bit</File>
+ <FileTime>12/04/14 15:43:18</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
<Usercode>0x00000000</Usercode>
- <AccessMode>JTAG</AccessMode>
</Option>
</Device>
<Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <Operation>Bypass</Operation>
+ <Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
</Option>
</Device>
<Device>
- <SelectedProg value="FALSE"/>
+ <SelectedProg value="TRUE"/>
<Pos>4</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <Operation>Bypass</Operation>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141204.bit</File>
+ <FileTime>12/04/14 15:43:18</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
+ <Usercode>0x00000000</Usercode>
</Option>
</Device>
<Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141015.bit</File>
- <FileTime>10/15/14 15:08:51</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
+ <File>/local/lemmens/lattice/soda/trb3_periphEP_soda_quad_source_20141203.bit</File>
+ <FileTime>12/03/14 10:10:40</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
<Usercode>0x00000000</Usercode>
- <AccessMode>JTAG</AccessMode>
</Option>
</Device>
<Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1.jed</File>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
<FileTime>04/10/13 09:35:41</FileTime>
- <JedecChecksum>0x1C8C</JedecChecksum>
+ <JedecChecksum>0x1C57</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
<Usercode>0xFFFFFFFF</Usercode>
- <AccessMode>JTAG</AccessMode>
</Option>
</Device>
<Device>
- <SelectedProg value="TRUE"/>
+ <SelectedProg value="FALSE"/>
<Pos>7</Pos>
<Vendor>Lattice</Vendor>
<Family>ispCLOCK</Family>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <Operation>Bypass</Operation>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM2.jed</File>
+ <FileTime>04/10/13 09:35:41</FileTime>
+ <JedecChecksum>0x18FB</JedecChecksum>
+ <Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
+ <Usercode>0xFFFFFFFF</Usercode>
</Option>
</Device>
</Chain>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<JTAGPinSetting>
- TRST HIGH;
- ISPEN HIGH;
+ TRST ABSENT;
+ ISPEN ABSENT;
</JTAGPinSetting>
- <TRSTConnect value="TRUE"/>
- <ISPENConnect value="TRUE"/>
</CableOptions>
</ispXCF>
jspc29 / soda.git / commitdiff