Fixing the hadesstart to compile again with updated TDC

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index 994c690e8c3b32121425f63225912ddff2094699..2a4fc8a30f795c682e175a911109b98bdebecbd0 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -441,6 +441,45 @@ package trb3_components is
       AlmostEmpty : out std_logic);
   end component FIFO_36x128_OutReg;
 
+  component FIFO_36x64_OutReg is
+    port (
+      Data        : in  std_logic_vector(35 downto 0);
+      Clock       : in  std_logic;
+      WrEn        : in  std_logic;
+      RdEn        : in  std_logic;
+      Reset       : in  std_logic;
+      Q           : out std_logic_vector(35 downto 0);
+      Empty       : out std_logic;
+      Full        : out std_logic;
+      AlmostEmpty : out std_logic);
+  end component;
+  
+  component FIFO_36x32_OutReg is
+    port (
+      Data        : in  std_logic_vector(35 downto 0);
+      Clock       : in  std_logic;
+      WrEn        : in  std_logic;
+      RdEn        : in  std_logic;
+      Reset       : in  std_logic;
+      Q           : out std_logic_vector(35 downto 0);
+      Empty       : out std_logic;
+      Full        : out std_logic;
+      AlmostEmpty : out std_logic);
+  end component;
+  
+  component FIFO_36x16_OutReg is
+    port (
+      Data        : in  std_logic_vector(35 downto 0);
+      Clock       : in  std_logic;
+      WrEn        : in  std_logic;
+      RdEn        : in  std_logic;
+      Reset       : in  std_logic;
+      Q           : out std_logic_vector(35 downto 0);
+      Empty       : out std_logic;
+      Full        : out std_logic;
+      AlmostEmpty : out std_logic);
+  end component;  
+  
   component FIFO_DC_36x128_OutReg is
     port (
       Data       : in  std_logic_vector(35 downto 0);
@@ -486,6 +525,36 @@ package trb3_components is
       Full    : out std_logic);
   end component FIFO_36x128_OutReg_Counter;
 
+  component FIFO_DC_36x32_OutReg is
+    port (
+      Data       : in  std_logic_vector(35 downto 0);
+      WrClock    : in  std_logic;
+      RdClock    : in  std_logic;
+      WrEn       : in  std_logic;
+      RdEn       : in  std_logic;
+      Reset      : in  std_logic;
+      RPReset    : in  std_logic;
+      Q          : out std_logic_vector(35 downto 0);
+      Empty      : out std_logic;
+      Full       : out std_logic;
+      AlmostFull : out std_logic);
+  end component;
+  
+  component FIFO_DC_36x16_OutReg is
+    port (
+      Data       : in  std_logic_vector(35 downto 0);
+      WrClock    : in  std_logic;
+      RdClock    : in  std_logic;
+      WrEn       : in  std_logic;
+      RdEn       : in  std_logic;
+      Reset      : in  std_logic;
+      RPReset    : in  std_logic;
+      Q          : out std_logic_vector(35 downto 0);
+      Empty      : out std_logic;
+      Full       : out std_logic;
+      AlmostFull : out std_logic);
+  end component;  
+  
   --component FIFO_24x2_OutReg
   --  port (
   --    Data    : in  std_logic_vector(23 downto 0);

diff --git a/hadesstart/compile_periph_frankfurt.pl b/hadesstart/compile_periph_frankfurt.pl
index dc92350d8afd7cfcbb916139f8102510f071edaa..ed798b910e44d4248ce64dd662f2ce23beb1e6bd 100755 (executable)
--- a/hadesstart/compile_periph_frankfurt.pl
+++ b/hadesstart/compile_periph_frankfurt.pl
@@ -36,10 +36,14 @@ my $SPEEDGRADE="8";
 
 
 #create full lpf file
-system("cp ../base/trb3_periph_ada.lpf workdir/$TOPNAME.lpf");
-system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf");
-system("cat currentRelease/tdc_constraints_4.lpf >> workdir/$TOPNAME.lpf");
-
+# system("cp ../base/trb3_periph_ada.lpf workdir/$TOPNAME.lpf");
+# system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf");
+# system("cat currentRelease/tdc_constraints_4.lpf >> workdir/$TOPNAME.lpf");
+system("cp ../base/trb3_periph_ada.lpf workdir/trb3_periph.lpf");
+system("cat currentRelease/trbnet_constraints.lpf >> workdir/trb3_periph.lpf");
+system("cat currentRelease/tdc_constraints_64.lpf >> workdir/trb3_periph.lpf");
+system("cat currentRelease/unimportant_lines_constraints.lpf >> workdir/trb3_periph.lpf");
+system("cat unimportant_lines_constraints.lpf >> workdir/trb3_periph.lpf");
 
 #set -e
 #set -o errexit

diff --git a/hadesstart/config.vhd b/hadesstart/config.vhd
index 07a1454f0ccd46e7514c9dbc2115032db2a06564..b3b808b42106ce996442d46cefe3a9ceda8faff3 100644 (file)
--- a/hadesstart/config.vhd
+++ b/hadesstart/config.vhd
@@ -11,9 +11,11 @@ package config is
 ------------------------------------------------------------------------------
 
 --TDC settings
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 33;
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 2;
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
   constant USE_DOUBLE_EDGE         : integer               := c_YES;
+--Define ringbuffer size for TDC channels: 32-64-128
+  constant RING_BUFFER_SIZE : integer range 32 to 128 := 64;
 
 --use only every fourth input as in HPTDC high precision mode    
   constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES;
@@ -30,9 +32,6 @@ package config is
 --number of real inputs to the FPGA    
   constant PHYSICAL_INPUTS : integer := 16;
 
---Define ringbuffer size for TDC channels: 32-64-128
-  constant RING_BUFFER_SIZE : integer range 32 to 128 := 32;
-
 --Run wih 125 MHz instead of 100 MHz     
   constant USE_125_MHZ : integer := c_NO;  --not implemented yet!  
 

diff --git a/hadesstart/trb3_periph_hadesstart.prj b/hadesstart/trb3_periph_hadesstart.prj
index 1e44246a559a28efa5677ff5e594704ecffd0c1c..a99e7afc0de2374be5fec51b592fd43877c2be1c 100644 (file)
--- a/hadesstart/trb3_periph_hadesstart.prj
+++ b/hadesstart/trb3_periph_hadesstart.prj
@@ -52,7 +52,7 @@ impl -active "workdir"
 #add_file options
 
 add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "currectRelease/tdc_version.vhd"
+add_file -vhdl -lib work "currentRelease/tdc_version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
@@ -127,7 +127,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dual
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
 
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
@@ -166,8 +166,13 @@ add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
 add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
 add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_36x16_OutReg.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x16_OutReg.vhd"
 #add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd"
 #add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd"