-- File : Channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-08-28
--- Last update: 2014-04-24
+-- Last update: 2014-04-30
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
signal epoch_capture_time : std_logic_vector(10 downto 0);
signal epoch_value : std_logic_vector(35 downto 0);
- -- fifo
- signal fifo_data_out_i : std_logic_vector(35 downto 0);
- signal fifo_data_in_i : std_logic_vector(35 downto 0);
- signal fifo_empty_i : std_logic;
- signal fifo_full_i : std_logic;
- signal fifo_almost_full_sync : std_logic;
- signal fifo_almost_full_i : std_logic := '0';
- signal fifo_almost_full_flag : std_logic := '0';
- signal fifo_wr_en_i : std_logic;
- signal fifo_rd_en_i : std_logic;
- signal fifo_rd_data_i : std_logic;
- signal fifo_data_i : std_logic_vector(35 downto 0);
- signal fifo_data_valid_i : std_logic;
+ -- ring bugger
+ signal ringBuffer_data_out_i : std_logic_vector(35 downto 0);
+ signal ringBuffer_data_in_i : std_logic_vector(35 downto 0);
+ signal ringBuffer_empty_i : std_logic;
+ signal ringBuffer_full_i : std_logic;
+ signal ringBuffer_almost_full_sync : std_logic;
+ signal ringBuffer_almost_full_i : std_logic := '0';
+ signal ringBuffer_almost_full_flag : std_logic := '0';
+ signal ringBuffer_wr_en_i : std_logic;
+ signal ringBuffer_rd_en_i : std_logic;
+ signal ringBuffer_rd_data_i : std_logic;
+ signal fifo_data_i : std_logic_vector(35 downto 0);
+ signal fifo_data_valid_i : std_logic;
-- fsm
type FSM_WR is (WRITE_EPOCH, WRITE_DATA, WRITE_STOP_A, WRITE_STOP_B, WRITE_STOP_C, WRITE_STOP_D, WAIT_FOR_HIT,
RingBuffer_128 : if USE_64_FIFO = c_NO generate
FIFO : FIFO_DC_36x128_OutReg
port map (
- Data => fifo_data_in_i,
+ Data => ringBuffer_data_in_i,
WrClock => CLK_200,
RdClock => CLK_100,
- WrEn => fifo_wr_en_i,
- RdEn => fifo_rd_en_i,
+ WrEn => ringBuffer_wr_en_i,
+ RdEn => ringBuffer_rd_en_i,
Reset => RESET_100,
- RPReset => RESET_200,
- Q => fifo_data_out_i,
- Empty => fifo_empty_i,
- Full => fifo_full_i,
- AlmostFull => fifo_almost_full_i);
+ RPReset => RESET_100,
+ Q => ringBuffer_data_out_i,
+ Empty => ringBuffer_empty_i,
+ Full => ringBuffer_full_i,
+ AlmostFull => ringBuffer_almost_full_i);
end generate RingBuffer_128;
RingBuffer_64 : if USE_64_FIFO = c_YES generate
FIFO : FIFO_DC_36x64_OutReg
port map (
- Data => fifo_data_in_i,
+ Data => ringBuffer_data_in_i,
WrClock => CLK_200,
RdClock => CLK_100,
- WrEn => fifo_wr_en_i,
- RdEn => fifo_rd_en_i,
+ WrEn => ringBuffer_wr_en_i,
+ RdEn => ringBuffer_rd_en_i,
Reset => RESET_100,
- RPReset => RESET_200,
- Q => fifo_data_out_i,
- Empty => fifo_empty_i,
- Full => fifo_full_i,
- AlmostFull => fifo_almost_full_i);
+ RPReset => RESET_100,
+ Q => ringBuffer_data_out_i,
+ Empty => ringBuffer_empty_i,
+ Full => ringBuffer_full_i,
+ AlmostFull => ringBuffer_almost_full_i);
end generate RingBuffer_64;
- fifo_almost_full_sync <= fifo_almost_full_i when rising_edge(CLK_100);
- fifo_rd_en_i <= fifo_rd_data_i or fifo_almost_full_sync when rising_edge(CLK_100);
+ ringBuffer_almost_full_sync <= ringBuffer_almost_full_i when rising_edge(CLK_100);
+ ringBuffer_rd_en_i <= ringBuffer_rd_data_i or ringBuffer_almost_full_sync when rising_edge(CLK_100);
FifoAlmostmptyFlag : process (CLK_100)
begin
if rising_edge(CLK_100) then
- if FSM_RD_STATE = READOUT_DATA_C then
- fifo_almost_full_flag <= '0';
- elsif fifo_almost_full_sync = '1' then
- fifo_almost_full_flag <= '1';
+ if RESET_100 = '1' then
+ ringBuffer_almost_full_flag <= '0';
+ elsif FSM_RD_STATE = READOUT_DATA_C then
+ ringBuffer_almost_full_flag <= '0';
+ elsif ringBuffer_almost_full_sync = '1' then
+ ringBuffer_almost_full_flag <= '1';
end if;
end if;
end process FifoAlmostmptyFlag;
-- Readout fsm
FSM_CLK : process (CLK_200)
begin
- if rising_edge(CLK_200) then
+ if RESET_200 = '1' then
+ FSM_WR_CURRENT <= WRITE_EPOCH;
+ elsif rising_edge(CLK_200) then
FSM_WR_CURRENT <= FSM_WR_NEXT;
write_epoch_i <= write_epoch_fsm;
write_data_i <= write_data_fsm;
TriggerWindowFlag : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if TRIGGER_WIN_END_TDC = '1' then
+ if RESET_200 = '1' then
+ trig_win_end_tdc_flag_i <= '0';
+ elsif TRIGGER_WIN_END_TDC = '1' then
trig_win_end_tdc_flag_i <= '1';
elsif FSM_WR_CURRENT = WRITE_STOP_D then
trig_win_end_tdc_flag_i <= '0';
begin
if rising_edge(CLK_200) then
if write_epoch_i = '1' and EPOCH_WRITE_EN_IN = '1' then
- fifo_data_in_i(35 downto 32) <= x"1";
- fifo_data_in_i(31 downto 29) <= "011";
- fifo_data_in_i(28) <= '0';
- fifo_data_in_i(27 downto 0) <= epoch_cntr;
- fifo_wr_en_i <= '1';
+ ringBuffer_data_in_i(35 downto 32) <= x"1";
+ ringBuffer_data_in_i(31 downto 29) <= "011";
+ ringBuffer_data_in_i(28) <= '0';
+ ringBuffer_data_in_i(27 downto 0) <= epoch_cntr;
+ ringBuffer_wr_en_i <= '1';
elsif write_data_i = '1' then
- fifo_data_in_i(35 downto 32) <= x"1";
- fifo_data_in_i(31) <= '1'; -- data marker
- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits
- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number
- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder
- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge
- fifo_data_in_i(10 downto 0) <= time_stamp_6reg; -- hit time stamp
- fifo_wr_en_i <= '1';
+ ringBuffer_data_in_i(35 downto 32) <= x"1";
+ ringBuffer_data_in_i(31) <= '1'; -- data marker
+ ringBuffer_data_in_i(30 downto 29) <= "00"; -- reserved bits
+ ringBuffer_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number
+ ringBuffer_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder
+ ringBuffer_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge
+ ringBuffer_data_in_i(10 downto 0) <= time_stamp_6reg; -- hit time stamp
+ ringBuffer_wr_en_i <= '1';
elsif write_stop_a_i = '1' then
- fifo_data_in_i(35 downto 32) <= x"f";
- fifo_data_in_i(31 downto 0) <= (others => '0');
- fifo_wr_en_i <= '1';
+ ringBuffer_data_in_i(35 downto 32) <= x"f";
+ ringBuffer_data_in_i(31 downto 0) <= (others => '0');
+ ringBuffer_wr_en_i <= '1';
elsif write_stop_b_i = '1' then
- fifo_data_in_i(35 downto 32) <= x"0";
- fifo_data_in_i(31 downto 0) <= (others => '0');
- fifo_wr_en_i <= '1';
+ ringBuffer_data_in_i(35 downto 32) <= x"0";
+ ringBuffer_data_in_i(31 downto 0) <= (others => '0');
+ ringBuffer_wr_en_i <= '1';
else
- fifo_data_in_i(35 downto 32) <= x"e";
- fifo_data_in_i(31 downto 0) <= (others => '0');
- fifo_wr_en_i <= '0';
+ ringBuffer_data_in_i(35 downto 32) <= x"e";
+ ringBuffer_data_in_i(31 downto 0) <= (others => '0');
+ ringBuffer_wr_en_i <= '0';
end if;
end if;
end process FifoWriteSignal;
- FIFO_WRITE_OUT <= fifo_wr_en_i;
+ FIFO_WRITE_OUT <= ringBuffer_wr_en_i;
ENCODER_FINISHED_OUT <= encoder_finished_i;
-------------------------------------------------------------------------------
if TRIGGER_WIN_END_RDO = '1' then
FSM_RD_STATE <= READOUT_DATA_A;
-- if the data readout is triggered by full fifo
- elsif fifo_almost_full_flag = '1' then
+ elsif ringBuffer_almost_full_flag = '1' then
FSM_RD_STATE <= FLUSH_A;
else
FSM_RD_STATE <= IDLE;
--
when READOUT_DATA_C =>
-- normal data readout until the end of the readout request
- if fifo_data_out_i(35 downto 32) = x"f" then
+ if ringBuffer_data_out_i(35 downto 32) = x"f" then
FSM_RD_STATE <= IDLE;
else
FSM_RD_STATE <= READOUT_DATA_C;
-- Determine the output based only on the current state and the input (do not wait for a clock
-- edge).
- FSM_DATA_OUTPUT : process (FSM_RD_STATE, TRIGGER_WIN_END_RDO, fifo_data_out_i, epoch_value)
+ FSM_DATA_OUTPUT : process (FSM_RD_STATE, TRIGGER_WIN_END_RDO, ringBuffer_data_out_i, epoch_value)
begin
trigger_win_end_rdo_flag_i <= trigger_win_end_rdo_flag_i;
epoch_value <= epoch_value;
case FSM_RD_STATE is
when IDLE =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '0';
- fsm_rd_debug_i <= x"1";
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '0';
+ fsm_rd_debug_i <= x"1";
when FLUSH_A =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '0';
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '0';
if TRIGGER_WIN_END_RDO = '1' then
trigger_win_end_rdo_flag_i <= '1';
end if;
fsm_rd_debug_i <= x"2";
when FLUSH_B =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '0';
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '0';
if TRIGGER_WIN_END_RDO = '1' then
trigger_win_end_rdo_flag_i <= '1';
end if;
fsm_rd_debug_i <= x"3";
when FLUSH_C =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '0';
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '0';
if TRIGGER_WIN_END_RDO = '1' then
trigger_win_end_rdo_flag_i <= '1';
end if;
fsm_rd_debug_i <= x"4";
when FLUSH_D =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '0';
- if fifo_data_out_i(31 downto 29) = "011" then
- epoch_value <= fifo_data_out_i;
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '0';
+ if ringBuffer_data_out_i(31 downto 29) = "011" then
+ epoch_value <= ringBuffer_data_out_i;
end if;
fsm_rd_debug_i <= x"5";
when READOUT_EPOCH =>
- fifo_data_i <= epoch_value;
- fifo_data_valid_i <= '1';
- fifo_rd_data_i <= '1';
- fsm_rd_debug_i <= x"6";
+ fifo_data_i <= epoch_value;
+ fifo_data_valid_i <= '1';
+ ringBuffer_rd_data_i <= '1';
+ fsm_rd_debug_i <= x"6";
when READOUT_DATA_A =>
fifo_data_i <= (others => '0');
fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '1';
+ ringBuffer_rd_data_i <= '1';
trigger_win_end_rdo_flag_i <= '0';
fsm_rd_debug_i <= x"7";
when READOUT_DATA_B =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '1';
- fsm_rd_debug_i <= x"8";
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '1';
+ fsm_rd_debug_i <= x"8";
when READOUT_DATA_C =>
- fifo_data_i <= fifo_data_out_i;
- if fifo_data_out_i(35 downto 32) = x"0" then
+ fifo_data_i <= ringBuffer_data_out_i;
+ if ringBuffer_data_out_i(35 downto 32) = x"0" then
fifo_data_valid_i <= '0';
else
fifo_data_valid_i <= '1';
end if;
- fifo_rd_data_i <= '1';
- fsm_rd_debug_i <= x"9";
+ ringBuffer_rd_data_i <= '1';
+ fsm_rd_debug_i <= x"9";
when others =>
- fifo_data_i <= (others => '0');
- fifo_data_valid_i <= '0';
- fifo_rd_data_i <= '0';
- fsm_rd_debug_i <= x"0";
+ fifo_data_i <= (others => '0');
+ fifo_data_valid_i <= '0';
+ ringBuffer_rd_data_i <= '0';
+ fsm_rd_debug_i <= x"0";
end case;
end process FSM_DATA_OUTPUT;
RegisterOutputs : process (CLK_100)
begin
if rising_edge(CLK_100) then
- FIFO_EMPTY_OUT <= fifo_empty_i;
+ FIFO_EMPTY_OUT <= ringBuffer_empty_i;
end if;
end process RegisterOutputs;
- FIFO_FULL_OUT <= fifo_full_i when rising_edge(CLK_200);
- FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i when rising_edge(CLK_200);
+ FIFO_FULL_OUT <= ringBuffer_full_i when rising_edge(CLK_200);
+ FIFO_ALMOST_FULL_OUT <= ringBuffer_almost_full_i when rising_edge(CLK_200);
-------------------------------------------------------------------------------
-- DEBUG
-------------------------------------------------------------------------------
- --CHANNEL_200_DEBUG(7 downto 0) <= fifo_data_in_i(35 downto 28);
+ --CHANNEL_200_DEBUG(7 downto 0) <= ringBuffer_data_in_i(35 downto 28);
--CHANNEL_200_DEBUG(15 downto 8) <= fifo_data_i(35 downto 28);
- --CHANNEL_200_DEBUG(16) <= fifo_wr_en_i;
+ --CHANNEL_200_DEBUG(16) <= ringBuffer_wr_en_i;
--CHANNEL_200_DEBUG(17) <= fifo_data_valid_i;
- --CHANNEL_200_DEBUG(18) <= fifo_rd_en_i;
+ --CHANNEL_200_DEBUG(18) <= ringBuffer_rd_en_i;
--CHANNEL_200_DEBUG(23 downto 19) <= (others => '0');
- --CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i;
- --CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i;
+ CHANNEL_200_DEBUG(23 downto 0) <= (others => '0');
+ CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i;
+ CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i;
- ch_fifo_counter_100 <= ch_fifo_counter when rising_edge(CLK_100);
- CHANNEL_200_DEBUG(15 downto 0) <= std_logic_vector(ch_fifo_counter_100);
+ --ch_fifo_counter_100 <= ch_fifo_counter when rising_edge(CLK_100);
+ --CHANNEL_200_DEBUG(15 downto 0) <= std_logic_vector(ch_fifo_counter_100);
gen_DEBUG : if DEBUG = c_YES generate
debugChannelDataCount : process (CLK_200)
if rising_edge(CLK_200) then
if RESET_COUNTERS = '1' then
ch_fifo_counter <= (others => '0');
- elsif fifo_wr_en_i = '1' then
- if fifo_data_in_i(35 downto 31) = "00011" then -- it is a data word
+ elsif ringBuffer_wr_en_i = '1' then
+ if ringBuffer_data_in_i(35 downto 31) = "00011" then -- it is a data word
ch_fifo_counter <= ch_fifo_counter + to_unsigned(1, 16);
end if;
end if;
-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2014-04-22
+-- Last update: 2014-04-29
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
signal wr_finished_fsm : std_logic;
signal trig_release_fsm : std_logic;
signal wr_header_fsm : std_logic;
+ signal wr_trailer_fsm : std_logic;
signal wr_ch_data_fsm : std_logic;
signal wr_status_fsm : std_logic;
signal wrong_readout_fsm : std_logic;
+ signal wrong_reference_fsm : std_logic;
signal wr_number_fsm : unsigned(7 downto 0);
signal wr_number : unsigned(7 downto 0);
signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0;
signal wr_ch_data_i : std_logic;
signal wr_ch_data_reg : std_logic;
signal wr_status : std_logic;
--- signal wr_trailer : std_logic;
+ signal wr_trailer : std_logic;
signal wr_info : std_logic;
signal wr_time : std_logic;
signal wr_epoch : std_logic;
signal readout_time_up : std_logic;
signal wait_time_up : std_logic;
signal wrong_readout_up : std_logic;
+ signal wrong_reference : std_logic;
signal finished_i : std_logic;
-- debug
signal header_error_bits : std_logic_vector(15 downto 0);
DefineTriggerTime : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if TRIGGER_TDC_IN = '1' then
+ if RESET_200 = '1' then
+ trig_time_i <= (others => '0');
+ elsif TRIGGER_TDC_IN = '1' then
trig_time_i <= epoch_cntr_12reg & coarse_cntr_12reg;
end if;
end if;
RD_CURRENT <= RD_NEXT;
rd_en <= rd_en_fsm;
wr_header <= wr_header_fsm;
+ wr_trailer <= wr_trailer_fsm;
wr_status <= wr_status_fsm;
data_finished <= data_finished_fsm;
trig_release_reg <= trig_release_fsm;
buf_delay_i <= buf_delay_fsm;
wrong_readout_up <= wrong_readout_fsm;
+ wrong_reference <= wrong_reference_fsm;
idle_time_up <= idle_fsm;
readout_time_up <= readout_fsm;
wait_time_up <= wait_fsm;
TRIG_WIN_END_RDO_IN, buf_delay_i, CH_EMPTY_IN, CLK_100)
begin
- rd_en_fsm <= (others => '0');
- wr_header_fsm <= '0';
- data_finished_fsm <= '0';
- trig_release_fsm <= '0';
- wrong_readout_fsm <= '0';
- idle_fsm <= '0';
- readout_fsm <= '0';
- wait_fsm <= '0';
- wr_status_fsm <= '0';
- buf_delay_fsm <= 0;
- fifo_nr_rd_fsm <= fifo_nr_rd;
- rd_fsm_debug_fsm <= x"0";
- RD_NEXT <= RD_CURRENT;
+ rd_en_fsm <= (others => '0');
+ wr_header_fsm <= '0';
+ wr_trailer_fsm <= '0';
+ data_finished_fsm <= '0';
+ trig_release_fsm <= '0';
+ wrong_readout_fsm <= '0';
+ wrong_reference_fsm <= '0';
+ idle_fsm <= '0';
+ readout_fsm <= '0';
+ wait_fsm <= '0';
+ wr_status_fsm <= '0';
+ buf_delay_fsm <= 0;
+ fifo_nr_rd_fsm <= fifo_nr_rd;
+ rd_fsm_debug_fsm <= x"0";
+ RD_NEXT <= RD_CURRENT;
case (RD_CURRENT) is
when IDLE =>
when WAIT_FOR_LVL1_TRIG_A => -- wait for trigger data valid
if TRG_DATA_VALID_IN = '1' then
RD_NEXT <= WAIT_FOR_LVL1_TRIG_B;
- --elsif TMGTRG_TIMEOUT_IN = '1' then
- -- RD_NEXT <= IDLE;
+ elsif TMGTRG_TIMEOUT_IN = '1' then
+ RD_NEXT <= SEND_TRIG_RELEASE_A;
+ data_finished_fsm <= '1';
end if;
wait_fsm <= '1';
rd_fsm_debug_fsm <= x"6";
when WAIT_FOR_LVL1_TRIG_B =>
+ --if MULTI_TMG_TRG_IN = '1' or SPIKE_DETECTED_IN = '1' then
+ -- wrong_reference_fsm <= '1';
+ -- wr_trailer_fsm <= '1';
+ --end if;
RD_NEXT <= WAIT_FOR_LVL1_TRIG_C;
wait_fsm <= '1';
rd_fsm_debug_fsm <= x"7";
when WAIT_FOR_LVL1_TRIG_C =>
if SPURIOUS_TRG_IN = '1' then
wrong_readout_fsm <= '1';
+-- wr_trailer_fsm <= '1';
end if;
RD_NEXT <= SEND_TRIG_RELEASE_A;
wait_fsm <= '1';
SRB_DATA_OUT : out std_logic_vector(31 downto 0);
SRB_DATAREADY_OUT : out std_logic;
SRB_UNKNOWN_ADDR_OUT : out std_logic;
+ CDB_READ_EN_IN : in std_logic;
+ CDB_WRITE_EN_IN : in std_logic;
+ CDB_ADDR_IN : in std_logic_vector(6 downto 0);
+ CDB_DATA_OUT : out std_logic_vector(31 downto 0);
+ CDB_DATAREADY_OUT : out std_logic;
+ CDB_UNKNOWN_ADDR_OUT : out std_logic;
ESB_READ_EN_IN : in std_logic;
ESB_WRITE_EN_IN : in std_logic;
ESB_ADDR_IN : in std_logic_vector(6 downto 0);
signal reset_tdc : std_logic;
signal reset_tdc_i : std_logic;
-- Coarse counters
- signal coarse_cntr : std_logic_vector_array_11(0 to 4);
+ signal coarse_cntr : std_logic_vector_array_11(0 to 16);
signal coarse_cntr_reset : std_logic;
- signal coarse_cntr_reset_r : std_logic_vector(4 downto 0);
+ signal coarse_cntr_reset_r : std_logic_vector(16 downto 0);
-- Slow control
signal logic_anal_control : std_logic_vector(3 downto 0);
signal debug_mode_en_i : std_logic;
signal trig_win_end_rdo : std_logic;
signal trig_win_end_tdc : std_logic;
signal trig_win_end_tdc_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+ signal valid_trigger_rdo : std_logic;
+ signal valid_trigger_tdc : std_logic;
-- Debug signals
signal ref_debug_i : std_logic_vector(31 downto 0);
reset_counters_i <= CONTROL_REG_IN(8) or reset_tdc when rising_edge(CLK_TDC);
run_mode_i <= CONTROL_REG_IN(12);
run_mode_200 <= run_mode_i when rising_edge(CLK_TDC);
- reset_coarse_cntr_i <= CONTROL_REG_IN(13);
+ reset_coarse_cntr_i <= CONTROL_REG_IN(13) when rising_edge(CLK_TDC);
reset_coarse_cntr_200 <= reset_coarse_cntr_i when rising_edge(CLK_TDC);
calibration_freq_select <= unsigned(CONTROL_REG_IN(31 downto 28));
CHANNEL_ID => 0,
DEBUG => DEBUG,
SIMULATION => SIMULATION,
- REFERENCE => c_YES)
+ REFERENCE => c_NO)
port map (
RESET_200 => reset_tdc,
RESET_100 => reset_rdo,
TRIGGER_WIN_END_TDC => trig_win_end_tdc_i(i),
TRIGGER_WIN_END_RDO => trig_win_end_rdo,
EPOCH_COUNTER_IN => epoch_cntr,
- COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(16)))),
+ COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(4)))),
READ_EN_IN => rd_en_i(i),
FIFO_DATA_OUT => ch_data_i(i),
FIFO_DATA_VALID_OUT => ch_data_valid_i(i),
end generate GEN_Channels;
ch_data_i(CHANNEL_NUMBER) <= (others => '1');
- -- Trigger handler
+ -- Valid Trigger Sync
+ ValidTriggerPulseSync: entity work.pulse_sync
+ port map (
+ CLK_A_IN => CLK_READOUT,
+ RESET_A_IN => reset_rdo,
+ PULSE_A_IN => valid_trigger_rdo,
+ CLK_B_IN => CLK_TDC,
+ RESET_B_IN => reset_tdc,
+ PULSE_B_OUT => valid_trigger_tdc);
+ valid_trigger_rdo <= VALID_NOTIMING_TRG_IN or VALID_TIMING_TRG_IN;
+
+ -- Timing Trigger handler
TheTriggerHandler : TriggerHandler
generic map (
TRIGGER_NUM => 1,
TRIGGER_WIN_POST_IN => unsigned(TRG_WIN_POST),
TRIGGER_WIN_END_RDO_OUT => trig_win_end_rdo,
TRIGGER_WIN_END_TDC_OUT => trig_win_end_tdc);
--- trig_in_i <= REFERENCE_TIME or VALID_NOTIMING_TRG_IN;
- trig_in_i <= VALID_TIMING_TRG_IN or VALID_NOTIMING_TRG_IN;
+ trig_in_i <= REFERENCE_TIME or VALID_NOTIMING_TRG_IN;
GenTriggerWindowEnd: for i in 0 to CHANNEL_NUMBER-1 generate
trig_win_end_tdc_i(i) <= trig_win_end_tdc when rising_edge(CLK_TDC);
end generate GenTriggerWindowEnd;
DATA_FINISHED_OUT <= data_finished_i;
-- Coarse counter
- GenCoarseCounter : for i in 0 to 4 generate
+ GenCoarseCounter : for i in 0 to 16 generate
TheCoarseCounter : up_counter
generic map (
NUMBER_OF_BITS => 11)
coarse_cntr_reset <= trig_win_end_tdc_i(1);
elsif run_mode_edge_200 = '1' then
coarse_cntr_reset <= '1';
- elsif reset_coarse_cntr_flag = '1' and (VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1') then
+ elsif reset_coarse_cntr_flag = '1' and valid_trigger_tdc = '1' then --(VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1') then
coarse_cntr_reset <= '1';
else
coarse_cntr_reset <= '0';
end if;
if reset_coarse_cntr_edge_200 = '1' then
reset_coarse_cntr_flag <= '1';
- elsif VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1' then
+ elsif valid_trigger_tdc = '1' then
reset_coarse_cntr_flag <= '0';
end if;
end if;
SIGNAL_IN => reset_coarse_cntr_200,
PULSE_OUT => reset_coarse_cntr_edge_200);
- GenCoarseCounterReset : for i in 0 to 4 generate
+ GenCoarseCounterReset : for i in 0 to 16 generate
coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC);
end generate GenCoarseCounterReset;
DATAREADY_OUT => SRB_DATAREADY_OUT,
UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT);
--- status_registers_bus_i(21) <= ch_200_debug_i(0);
+ TheChannelDebugBus : BusHandler
+ generic map (
+ BUS_LENGTH => CHANNEL_NUMBER - 1)
+ port map (
+ RESET => reset_rdo,
+ CLK => CLK_READOUT,
+ DATA_IN => ch_200_debug_i,
+ READ_EN_IN => CDB_READ_EN_IN,
+ WRITE_EN_IN => CDB_WRITE_EN_IN,
+ ADDR_IN => CDB_ADDR_IN,
+ DATA_OUT => CDB_DATA_OUT,
+ DATAREADY_OUT => CDB_DATAREADY_OUT,
+ UNKNOWN_ADDR_OUT => CDB_UNKNOWN_ADDR_OUT);
+
--TheLostHitBus : BusHandler
-- generic map (
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