--attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group";
-component tsmac36 --tsmac35
+component tsmac35 --tsmac36 --tsmac35
port(
--------------- clock and reset port declarations ------------------
hclk : in std_logic;
signal mc_fc_h_ready, mc_fc_ready, mc_fc_wr_en : std_logic;
signal mc_ident, mc_size_left : std_logic_vector(15 downto 0);
+
begin
stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
-- gk 23.04.10
-LED_PACKET_SENT_OUT <= timeout_noticed; --pc_ready;
-LED_AN_DONE_N_OUT <= not link_ok; --not pcs_an_complete;
+LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready;
+LED_AN_DONE_N_OUT <= '0'; --not link_ok; --not pcs_an_complete;
fc_ihl_version <= x"45";
fc_tos <= x"10";
fc_ttl <= x"ff";
-
MAIN_CONTROL : trb_net16_gbe_main_control
port map(
CLK => CLK,
RESET => RESET,
MC_LINK_OK_OUT => link_ok,
- MC_RESET_LINK_IN => MR_RESTART_IN,
+ MC_RESET_LINK_IN => '0',
MC_IDLE_TOO_LONG_OUT => idle_too_long,
-- signals to/from receive controller
DEBUG_OUT => dbg_mc
);
- MAKE_RESET_OUT <= make_reset or idle_too_long;
+ MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
CLK => CLK,
RESET => RESET,
--- signal to/from main controller
--- MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
--- MC_DATA_IN => mc_data,
--- MC_WR_EN_IN => mc_wr_en,
--- MC_DATA_NOT_VALID_IN => tc_data_not_valid,
--- MC_FRAME_SIZE_IN => mc_frame_size,
--- MC_FRAME_TYPE_IN => mc_type,
--- MC_IP_PROTOCOL_IN => mc_ip_proto,
--- MC_IDENT_IN => mc_ident,
---
--- MC_DEST_MAC_IN => mc_dest_mac,
--- MC_DEST_IP_IN => mc_dest_ip,
--- MC_DEST_UDP_IN => mc_dest_udp,
--- MC_SRC_MAC_IN => mc_src_mac,
--- MC_SRC_IP_IN => mc_src_ip,
--- MC_SRC_UDP_IN => mc_src_udp,
---
--- MC_IP_SIZE_IN => mc_ip_size,
--- MC_UDP_SIZE_IN => mc_udp_size,
--- MC_FLAGS_OFFSET_IN => mc_flags,
---
--- MC_FC_H_READY_OUT => mc_fc_h_ready,
--- MC_FC_READY_OUT => mc_fc_ready,
--- MC_FC_WR_EN_IN => mc_fc_wr_en,
---
--- MC_BUSY_OUT => mc_busy,
--- MC_TRANSMIT_DONE_OUT => mc_transmit_done,
-
-- signal to/from main controller
TC_DATAREADY_IN => mc_transmit_ctrl,
TC_RD_EN_OUT => mc_wr_en,
end generate;
-
----- IP configurator: allows IP config to change for each event builder
---THE_IP_CONFIGURATOR: ip_configurator
---port map(
--- CLK => CLK,
--- RESET => RESET,
--- -- configuration interface
--- START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10
--- BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10
--- CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10
--- MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10
--- MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10
--- MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10
--- -- information for IP cores
--- DEST_MAC_OUT => ic_dest_mac,
--- DEST_IP_OUT => ic_dest_ip,
--- DEST_UDP_OUT => ic_dest_udp,
--- SRC_MAC_OUT => ic_src_mac,
--- SRC_IP_OUT => ic_src_ip,
--- SRC_UDP_OUT => ic_src_udp,
--- MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10
--- -- Debug
--- DEBUG_OUT => open
---);
---
----- gk 27.03.01
---MB_IP_CONFIG: slv_mac_memory
---port map(
--- CLK => CLK, -- clk_100,
--- RESET => RESET, --reset_i,
--- BUSY_IN => '0',
--- -- Slave bus
--- SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0),
--- SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read,
--- SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write,
--- SLV_BUSY_OUT => SLV_BUSY_OUT,
--- SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack,
--- SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr,
--- SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd,
--- -- I/O to the backend
--- MEM_CLK_IN => ip_cfg_mem_clk,
--- MEM_ADDR_IN => ip_cfg_mem_addr,
--- MEM_DATA_OUT => ip_cfg_mem_data,
--- -- Status lines
--- STAT => open
---);
-
--- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS
---THE_IPU_INTERFACE: trb_net16_ipu2gbe
---port map(
--- CLK => CLK,
--- RESET => RESET,
--- --Event information coming from CTS
--- CTS_NUMBER_IN => CTS_NUMBER_IN,
--- CTS_CODE_IN => CTS_CODE_IN,
--- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
--- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
--- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
--- --Information sent to CTS
--- --status data, equipped with DHDR
--- CTS_DATA_OUT => cts_data,
--- CTS_DATAREADY_OUT => cts_dataready,
--- CTS_READOUT_FINISHED_OUT => cts_readout_finished,
--- CTS_READ_IN => CTS_READ_IN,
--- CTS_LENGTH_OUT => cts_length,
--- CTS_ERROR_PATTERN_OUT => cts_error_pattern,
--- -- Data from Frontends
--- FEE_DATA_IN => FEE_DATA_IN,
--- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
--- FEE_READ_OUT => fee_read,
--- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
--- FEE_BUSY_IN => FEE_BUSY_IN,
--- -- slow control interface
--- START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10
--- BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10
--- CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10
--- DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10
--- DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10
--- MULT_EVT_ENABLE_IN => use_multievents,
--- MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10
--- MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10
--- READOUT_CTR_IN => readout_ctr, -- gk 26.04.10
--- READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10
--- ALLOW_LARGE_IN => allow_large, -- gk 21.07.10
--- SCTRL_DUMMY_SIZE_IN => dummy_size,
--- SCTRL_DUMMY_PAUSE_IN => dummy_pause,
--- -- PacketConstructor interface
--- PC_WR_EN_OUT => pc_wr_en,
--- PC_DATA_OUT => pc_data,
--- PC_READY_IN => pc_ready,
--- PC_SOS_OUT => pc_sos,
--- PC_EOS_OUT => pc_eos, -- gk 07.10.10
--- PC_EOD_OUT => pc_eod,
--- PC_SUB_SIZE_OUT => pc_sub_size,
--- PC_TRIG_NR_OUT => pc_trig_nr,
--- PC_PADDING_OUT => pc_padding,
--- MONITOR_OUT(31 downto 0) => monitor_sent,
--- MONITOR_OUT(63 downto 32) => monitor_dropped,
--- MONITOR_OUT(95 downto 64) => monitor_hr,
--- MONITOR_OUT(127 downto 96) => monitor_sm,
--- MONITOR_OUT(159 downto 128) => monitor_lr,
--- MONITOR_OUT(191 downto 160) => monitor_fifos,
--- MONITOR_OUT(223 downto 192) => monitor_empty,
--- DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1,
--- DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2,
--- DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3,
--- DEBUG_OUT(127 downto 96) => dbg_ipu2gbe4,
--- DEBUG_OUT(159 downto 128) => dbg_ipu2gbe5,
--- DEBUG_OUT(191 downto 160) => dbg_ipu2gbe6,
--- DEBUG_OUT(223 downto 192) => dbg_ipu2gbe7,
--- DEBUG_OUT(255 downto 224) => dbg_ipu2gbe8,
--- DEBUG_OUT(287 downto 256) => dbg_ipu2gbe9,
--- DEBUG_OUT(319 downto 288) => dbg_ipu2gbe10,
--- DEBUG_OUT(351 downto 320) => dbg_ipu2gbe11,
--- DEBUG_OUT(383 downto 352) => dbg_ipu2gbe12
---);
-
----- Second stage: Packet constructor
---PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
---port map(
--- -- ports for user logic
--- RESET => RESET,
--- CLK => CLK,
--- MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
--- PC_WR_EN_IN => pc_wr_en,
--- PC_DATA_IN => pc_data,
--- PC_READY_OUT => pc_ready,
--- PC_START_OF_SUB_IN => pc_sos, --CHANGED TO SLOW CONTROL PULSE
--- PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10
--- PC_END_OF_DATA_IN => pc_eod,
--- PC_TRANSMIT_ON_OUT => pc_transmit_on,
--- -- queue and subevent layer headers
--- PC_SUB_SIZE_IN => pc_sub_size,
--- PC_PADDING_IN => pc_padding, -- gk 29.03.10
--- PC_DECODING_IN => pc_decoding,
--- PC_EVENT_ID_IN => pc_event_id,
--- PC_TRIG_NR_IN => pc_trig_nr,
--- PC_QUEUE_DEC_IN => pc_queue_dec,
--- PC_MAX_FRAME_SIZE_IN => pc_max_frame_size,
--- PC_DELAY_IN => pc_delay, -- gk 28.04.10
--- -- NEW PORTS
--- TC_WR_EN_OUT => tc_wr_en,
--- TC_DATA_OUT => tc_data,
--- TC_H_READY_IN => tc_pc_h_ready,
--- TC_READY_IN => tc_pc_ready,
--- TC_IP_SIZE_OUT => tc_ip_size,
--- TC_UDP_SIZE_OUT => tc_udp_size,
--- --FC_IDENT_OUT => fc_ident,
--- TC_FLAGS_OFFSET_OUT => tc_flags_offset,
--- TC_SOD_OUT => tc_sod,
--- TC_EOD_OUT => tc_eod,
--- DEBUG_OUT(31 downto 0) => dbg_pc1,
--- DEBUG_OUT(63 downto 32) => dbg_pc2
---);
-
-- Third stage: Frame Constructor
FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
port map(
-- MAC part
- MAC: tsmac36 --tsmac35
+ MAC: tsmac35 --tsmac36 --tsmac35
port map(
----------------- clock and reset port declarations ------------------
hclk => CLK,
PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
+ PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
PC_MAX_QUEUE_SIZE_IN : in std_logic_vector(31 downto 0);
architecture RTL of trb_net16_gbe_event_constr is
-type saveStates is (IDLE, SAVE_DATA, CLEANUP);
-signal save_current_state, save_next_state : saveStates;
+attribute syn_encoding : string;
+
+--type saveStates is (IDLE, SAVE_DATA, CLEANUP);
+--signal save_current_state, save_next_state : saveStates;
+--attribute syn_encoding of save_current_state : signal is "onehot";
type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP);
signal load_current_state, load_next_state : loadStates;
+attribute syn_encoding of load_current_state : signal is "onehot";
type saveSubHdrStates is (IDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRG_NR);
signal save_sub_hdr_current_state, save_sub_hdr_next_state : saveSubHdrStates;
+attribute syn_encoding of save_sub_hdr_current_state : signal is "onehot";
signal df_eod, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic;
signal df_q, df_qq : std_logic_vector(7 downto 0);
signal actual_q_size : std_logic_vector(15 downto 0);
signal tc_data : std_logic_vector(7 downto 0);
+signal df_data : std_logic_vector(7 downto 0);
+signal df_eod_q, df_eod_qq : std_logic;
+signal df_wr_en_q, df_wr_en_qq : std_logic;
+signal qsf_full : std_logic;
begin
-- SAVING PART
--*******
-SAVE_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- save_current_state <= IDLE;
- else
- save_current_state <= save_next_state;
- end if;
- end if;
-end process SAVE_MACHINE_PROC;
-
-SAVE_MACHINE : process(save_current_state, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN)
-begin
- case (save_current_state) is
-
- when IDLE =>
- if (PC_START_OF_SUB_IN = '1') then
- save_next_state <= SAVE_DATA;
- else
- save_next_state <= IDLE;
- end if;
-
- when SAVE_DATA =>
- if (PC_END_OF_DATA_IN = '1') then
- save_next_state <= CLEANUP;
- else
- save_next_state <= SAVE_DATA;
- end if;
-
- when CLEANUP =>
- save_next_state <= IDLE;
-
- when others => save_next_state <= IDLE;
-
- end case;
-end process SAVE_MACHINE;
+--SAVE_MACHINE_PROC : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- save_current_state <= IDLE;
+-- else
+-- save_current_state <= save_next_state;
+-- end if;
+-- end if;
+--end process SAVE_MACHINE_PROC;
+--
+--SAVE_MACHINE : process(save_current_state, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN)
+--begin
+-- case (save_current_state) is
+--
+-- when IDLE =>
+-- if (PC_START_OF_SUB_IN = '1') then
+-- save_next_state <= SAVE_DATA;
+-- else
+-- save_next_state <= IDLE;
+-- end if;
+--
+-- when SAVE_DATA =>
+-- if (PC_END_OF_DATA_IN = '1') then
+-- save_next_state <= CLEANUP;
+-- else
+-- save_next_state <= SAVE_DATA;
+-- end if;
+--
+-- when CLEANUP =>
+-- save_next_state <= IDLE;
+--
+-- when others => save_next_state <= IDLE;
+--
+-- end case;
+--end process SAVE_MACHINE;
DF_EOD_PROC : process(CLK)
begin
else
df_eod <= '0';
end if;
+
+ df_eod_q <= df_eod;
+ df_eod_qq <= df_eod_q;
end if;
end process DF_EOD_PROC;
else
df_wr_en <= '0';
end if;
+
+ df_wr_en_q <= df_wr_en;
+ df_wr_en_qq <= df_wr_en_q;
+
+ df_data <= PC_DATA_IN;
end if;
end process DF_WR_EN_PROC;
-
DATA_FIFO : fifo_64kx9
port map(
- Data(7 downto 0) => PC_DATA_IN,
- Data(8) => df_eod,
+ Data(7 downto 0) => df_data, --PC_DATA_IN,
+ Data(8) => df_eod_qq,
WrClock => CLK,
RdClock => CLK,
- WrEn => df_wr_en,
+ WrEn => df_wr_en_qq,
RdEn => df_rd_en,
Reset => RESET,
RPReset => RESET,
end if;
end process DF_QQ_PROC;
-PC_READY_OUT <= '1' when save_current_state = IDLE and df_full = '0' else '0';
+READY_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ --if (save_current_state = IDLE and df_full = '0') then
+-- if (df_full = '0') then
+-- PC_READY_OUT <= '1';
+-- else
+-- PC_READY_OUT <= '0';
+-- end if;
+ PC_READY_OUT <= not qsf_full;
+ end if;
+end process READY_PROC;
--*****
-- subevent headers
-
-SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3 --fifo_512x8 --fifo_4kx8_ecp3
+SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3
port map(
Data => shf_data,
+ --Clock => CLK,
WrClock => CLK,
RdClock => CLK,
WrEn => shf_wr_en,
end if;
end process SUB_INT_CTR_PROC;
-SUB_SIZE_TO_SAVE_PROC : process (CLK) is
+SUB_SIZE_TO_SAVE_PROC : process (CLK)
begin
if rising_edge(CLK) then
if (PC_PADDING_IN = '0') then
shf_data <= sub_size_to_save(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
when SAVE_DECODING =>
- shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
+ --shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
+ if (sub_int_ctr = 0) then
+ shf_data(3 downto 0) <= PC_DECODING_IN(3 downto 0);
+ shf_data(7 downto 4) <= PC_TRIGGER_TYPE_IN;
+ else
+ shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
+ end if;
when SAVE_ID =>
shf_data <= PC_EVENT_ID_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
RPReset => RESET,
Q => qsf_q,
Empty => qsf_empty,
- Full => open
+ Full => qsf_full
);
qsf_wr <= qsf_wr_en or qsf_wr_en_q or qsf_wr_en_qq;
queue_size <= queue_size;
end if;
else
- if (save_current_state = IDLE) then
+ --if (save_current_state = IDLE) then
+ if (PC_START_OF_SUB_IN = '1') then
queue_size <= x"0000_0000"; --queue_size <= x"0000_0028";
elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
if (PC_SUB_SIZE_IN(2) = '1') then
end if;
end process LOAD_MACHINE_PROC;
-LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod)
+LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod, term_ctr)
begin
case (load_current_state) is
-- read from fifos
df_rd_en <= '1' when (load_current_state = LOAD_DATA and TC_RD_EN_IN = '1') or
- (load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1') or
- (load_current_state = LOAD_SUB and header_ctr = 1 and TC_RD_EN_IN = '1')
+ (load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1')
+ --(load_current_state = LOAD_SUB and header_ctr = 1 and TC_RD_EN_IN = '1')
else '0';
shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1') or
);\r
end component;\r
\r
-attribute sys_encoding : string;\r
+attribute syn_encoding : string;\r
\r
type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,\r
TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
signal constructCurrentState, constructNextState : constructStates;\r
signal bsm_constr : std_logic_vector(7 downto 0);\r
-attribute sys_encoding of constructCurrentState: signal is "safe,gray";\r
+attribute syn_encoding of constructCurrentState: signal is "onehot";\r
\r
type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);\r
signal transmitCurrentState, transmitNextState : transmitStates;\r
+attribute syn_encoding of transmitCurrentState : signal is "onehot";\r
+\r
signal bsm_trans : std_logic_vector(3 downto 0);\r
\r
signal headers_int_counter : integer range 0 to 6;\r
signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10\r
\r
signal fpf_reset : std_logic; -- gk 01.01.01\r
+signal link_ok_125, link_ok_q : std_logic;\r
\r
-- gk 09.12.10\r
signal delay_ctr : std_logic_vector(31 downto 0);\r
signal frame_delay_reg : std_logic_vector(31 downto 0);\r
+signal fpf_data_q : std_logic_vector(7 downto 0);\r
+signal fpf_wr_en_q, fpf_eod : std_logic;\r
\r
begin\r
\r
udp_checksum <= x"0000"; -- no checksum test needed\r
--debug <= (others => '0');\r
\r
-ready <= '1' when (constructCurrentState = IDLE)\r
- else '0';\r
-headers_ready <= '1' when (constructCurrentState = SAVE_DATA)\r
- else '0';\r
-\r
-sizeProc: process( put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN)\r
+process(CLK)\r
begin\r
- if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
- ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
- udp_size <= UDP_P_SIZE_IN + x"8";\r
- else\r
- ip_size <= IP_F_SIZE_IN + x"14";\r
- udp_size <= UDP_P_SIZE_IN;\r
+ if rising_edge(CLK) then\r
+ if constructCurrentState = IDLE then\r
+ ready <= '1';\r
+ else\r
+ ready <= '0';\r
+ end if;\r
+ \r
+ if (constructCurrentState = SAVE_DATA) then\r
+ headers_ready <= '1';\r
+ else\r
+ headers_ready <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+--ready <= '1' when (constructCurrentState = IDLE)\r
+-- else '0';\r
+--headers_ready <= '1' when (constructCurrentState = SAVE_DATA)\r
+-- else '0';\r
+ \r
+sizeProc: process(CLK) -- put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
+ ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
+ udp_size <= UDP_P_SIZE_IN + x"8";\r
+ else\r
+ ip_size <= IP_F_SIZE_IN + x"14";\r
+ udp_size <= UDP_P_SIZE_IN;\r
+ end if;\r
end if;\r
end process sizeProc;\r
\r
end if;\r
end process putUdpHeadersProc;\r
\r
---TODO: sync with clock\r
fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN)\r
begin\r
if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
end case;\r
end process fpfDataProc;\r
\r
+syncProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ fpf_data_q <= fpf_data;\r
+ fpf_wr_en_q <= fpf_wr_en;\r
+ fpf_eod <= END_OF_DATA_IN;\r
+ end if;\r
+end process syncProc;\r
+ \r
+\r
\r
readyFramesCtrProc: process( CLK )\r
begin\r
end if;\r
end process readyFramesCtrProc;\r
\r
-fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
+fpfResetProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1' or LINK_OK_IN = '0') then\r
+ fpf_reset <= '1';\r
+ else\r
+ fpf_reset <= '0';\r
+ end if;\r
+ end if;\r
+end process fpfResetProc;\r
+--fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
\r
FINAL_PACKET_FIFO: fifo_4096x9\r
port map( \r
- Data(7 downto 0) => fpf_data,\r
- Data(8) => END_OF_DATA_IN,\r
+ Data(7 downto 0) => fpf_data_q,\r
+ Data(8) => fpf_eod, --END_OF_DATA_IN,\r
WrClock => CLK,\r
RdClock => RD_CLK,\r
- WrEn => fpf_wr_en,\r
+ WrEn => fpf_wr_en_q,\r
RdEn => fpf_rd_en, --FT_TX_RD_EN_IN,\r
Reset => fpf_reset,\r
RPReset => fpf_reset,\r
Full => fpf_full\r
);\r
\r
-fpf_rd_en <= '1' when ((LINK_OK_IN = '1') and (FT_TX_RD_EN_IN = '1'))\r
- or (LINK_OK_IN = '0') -- clear the fifo if link is down\r
+--fpf_rd_en <= FT_TX_RD_EN_IN;\r
+fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1'))\r
+ or (link_ok_125 = '0') -- clear the fifo if link is down\r
else '0';\r
\r
transferToRdClock : signal_sync\r
D_OUT => ready_frames_ctr_q\r
);\r
\r
+process(RD_CLK)\r
+begin\r
+ if rising_edge(RD_CLK) then\r
+ link_ok_q <= LINK_OK_IN;\r
+ link_ok_125 <= link_ok_q;\r
+ end if;\r
+end process;\r
+\r
transmitMachineProc: process( RD_CLK )\r
begin\r
if( rising_edge(RD_CLK) ) then\r
- if( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
+ if( RESET = '1' ) or (link_ok_125 = '0') then -- gk 01.10.10\r
transmitCurrentState <= T_IDLE;\r
else\r
transmitCurrentState <= transmitNextState;\r
end if;\r
end process transmitMachineProc;\r
\r
-transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
+transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
begin\r
case transmitCurrentState is\r
when T_IDLE =>\r
when T_TRANSMIT =>\r
bsm_trans <= x"2";\r
-- gk 03.08.10\r
- if ((LINK_OK_IN = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
+ if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
transmitNextState <= T_CLEANUP;\r
- elsif (LINK_OK_IN = '0') then\r
+ elsif (link_ok_125 = '0') then\r
transmitNextState <= T_PAUSE;\r
else\r
transmitNextState <= T_TRANSMIT;\r
sopProc: process( RD_CLK )\r
begin\r
if rising_edge(RD_CLK) then\r
- if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
+ if ( RESET = '1' ) or (link_ok_125 = '0') then -- gk 01.10.10\r
ft_sop <= '0';\r
elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then\r
ft_sop <= '1';\r
attribute syn_encoding : string;
type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP);
signal filter_current_state, filter_next_state : filter_states;
-attribute syn_encoding of filter_current_state : signal is "safe,gray";
+attribute syn_encoding of filter_current_state : signal is "onehot";
signal fifo_wr_en : std_logic;
signal rx_bytes_ctr : std_logic_vector(15 downto 0);
signal parsed_frames_ctr : std_logic_vector(15 downto 0);
signal ok_frames_ctr : std_logic_vector(15 downto 0);
-signal rx_data : std_logic_vector(8 downto 0);
+signal rx_data, fr_q : std_logic_vector(8 downto 0);
+
+signal fr_src_ip, fr_dest_ip : std_logic_vector(31 downto 0);
+signal fr_dest_udp, fr_src_udp, fr_frame_size, fr_frame_proto : std_logic_vector(15 downto 0);
+signal fr_dest_mac, fr_src_mac : std_logic_vector(47 downto 0);
+signal fr_ip_proto : std_logic_vector(7 downto 0);
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
begin
-DEBUG_OUT(0) <= rec_fifo_empty;
-DEBUG_OUT(1) <= rec_fifo_full;
-DEBUG_OUT(2) <= sizes_fifo_empty;
-DEBUG_OUT(3) <= sizes_fifo_full;
-DEBUG_OUT(7 downto 4) <= state;
--- DEBUG_OUT(19 downto 8) <= dbg_rec_frames(11 downto 0);
--- DEBUG_OUT(31 downto 20) <= parsed_frames_ctr(11 downto 0);
---
--- DEBUG_OUT(47 downto 32) <= dbg_ack_frames;
--- DEBUG_OUT(63 downto 48) <= dbg_drp_frames;
--- DEBUG_OUT(79 downto 64) <= error_frames_ctr;
--- DEBUG_OUT(95 downto 80) <= ok_frames_ctr;
-
-
-- new_frame is asserted when first byte of the frame arrives
NEW_FRAME_PROC : process(RX_MAC_CLK)
begin
end if;
end process FILTER_MACHINE_PROC;
-FILTER_MACHINE : process(filter_current_state, saved_frame_type, saved_proto, g_MY_MAC, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)
+FILTER_MACHINE : process(filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, g_MY_MAC, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)
begin
case filter_current_state is
state <= x"6";
if (frame_type_valid = '1') then
filter_next_state <= SAVE_FRAME;
+ elsif (saved_frame_type = x"0806") then
+ filter_next_state <= SAVE_FRAME;
else
filter_next_state <= DROP_FRAME;
end if;
type_validator : trb_net16_gbe_type_validator
port map(
- CLK => RX_MAC_CLK,
- RESET => RESET,
- FRAME_TYPE_IN => saved_frame_type,
- SAVED_VLAN_ID_IN => saved_vid,
- ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
- VLAN_ID_IN => FR_VLAN_ID_IN,
+ CLK => RX_MAC_CLK,
+ RESET => RESET,
+ FRAME_TYPE_IN => saved_frame_type,
+ SAVED_VLAN_ID_IN => saved_vid,
+ ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
+ VLAN_ID_IN => FR_VLAN_ID_IN,
-- IP level
- IP_PROTOCOLS_IN => saved_proto,
+ IP_PROTOCOLS_IN => saved_proto,
ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN,
-- UDP level
- UDP_PROTOCOL_IN => saved_dest_udp,
+ UDP_PROTOCOL_IN => saved_dest_udp,
ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN,
- VALID_OUT => frame_type_valid
+ VALID_OUT => frame_type_valid
);
---TODO put here a larger fifo maybe (for sure!)
receive_fifo : fifo_4096x9
port map(
- Data(7 downto 0) => MAC_RXD_IN,
- Data(8) => MAC_RX_EOF_IN,
--- Data => rx_data,
+-- Data(7 downto 0) => MAC_RXD_IN,
+-- Data(8) => MAC_RX_EOF_IN,
+ Data => rx_data,
WrClock => RX_MAC_CLK,
RdClock => CLK,
WrEn => fifo_wr_en,
RdEn => FR_RD_EN_IN,
Reset => RESET,
RPReset => RESET,
- Q => FR_Q_OUT,
+ Q => fr_q, --FR_Q_OUT,
Empty => rec_fifo_empty,
Full => rec_fifo_full
);
-- BUG HERE, probably more lost bytes in the fifo in other conditions
-fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or
- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
- ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
- (filter_current_state = DECIDE and frame_type_valid = '1')))
- else '0';
-
---RX_FIFO_SYNC : process(RX_MAC_CLK)
---begin
--- if rising_edge(RX_MAC_CLK) then
---
--- rx_data(8) <= MAC_RX_EOF_IN;
--- rx_data(7 downto 0) <= MAC_RXD_IN;
---
--- if (MAC_RX_EN_IN = '1') then
--- if (filter_current_state = SAVE_FRAME) then
--- fifo_wr_en <= '1';
--- elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then
--- fifo_wr_en <= '1';
--- elsif (filter_current_state = DECIDE and frame_type_valid = '1') then
--- fifo_wr_en <= '1';
--- else
--- fifo_wr_en <= '0';
--- end if;
--- else
--- fifo_wr_en <= '0';
--- end if;
---
--- end if;
---end process RX_FIFO_SYNC;
+--fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or
+-- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
+-- ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
+-- (filter_current_state = DECIDE and frame_type_valid = '1')))
+-- else '0';
+
+RX_FIFO_SYNC : process(RX_MAC_CLK)
+begin
+ if rising_edge(RX_MAC_CLK) then
+
+ rx_data(8) <= MAC_RX_EOF_IN;
+ rx_data(7 downto 0) <= MAC_RXD_IN;
+
+ if (MAC_RX_EN_IN = '1') then
+ if (filter_current_state = SAVE_FRAME) then
+ fifo_wr_en <= '1';
+ elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then
+ fifo_wr_en <= '1';
+ elsif (filter_current_state = DECIDE and frame_type_valid = '1') then
+ fifo_wr_en <= '1';
+ else
+ fifo_wr_en <= '0';
+ end if;
+ else
+ fifo_wr_en <= '0';
+ end if;
+
+ MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;
+ end if;
+end process RX_FIFO_SYNC;
-MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;
sizes_fifo : fifo_512x32
port map(
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(15 downto 0) => FR_FRAME_SIZE_OUT,
- Q(31 downto 16) => FR_FRAME_PROTO_OUT,
+ Q(15 downto 0) => fr_frame_size, --FR_FRAME_SIZE_OUT,
+ Q(31 downto 16) => fr_frame_proto, --FR_FRAME_PROTO_OUT,
Empty => sizes_fifo_empty,
Full => sizes_fifo_full
);
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(47 downto 0) => FR_SRC_MAC_ADDRESS_OUT,
- Q(63 downto 48) => FR_SRC_UDP_PORT_OUT,
+ Q(47 downto 0) => fr_src_mac, --FR_SRC_MAC_ADDRESS_OUT,
+ Q(63 downto 48) => fr_src_udp, --FR_SRC_UDP_PORT_OUT,
Q(71 downto 64) => dump2,
Empty => open,
Full => open
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(47 downto 0) => FR_DEST_MAC_ADDRESS_OUT,
- Q(63 downto 48) => FR_DEST_UDP_PORT_OUT,
+ Q(47 downto 0) => fr_dest_mac, --FR_DEST_MAC_ADDRESS_OUT,
+ Q(63 downto 48) => fr_dest_udp, --FR_DEST_UDP_PORT_OUT,
Q(71 downto 64) => dump,
Empty => open,
Full => open
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(31 downto 0) => FR_SRC_IP_ADDRESS_OUT,
- Q(63 downto 32) => FR_DEST_IP_ADDRESS_OUT,
- Q(71 downto 64) => FR_IP_PROTOCOL_OUT,
+ Q(31 downto 0) => fr_src_ip, --FR_SRC_IP_ADDRESS_OUT,
+ Q(63 downto 32) => fr_dest_ip, --FR_DEST_IP_ADDRESS_OUT,
+ Q(71 downto 64) => fr_ip_proto, --FR_IP_PROTOCOL_OUT,
Empty => open,
Full => open
);
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;
+ FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;
+ FR_IP_PROTOCOL_OUT <= fr_ip_proto;
+ FR_DEST_UDP_PORT_OUT <= fr_dest_udp;
+ FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;
+ FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;
+ FR_SRC_UDP_PORT_OUT <= fr_src_udp;
+ FR_FRAME_PROTO_OUT <= fr_frame_proto;
+ FR_FRAME_SIZE_OUT <= fr_frame_size;
+ FR_Q_OUT <= fr_q;
+ end if;
+end process;
+
FRAME_VALID_PROC : process(RX_MAC_CLK)
begin
if rising_edge(RX_MAC_CLK) then
if rising_edge(RX_MAC_CLK) then
if (RESET = '1') or (delayed_frame_valid_q = '1') then
--if (RESET = '1') or (frame_valid_q = '1') then
- rx_bytes_ctr <= (others => '0');
+ rx_bytes_ctr <= x"0001";
elsif (fifo_wr_en = '1') then
rx_bytes_ctr <= rx_bytes_ctr + x"1";
end if;
\r
type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED);\r
signal macInitState, macInitNextState : macInitStates;\r
-attribute syn_encoding of macInitState: signal is "safe,gray";\r
+attribute syn_encoding of macInitState: signal is "onehot";\r
signal bsm_init : std_logic_vector(3 downto 0);\r
\r
type macStates is (M_RESETING, M_IDLE, M_INIT);\r
signal macCurrentState, macNextState : macStates;\r
+attribute syn_encoding of macCurrentState : signal is "onehot";\r
signal bsm_mac : std_logic_vector(3 downto 0);\r
\r
type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO);\r
signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState: signal is "safe,gray";\r
+attribute syn_encoding of transmitCurrentState: signal is "onehot";\r
signal bsm_trans : std_logic_vector(3 downto 0);\r
\r
signal tx_fifoavail_i : std_logic;\r
signal FifoEmpty : std_logic;\r
signal debug : std_logic_vector(63 downto 0);\r
signal sent_ctr : std_logic_vector(31 downto 0);\r
+signal link_ok_125 : std_logic;\r
\r
begin\r
\r
+linkOkSync : pulse_sync\r
+port map(\r
+ CLK_A_IN => CLK,\r
+ RESET_A_IN => RESET,\r
+ PULSE_A_IN => LINK_OK_IN,\r
+ CLK_B_IN => TX_MAC_CLK,\r
+ RESET_B_IN => RESET,\r
+ PULSE_B_OUT => link_ok_125\r
+);\r
+\r
-- Fakes\r
debug(63 downto 32) <= (others => '0');\r
--debug(31 downto 0) <= sent_ctr;\r
end if;\r
end process TransmitStatemachineProc;\r
\r
---TransmitStateMachine : process (transmitCurrentState, macCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN)\r
TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN)\r
begin\r
case transmitCurrentState is\r
when T_IDLE =>\r
bsm_trans <= x"0";\r
- if (START_OF_PACKET_IN = '1') then --and (macCurrentState = M_IDLE)) then\r
+ if (START_OF_PACKET_IN = '1') then\r
transmitNextState <= T_TRANSMIT;\r
else\r
transmitNextState <= T_IDLE;\r
end if;\r
when T_WAITFORFIFO =>\r
bsm_trans <= x"2";\r
- if (TX_DONE_IN = '1') then --or (TX_DISCFRM_IN = '1') then\r
+ if (TX_DONE_IN = '1') then\r
transmitNextState <= T_IDLE;\r
else\r
transmitNextState <= T_WAITFORFIFO;\r
PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
PC_PADDING_OUT : out std_logic;
+ PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0);
MONITOR_OUT : out std_logic_vector(223 downto 0);
DEBUG_OUT : out std_logic_vector(383 downto 0)
);
architecture RTL of trb_net16_gbe_ipu_interface is
+attribute syn_encoding : string;
+
type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, RESET_FIFO, CLEANUP, DROP_SUBEVENT);
signal save_current_state, save_next_state : saveStates;
+attribute syn_encoding of save_current_state : signal is "onehot";
-type loadStates is (IDLE, REMOVE, WAIT_ONE, DECIDE, CALC_PADDING, WAIT_FOR_LOAD, LOAD, LOAD_LAST_ONE, LOAD_LAST_TWO, DROP, CLOSE);
+--type loadStates is (IDLE, REMOVE, WAIT_ONE, DECIDE, CALC_PADDING, WAIT_FOR_LOAD, LOAD, LOAD_LAST_ONE, LOAD_LAST_TWO, DROP, CLOSE);
+type loadStates is (IDLE, REMOVE, WAIT_ONE, DECIDE, WAIT_FOR_LOAD, LOAD, CLOSE);
signal load_current_state, load_next_state : loadStates;
+attribute syn_encoding of load_current_state : signal is "onehot";
signal sf_data : std_Logic_vector(15 downto 0);
signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eod, sf_eod_q, sf_eod_qq : std_logic;
signal trigger_random : std_logic_vector(7 downto 0);
signal trigger_number : std_logic_vector(15 downto 0);
signal subevent_size : std_logic_vector(17 downto 0);
+signal trigger_type : std_logic_vector(3 downto 0);
signal bank_select : std_logic_vector(3 downto 0);
signal readout_ctr : std_logic_vector(23 downto 0);
SF_DATA_EOD_PROC : process(CLK_IPU)
begin
if rising_edge(CLK_IPU) then
- case (save_current_state) is
+ case (save_current_state) is
when SAVE_EVT_ADDR =>
sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0);
- sf_data(15 downto 4) <= x"abc";
+ sf_data(7 downto 4) <= CTS_READOUT_TYPE_IN;
+ sf_data(15 downto 8) <= x"ab";
save_eod <= '0';
when SAVE_DATA =>
AmFullThresh => b"111_1111_1110_1111", --b"111_1111_1110_1111", -- 0x7fef = 32751
Q(7 downto 0) => sf_q,
Q(8) => sf_eod,
- WCNT => open,
- RCNT => open,
+ --WCNT => open,
+ --RCNT => open,
Empty => sf_empty,
AlmostEmpty => open,
- Full => sf_full,
+ Full => open, --sf_afull -- WARNING, JUST FOR DEBUG
AlmostFull => sf_afull
);
-sf_reset <= '1' when save_current_state = DROP_SUBEVENT or RESET = '1' else '0';
+
+SF_RESET_PROC : process(CLK_IPU)
+begin
+ if rising_edge(CLK_IPU) then
+ if (RESET = '1') then
+ sf_reset <= '1';
+ elsif (save_current_state = DROP_SUBEVENT) then
+ sf_reset <= '1';
+ else
+ sf_reset <= '0';
+ end if;
+ end if;
+end process SF_RESET_PROC;
--*********
-- LOADING PART
load_next_state <= DECIDE;
when DECIDE =>
- load_next_state <= WAIT_FOR_LOAD; --CALC_PADDING;
-
--- when CALC_PADDING =>
--- load_next_state <= WAIT_FOR_LOAD;
+ load_next_state <= WAIT_FOR_LOAD;
when WAIT_FOR_LOAD =>
if (PC_READY_IN = '1') then
when LOAD =>
if (sf_eod = '1') then
- load_next_state <= LOAD_LAST_ONE;
+ load_next_state <= CLOSE; --LOAD_LAST_ONE;
else
load_next_state <= LOAD;
end if;
- when LOAD_LAST_ONE =>
- load_next_state <= LOAD_LAST_TWO;
-
- when LOAD_LAST_TWO =>
- load_next_state <= CLOSE;
+-- when LOAD_LAST_ONE =>
+-- load_next_state <= LOAD_LAST_TWO;
+--
+-- when LOAD_LAST_TWO =>
+-- load_next_state <= CLOSE;
--when DROP =>
when CLOSE =>
subevent_size(9 downto 2) <= pc_data;
elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0008") then
subevent_size(17 downto 10) <= pc_data;
--- elsif (load_current_state = CALC_PADDING and padding_needed = '1') then
--- subevent_size <= subevent_size + x"4"+ x"8";
--- elsif (load_current_state = CALC_PADDING and padding_needed = '0') then
--- subevent_size <= subevent_size + x"8";
elsif (load_current_state = DECIDE) then
subevent_size <= subevent_size + x"8";
else
end if;
end process SUBEVENT_SIZE_PROC;
---PADDING_NEEDED_PROC : process(CLK_GBE)
---begin
--- if rising_edge(CLK_GBE) then
--- if (load_current_state = IDLE) then
--- padding_needed <= '0';
--- elsif (load_current_state = DECIDE and subevent_size(2) = '1') then
--- padding_needed <= '1';
--- end if;
--- end if;
---end process PADDING_NEEDED_PROC;
-
-
+TRIGGER_TYPE_PROC : process(CLK_GBE)
+begin
+ if rising_edge(CLK_GBE) then
+ if (load_current_state = IDLE) then
+ trigger_type <= x"0";
+ elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
+ trigger_type <= pc_data(7 downto 4);
+ else
+ trigger_type <= trigger_type;
+ end if;
+ end if;
+end process TRIGGER_TYPE_PROC;
-- end of extraction
--*****
if (load_current_state = IDLE or load_current_state = DECIDE) then
loaded_bytes_ctr <= (others => '0');
elsif (sf_rd_en = '1') then
- if (load_current_state = REMOVE or load_current_state = LOAD or load_current_state = DROP) then
+ if (load_current_state = REMOVE or load_current_state = LOAD) then
loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
else
loaded_bytes_ctr <= loaded_bytes_ctr;
--*****
-- event builder selection
---TODO: close the currrent multievent packet in case event builder address changes
+--TODO: close the current multievent packet in case event builder address changes
BANK_SELECT_PROC : process(CLK_GBE)
begin
if rising_edge(CLK_GBE) then
if (load_current_state = LOAD) then
PC_WR_EN_OUT <= '1';
- elsif (load_current_state = LOAD_LAST_ONE or load_current_state = LOAD_LAST_TWO) then
- PC_WR_EN_OUT <= '1';
+-- elsif (load_current_state = LOAD_LAST_ONE or load_current_state = LOAD_LAST_TWO) then
+-- PC_WR_EN_OUT <= '1';
else
PC_WR_EN_OUT <= '0';
end if;
PC_SOS_PROC : process(CLK_GBE)
begin
if rising_edge(CLK_GBE) then
- --if (load_current_state = CALC_PADDING) then
if (load_current_state = DECIDE) then
PC_SOS_OUT <= '1';
else
PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & subevent_size;
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random;
+PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random;
+
+PC_TRIGGER_TYPE_OUT <= trigger_type;
PC_PADDING_OUT <= '0'; --padding_needed; not used anymore
architecture trb_net16_gbe_mac_control of trb_net16_gbe_mac_control is
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_mac_control : architecture is "GBE_BUF_group";
+attribute syn_encoding : string;
-type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL, WRITE_MAX_PKT_SIZE, SKIP, WRITE_IPG,
- WRITE_MAC0, WRITE_MAC1, WRITE_MAC2, ENABLE, READY);
+type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL1, WRITE_TX_RX_CTRL2, ENABLE, READY);
signal mac_conf_current_state, mac_conf_next_state : mac_conf_states;
+attribute syn_encoding of mac_conf_current_state : signal is "onehot";
signal tsmac_ready : std_logic;
-signal reg_mode : std_logic_vector(15 downto 0);
-signal reg_tx_rx_ctrl : std_logic_vector(15 downto 0);
+signal reg_mode : std_logic_vector(7 downto 0);
+signal reg_tx_rx_ctrl1, reg_tx_rx_ctrl2 : std_logic_vector(7 downto 0);
signal reg_max_pkt_size : std_logic_vector(15 downto 0);
signal reg_ipg : std_logic_vector(15 downto 0);
signal reg_mac0 : std_logic_vector(15 downto 0);
begin
-DEBUG_OUT(3 downto 0) <= state;
-DEBUG_OUT(7 downto 4) <= haddr(3 downto 0);
-DEBUG_OUT(8) <= hcs_n;
-DEBUG_OUT(9) <= hwrite_n;
-DEBUG_OUT(63 downto 11) <= (others => '0');
-
-reg_mode(15 downto 4) <= (others => '0'); -- reserved
+reg_mode(7 downto 4) <= x"0";
reg_mode(3) <= '1'; -- tx_en
reg_mode(2) <= '1'; -- rx_en
reg_mode(1) <= '1'; -- flow_control en
reg_mode(0) <= MC_GBE_EN_IN; -- gbe en
-reg_tx_rx_ctrl(15 downto 9) <= (others => '0'); -- reserved
-reg_tx_rx_ctrl(8) <= '1'; -- receive short
-reg_tx_rx_ctrl(7) <= '1'; -- receive broadcast
-reg_tx_rx_ctrl(6) <= '1'; -- drop control
-reg_tx_rx_ctrl(5) <= '0'; -- half_duplex en
-reg_tx_rx_ctrl(4) <= '1'; -- receive multicast
-reg_tx_rx_ctrl(3) <= '1'; -- receive pause
-reg_tx_rx_ctrl(2) <= '0'; -- transmit disable FCS
-reg_tx_rx_ctrl(1) <= '1'; -- receive discard FCS and padding
-reg_tx_rx_ctrl(0) <= MC_PROMISC_IN; -- promiscuous mode
-
-reg_max_pkt_size(15 downto 0) <= x"05EE"; -- 1518 default value
-
-reg_ipg(15 downto 5) <= (others => '0');
-reg_ipg(4 downto 0) <= "01100"; -- default value inter-packet-gap in byte time
-
-reg_mac0(7 downto 0) <= MC_MAC_ADDR_IN(7 downto 0);
-reg_mac0(15 downto 8) <= MC_MAC_ADDR_IN(15 downto 8);
-reg_mac1(7 downto 0) <= MC_MAC_ADDR_IN(23 downto 16);
-reg_mac1(15 downto 8) <= MC_MAC_ADDR_IN(31 downto 24);
-reg_mac2(7 downto 0) <= MC_MAC_ADDR_IN(39 downto 32);
-reg_mac2(15 downto 8) <= MC_MAC_ADDR_IN(47 downto 40);
+reg_tx_rx_ctrl2(7 downto 1) <= (others => '0'); -- reserved
+reg_tx_rx_ctrl2(0) <= '1'; -- receive short
+reg_tx_rx_ctrl1(7) <= '1'; -- receive broadcast
+reg_tx_rx_ctrl1(6) <= '1'; -- drop control
+reg_tx_rx_ctrl1(5) <= '0'; -- half_duplex en
+reg_tx_rx_ctrl1(4) <= '1'; -- receive multicast
+reg_tx_rx_ctrl1(3) <= '1'; -- receive pause
+reg_tx_rx_ctrl1(2) <= '0'; -- transmit disable FCS
+reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding
+reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode
MAC_CONF_MACHINE_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') or (MC_RECONF_IN = '1') then
+ if (RESET = '1') then
mac_conf_current_state <= IDLE;
else
mac_conf_current_state <= mac_conf_next_state;
end if;
end process MAC_CONF_MACHINE_PROC;
-MAC_CONF_MACHINE : process(mac_conf_current_state, tsmac_ready, haddr)
+MAC_CONF_MACHINE : process(mac_conf_current_state, MC_RECONF_IN, TSM_HREADY_N_IN)
begin
case mac_conf_current_state is
when IDLE =>
- state <= x"1";
- if (tsmac_ready = '0') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= IDLE;
- end if;
+ if (MC_RECONF_IN = '1') then
+ mac_conf_next_state <= DISABLE;
+ else
+ mac_conf_next_state <= IDLE;
+ end if;
when DISABLE =>
- state <= x"2";
- if (haddr = x"01") then
- mac_conf_next_state <= WRITE_TX_RX_CTRL;
- else
- mac_conf_next_state <= DISABLE;
- end if;
-
- when WRITE_TX_RX_CTRL =>
- state <= x"3";
- if (haddr = x"03") then
- mac_conf_next_state <= WRITE_MAX_PKT_SIZE;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL;
- end if;
-
- when WRITE_MAX_PKT_SIZE =>
- state <= x"4";
- if (haddr = x"05") then
- mac_conf_next_state <= SKIP;
- else
- mac_conf_next_state <= WRITE_MAX_PKT_SIZE;
- end if;
-
- when SKIP =>
- state <= x"5";
- if (haddr = x"07") then
- mac_conf_next_state <= WRITE_IPG;
- else
- mac_conf_next_state <= SKIP;
- end if;
-
- when WRITE_IPG =>
- state <= x"6";
- if (haddr = x"09") then
- mac_conf_next_state <= WRITE_MAC0;
- else
- mac_conf_next_state <= WRITE_IPG;
- end if;
-
- when WRITE_MAC0 =>
- state <= x"7";
- if (haddr = x"0B") then
- mac_conf_next_state <= WRITE_MAC1;
- else
- mac_conf_next_state <= WRITE_MAC0;
- end if;
-
- when WRITE_MAC1 =>
- state <= x"8";
- if (haddr = x"0D") then
- mac_conf_next_state <= WRITE_MAC2;
- else
- mac_conf_next_state <= WRITE_MAC1;
- end if;
-
- when WRITE_MAC2 =>
- state <= x"9";
- if (haddr = x"0F") then
- mac_conf_next_state <= ENABLE;
- else
- mac_conf_next_state <= WRITE_MAC2;
- end if;
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= WRITE_TX_RX_CTRL1;
+ else
+ mac_conf_next_state <= DISABLE;
+ end if;
+
+ when WRITE_TX_RX_CTRL1 =>
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= WRITE_TX_RX_CTRL2;
+ else
+ mac_conf_next_state <= WRITE_TX_RX_CTRL1;
+ end if;
+
+ when WRITE_TX_RX_CTRL2 =>
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= ENABLE;
+ else
+ mac_conf_next_state <= WRITE_TX_RX_CTRL2;
+ end if;
when ENABLE =>
- state <= x"a";
- if (haddr = x"01") then
- mac_conf_next_state <= READY;
- else
- mac_conf_next_state <= ENABLE;
- end if;
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= READY;
+ else
+ mac_conf_next_state <= ENABLE;
+ end if;
when READY =>
- state <= x"b";
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= IDLE;
- else
- mac_conf_next_state <= READY;
- end if;
+ if (MC_RECONF_IN = '1') then
+ mac_conf_next_state <= DISABLE;
+ else
+ mac_conf_next_state <= READY;
+ end if;
end case;
HADDR_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') or (mac_conf_current_state = IDLE) then
- haddr <= (others => '0');
- elsif (mac_conf_current_state /= IDLE) and (hcs_n = '0') and (TSM_HREADY_N_IN = '0') then
- haddr <= haddr + x"1";
- elsif (mac_conf_current_state = SKIP) then
- haddr <= haddr + x"1";
- elsif (mac_conf_current_state = WRITE_MAC2) and (haddr = x"0F") and (TSM_HREADY_N_IN = '0') then
- haddr <= (others => '0');
- end if;
- end if;
+ if rising_edge(CLK) then
+ case mac_conf_current_state is
+ when IDLE =>
+ TSM_HADDR_OUT <= x"00";
+ when DISABLE =>
+ TSM_HADDR_OUT <= x"00";
+ when WRITE_TX_RX_CTRL1 =>
+ TSM_HADDR_OUT <= x"02";
+ when WRITE_TX_RX_CTRL2 =>
+ TSM_HADDR_OUT <= x"03";
+ when ENABLE =>
+ TSM_HADDR_OUT <= x"00";
+ when READY =>
+ TSM_HADDR_OUT <= x"00";
+ end case;
+ end if;
end process HADDR_PROC;
-HDATA_PROC : process(mac_conf_current_state)
+HDATA_PROC : process(CLK)
begin
-
- case mac_conf_current_state is
-
- when WRITE_TX_RX_CTRL =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when WRITE_MAX_PKT_SIZE =>
- TSM_HDATA_OUT <= reg_max_pkt_size(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when WRITE_IPG =>
- TSM_HDATA_OUT <= reg_ipg(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when WRITE_MAC0 =>
- TSM_HDATA_OUT <= reg_mac0(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when WRITE_MAC1 =>
- TSM_HDATA_OUT <= reg_mac1(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when WRITE_MAC2 =>
- TSM_HDATA_OUT <= reg_mac2(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when ENABLE =>
- TSM_HDATA_OUT <= reg_mode(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
-
- when others =>
- TSM_HDATA_OUT <= (others => '0');
-
- end case;
-
+ if rising_edge(CLK) then
+ case mac_conf_current_state is
+ when IDLE =>
+ TSM_HDATA_OUT <= x"00";
+ when DISABLE =>
+ TSM_HDATA_OUT <= x"00";
+ when WRITE_TX_RX_CTRL1 =>
+ TSM_HDATA_OUT <= reg_tx_rx_ctrl1;
+ when WRITE_TX_RX_CTRL2 =>
+ TSM_HDATA_OUT <= reg_tx_rx_ctrl2;
+ when ENABLE =>
+ TSM_HDATA_OUT <= reg_mode;
+ when READY =>
+ TSM_HDATA_OUT <= x"00";
+ end case;
+ end if;
end process HDATA_PROC;
--- delay hready by one clock cycle to keep hcs and hwrite active during hready
-HREADY_Q_PROC : process(CLK)
+process(CLK)
begin
- if rising_edge(CLK) then
- hready_n_q <= TSM_HREADY_N_IN;
- end if;
-end process HREADY_Q_PROC;
-
-hdata_pointer <= 1 when haddr(0) = '1' else 0;
-
-hcs_n <= '0' when (mac_conf_current_state /= IDLE) and (mac_conf_current_state /= SKIP) and (mac_conf_current_state /= READY) and (hready_n_q = '1')
- else '1'; -- should also support reading
-
-hwrite_n <= hcs_n when (mac_conf_current_state /= IDLE) else '1'; -- active only during writing
-
-tsmac_ready <= '1' when (mac_conf_current_state = READY) else '0';
+ if rising_edge(CLK) then
+ if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then
+ hcs_n <= '1';
+ hwrite_n <= '1';
+ elsif (TSM_HREADY_N_IN = '1') then
+ hcs_n <= '0';
+ hwrite_n <= '0';
+ else
+ hcs_n <= '1';
+ hwrite_n <= '1';
+ end if;
+
+ if (mac_conf_current_state = READY) then
+ tsmac_ready <= '1';
+ else
+ tsmac_ready <= '0';
+ end if;
+ end if;
+end process;
-TSM_HADDR_OUT <= haddr;
TSM_HCS_N_OUT <= hcs_n;
TSM_HWRITE_N_OUT <= hwrite_n;
-TSM_HREAD_N_OUT <= '1'; -- for the moment no reading
+TSM_HREAD_N_OUT <= '1';
MC_TSMAC_READY_OUT <= tsmac_ready;
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group";
+attribute syn_encoding : string;
+
signal tsm_ready : std_logic;
signal tsm_reconf : std_logic;
signal tsm_haddr : std_logic_vector(7 downto 0);
type link_states is (ACTIVE, INACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
signal link_current_state, link_next_state : link_states;
+attribute syn_encoding of link_current_state : signal is "onehot";
signal link_down_ctr : std_logic_vector(15 downto 0);
signal link_down_ctr_lock : std_logic;
type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP);
signal flow_current_state, flow_next_state : flow_states;
+attribute syn_encoding of flow_current_state : signal is "onehot";
signal state : std_logic_vector(3 downto 0);
signal link_state : std_logic_vector(3 downto 0);
signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, FINISH, CLEANUP);
+type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP);
signal redirect_current_state, redirect_next_state : redirect_states;
+attribute syn_encoding of redirect_current_state : signal is "onehot";
-signal disable_redirect, ps_wr_en_q : std_logic;
+signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic;
type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
RESET => RESET,
PS_DATA_IN => rc_data_local, -- RC_DATA_IN,
- PS_WR_EN_IN => ps_wr_en_q, --ps_wr_en,
+ PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en,
PS_PROTO_SELECT_IN => proto_select,
PS_BUSY_OUT => ps_busy,
PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN,
else
disable_redirect <= '0';
end if;
+ else
+ disable_redirect <= disable_redirect;
end if;
end if;
end process DISABLE_REDIRECT_PROC;
when DROP =>
redirect_state <= x"7";
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= FINISH;
+ redirect_next_state <= WAIT_ONE; --FINISH;
else
redirect_next_state <= DROP;
end if;
when LOAD =>
redirect_state <= x"2";
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= FINISH;
+ redirect_next_state <= WAIT_ONE; --FINISH;
else
redirect_next_state <= LOAD;
end if;
else
redirect_next_state <= BUSY;
end if;
+
+ when WAIT_ONE =>
+ redirect_state <= x"f";
+ redirect_next_state <= FINISH;
when FINISH =>
redirect_state <= x"4";
if rising_edge(CLK) then
if (RESET = '1') then
RC_LOADING_DONE_OUT <= '0';
- elsif (RC_DATA_IN(8) = '1' and ps_wr_en = '1') then
+ elsif (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then
RC_LOADING_DONE_OUT <= '1';
else
RC_LOADING_DONE_OUT <= '0';
PS_WR_EN_PROC : process(CLK)
begin
if rising_edge(CLK) then
- ps_wr_en <= rc_rd_en;
- ps_wr_en_q <= ps_wr_en;
+ ps_wr_en <= rc_rd_en;
+ ps_wr_en_q <= ps_wr_en;
+ ps_wr_en_qq <= ps_wr_en_q;
end if;
end process PS_WR_EN_PROC;
loaded_bytes_ctr <= (others => '0');
elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
+ else
+ loaded_bytes_ctr <= loaded_bytes_ctr;
end if;
end if;
end process LOADED_BYTES_CTR_PROC;
--*********************
-- DATA FLOW CONTROL
---TODO: do I really need this crap?
FLOW_MACHINE_PROC : process(CLK)
begin
if rising_edge(CLK) then
end case;
end process FLOW_MACHINE;
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (flow_current_state = IDLE and ps_response_ready = '1') then
+ TC_TRANSMIT_CTRL_OUT <= '1';
+ else
+ TC_TRANSMIT_CTRL_OUT <= '0';
+ end if;
+
+ if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then
+ mc_busy <= '1';
+ else
+ mc_busy <= '0';
+ end if;
+ end if;
+end process;
--TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) else '0';
-TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = IDLE and ps_response_ready = '1') else '0';
+--TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = IDLE and ps_response_ready = '1') else '0';
--mc_busy <= '0' when flow_current_state = IDLE else '1';
-mc_busy <= '1' when flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC else '0';
+--mc_busy <= '1' when flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC else '0';
--***********************
-- LINK STATE CONTROL
if (g_SIMULATE = 0) then
link_current_state <= INACTIVE;
else
- link_current_state <= GET_ADDRESS; --ACTIVE;
+ link_current_state <= ACTIVE; --GET_ADDRESS; --ACTIVE;
end if;
else
link_current_state <= link_next_state;
elsif (link_current_state = TIMEOUT) then
link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
end if;
+
+ if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then
+ link_ok <= '1';
+ else
+ link_ok <= '0';
+ end if;
+
+ if (link_current_state = GET_ADDRESS) then
+ dhcp_start <= '1';
+ else
+ dhcp_start <= '0';
+ end if;
end if;
end process LINK_OK_CTR_PROC;
---link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) or (link_current_state = WAIT_FOR_BOOT) else '0';
-link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0';
+--link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0';
WAIT_CTR_PROC : process(CLK)
begin
end if;
end process WAIT_CTR_PROC;
-dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0';
+--dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0';
--LINK_DOWN_CTR_PROC : process(CLK)
--begin
TSMAC_CONTROLLER : trb_net16_gbe_mac_control
port map(
- CLK => CLK,
+ CLK => CLK,
RESET => RESET,
-- signals to/from main controller
TSM_HREADY_N_IN => TSM_HREADY_N_IN,
TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN,
- DEBUG_OUT => mac_control_debug
+ DEBUG_OUT => open
);
--DEBUG_OUT <= mac_control_debug;
-
-tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0';
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
+ tsm_reconf <= '1';
+ else
+ tsm_reconf <= '0';
+ end if;
+ end if;
+end process;
+--tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0';
TSM_HADDR_OUT <= tsm_haddr;
TSM_HCS_N_OUT <= tsm_hcs_n;
if (UDP_PROTOCOL_IN = x"0044") then -- DHCP Client
CODE_OUT(1) <= '1';
-- No. 4 = SCTRL
- elsif (UDP_PROTOCOL_IN = x"61a8") then -- SCTRL module
- CODE_OUT(3) <= '1';
+ elsif (UDP_PROTOCOL_IN = x"6590") then -- SCTRL module
+ CODE_OUT(2) <= '1';
else
-- branch for pure IPv4
CODE_OUT <= (others => '0');
end if;
-- No. 3 = ICMP
- elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP
- CODE_OUT(2) <= '1';
+-- elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP
+-- CODE_OUT(2) <= '1';
else
CODE_OUT <= (others => '0');
end if;
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group";
+attribute syn_encoding : string;
+
signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP);
signal select_current_state, select_next_state : select_states;
+attribute syn_encoding of select_current_state : signal is "onehot";
signal state : std_logic_vector(3 downto 0);
signal index : integer range 0 to c_MAX_PROTOCOLS - 1;
signal mult : std_logic;
signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
begin
+zeros <= (others => '0');
+
-- protocol Nr. 1 ARP
ARP : trb_net16_gbe_response_constructor_ARP
generic map( STAT_ADDRESS_BASE => 6
);
-- protocol No. 3 Ping
-Ping : trb_net16_gbe_response_constructor_PseudoPing
-generic map( STAT_ADDRESS_BASE => 3
+--Ping : trb_net16_gbe_response_constructor_Ping
+--generic map( STAT_ADDRESS_BASE => 3
+--)
+--port map (
+-- CLK => CLK,
+-- RESET => RESET,
+--
+------ INTERFACE
+-- PS_DATA_IN => PS_DATA_IN,
+-- PS_WR_EN_IN => PS_WR_EN_IN,
+-- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
+-- PS_RESPONSE_READY_OUT => resp_ready(2),
+-- PS_BUSY_OUT => busy(2),
+-- PS_SELECTED_IN => selected(2),
+--
+-- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+-- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+-- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+-- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+-- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+-- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+--
+-- TC_RD_EN_IN => TC_RD_EN_IN,
+-- TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
+-- TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
+-- TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
+-- TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
+-- TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
+--
+-- TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
+-- TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
+-- TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
+-- TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
+-- TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
+-- TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
+--
+-- STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
+-- STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
+-- STAT_DATA_RDY_OUT => stat_rdy(2),
+-- STAT_DATA_ACK_IN => stat_ack(2),
+-- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
+-- SENT_FRAMES_OUT => SENT_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
+-- DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
+---- END OF INTERFACE
+--);
+
+SCTRL : trb_net16_gbe_response_constructor_SCTRL
+generic map( STAT_ADDRESS_BASE => 8
)
port map (
CLK => CLK,
TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
- TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
+ TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
STAT_DATA_RDY_OUT => stat_rdy(2),
STAT_DATA_ACK_IN => stat_ack(2),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
SENT_FRAMES_OUT => SENT_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
- DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
--- END OF INTERFACE
-);
-
-SCTRL : trb_net16_gbe_response_constructor_SCTRL
-generic map( STAT_ADDRESS_BASE => 8
-)
-port map (
- CLK => CLK,
- RESET => RESET,
-
--- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
- PS_RESPONSE_READY_OUT => resp_ready(3),
- PS_BUSY_OUT => busy(3),
- PS_SELECTED_IN => selected(3),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
- TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
- TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
- TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
- TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
- TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
- TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
-
- STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
- STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(3),
- STAT_DATA_ACK_IN => stat_ack(3),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
- SENT_FRAMES_OUT => SENT_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
-- END OF INTERFACE
GSC_CLK_IN => GSC_CLK_IN,
MAKE_RESET_OUT => MAKE_RESET_OUT,
- DEBUG_OUT => PROTOS_DEBUG_OUT(4 * 32 - 1 downto 3 * 32)
+ DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
);
TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
-- INTERFACE
PS_DATA_IN => PS_DATA_IN,
PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
- PS_RESPONSE_READY_OUT => resp_ready(4),
- PS_BUSY_OUT => busy(4),
- PS_SELECTED_IN => selected(4),
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
+ PS_RESPONSE_READY_OUT => resp_ready(3),
+ PS_BUSY_OUT => busy(3),
+ PS_SELECTED_IN => selected(3),
PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
- TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
-
- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32),
- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(4),
- STAT_DATA_ACK_IN => stat_ack(4),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
+ TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
+ TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16),
+
+ TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
+ TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
+ TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
+
+ STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
+ STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(3),
+ STAT_DATA_ACK_IN => stat_ack(3),
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
+ SENT_FRAMES_OUT => SENT_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
-- END OF INTERFACE
-- CTS interface
end if;
end process SELECT_MACHINE_PROC;
-SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index)
+SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros)
begin
case (select_current_state) is
when IDLE =>
- state <= x"1";
if (MC_BUSY_IN = '0') then
select_next_state <= LOOP_OVER;
else
end if;
when LOOP_OVER =>
- state <= x"2";
- if (or_all(resp_ready) = '1') then
+ if (resp_ready /= zeros) then
if (resp_ready(index) = '1') then
select_next_state <= SELECT_ONE;
elsif (index = c_MAX_PROTOCOLS) then
select_next_state <= CLEANUP;
+ else
+ select_next_state <= LOOP_OVER;
end if;
else
select_next_state <= CLEANUP;
- end if;
-
+ end if;
+
when SELECT_ONE =>
- state <= x"3";
if (MC_BUSY_IN = '1') then
select_next_state <= PROCESS_REQUEST;
else
end if;
when PROCESS_REQUEST =>
- state <= x"4";
if (MC_BUSY_IN = '0') then
select_next_state <= CLEANUP;
else
end if;
when CLEANUP =>
- state <= x"5";
select_next_state <= IDLE;
end case;
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_receive_control : architecture is "GBE_MAIN_group";
+attribute syn_encoding : string;
-type load_states is (IDLE, PREPARE, READY);
+type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
signal load_current_state, load_next_state : load_states;
+attribute syn_encoding of load_current_state : signal is "onehot";
signal frames_received_ctr : std_logic_vector(31 downto 0);
signal frames_readout_ctr : std_logic_vector(31 downto 0);
signal state : std_logic_vector(3 downto 0);
signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal reset_prioritizer : std_logic;
+signal frame_waiting : std_logic;
-- debug only
signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
protocol_prioritizer : trb_net16_gbe_protocol_prioritizer
port map(
- CLK => CLK,
- RESET => reset_prioritizer,
+ CLK => CLK,
+ RESET => reset_prioritizer,
FRAME_TYPE_IN => FR_FRAME_PROTO_IN,
PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN,
- CODE_OUT => proto_code
+ CODE_OUT => proto_code
);
reset_prioritizer <= '1' when load_current_state = IDLE else '0';
--RC_FRAME_PROTO_OUT <= proto_code when (and_all(proto_code) = '0') else (others => '0');
RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash
-DEBUG_OUT(3 downto 0) <= state;
-DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0);
-DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
-DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
+--DEBUG_OUT(3 downto 0) <= state;
+--DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0);
+--DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
+--DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
LOAD_MACHINE_PROC : process(CLK)
begin
when PREPARE => -- prepare frame size
state <= x"2";
- load_next_state <= READY;
+ load_next_state <= WAIT_ONE; --READY;
+
+ when WAIT_ONE =>
+ load_next_state <= READY;
when READY => -- wait for reading out the whole frame
state <= x"3";
end case;
end process LOAD_MACHINE;
-FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE)
- else '0';
-
-RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY)
- else '0';
-
-SYNC_PROC : process(CLK)
+process(CLK)
begin
- if rising_edge(CLK) then
- FRAMES_RECEIVED_OUT <= frames_received_ctr;
- --BYTES_RECEIVED_OUT <= bytes_rec_ctr;
- BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0);
- BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto;
- BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0');
- end if;
-end process SYNC_PROC;
+ if rising_edge(CLK) then
+ if (load_current_state = PREPARE) then
+ FR_GET_FRAME_OUT <= '1';
+ else
+ FR_GET_FRAME_OUT <= '0';
+ end if;
+
+ if (load_current_state = READY and RC_LOADING_DONE_IN = '0') then
+ RC_FRAME_WAITING_OUT <= '1';
+ else
+ RC_FRAME_WAITING_OUT <= '0';
+ end if;
+
+ --RC_FRAME_WAITING_OUT <= frame_waiting;
+ end if;
+end process;
+
+--FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE)
+-- else '0';
+--
+--RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY)
+-- else '0';
+
+--SYNC_PROC : process(CLK)
+--begin
+-- if rising_edge(CLK) then
+-- FRAMES_RECEIVED_OUT <= frames_received_ctr;
+-- --BYTES_RECEIVED_OUT <= bytes_rec_ctr;
+-- BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0);
+-- BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto;
+-- BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0');
+-- end if;
+--end process SYNC_PROC;
FRAMES_REC_CTR_PROC : process(CLK)
begin
end if;
end process FRAMES_READOUT_CTR_PROC;
+-- debug only
BYTES_REC_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process BYTES_REC_CTR_PROC;
--- debug only
SAVED_PROTO_PROC : process(CLK)
begin
if rising_edge(CLK) then
type dissect_states is (IDLE, READ_FRAME, DECIDE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
+attribute syn_encoding of dissect_current_state: signal is "onehot";
type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "safe,gray";
+attribute syn_encoding of stats_current_state : signal is "onehot";
+
signal saved_opcode : std_logic_vector(15 downto 0);
signal saved_sender_ip : std_logic_vector(31 downto 0);
signal saved_target_ip : std_logic_vector(31 downto 0);
elsif (dissect_current_state = READ_FRAME) then
case (data_ctr) is
- when 7 =>
+ when 6 =>
saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0);
- when 8 =>
+ when 7 =>
saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0);
- when 14 =>
+ when 13 =>
saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
- when 15 =>
+ when 14 =>
saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
- when 16 =>
+ when 15 =>
saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
- when 17 =>
+ when 16 =>
saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
- when 24 =>
+ when 23 =>
saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
- when 25 =>
+ when 24 =>
saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
- when 26 =>
+ when 25 =>
saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
- when 27 =>
+ when 26 =>
saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
when others => null;
type main_states is (BOOTING, SENDING_DISCOVER, WAITING_FOR_OFFER, SENDING_REQUEST, WAITING_FOR_ACK, ESTABLISHED);
signal main_current_state, main_next_state : main_states;
-attribute syn_encoding of main_current_state: signal is "safe,gray";
+attribute syn_encoding of main_current_state: signal is "onehot";
type receive_states is (IDLE, DISCARD, CLEANUP, SAVE_VALUES);
signal receive_current_state, receive_next_state : receive_states;
-attribute syn_encoding of receive_current_state: signal is "safe,gray";
+attribute syn_encoding of receive_current_state: signal is "onehot";
type discover_states is (IDLE, WAIT_FOR_LOAD, BOOTP_HEADERS, CLIENT_IP, YOUR_IP, ZEROS1, MY_MAC, ZEROS2, VENDOR_VALS, VENDOR_VALS2, TERMINATION, CLEANUP);
signal construct_current_state, construct_next_state : discover_states;
-attribute syn_encoding of construct_current_state: signal is "safe,gray";
+attribute syn_encoding of construct_current_state: signal is "onehot";
type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, LOAD_DISCARDED, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "safe,gray";
+attribute syn_encoding of stats_current_state : signal is "onehot";
signal state : std_logic_vector(3 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP);
signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
+attribute syn_encoding of dissect_current_state: signal is "onehot";
type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "safe,gray";
+attribute syn_encoding of stats_current_state : signal is "onehot";
signal rec_frames : std_logic_vector(15 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
--type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_A_WORD, WAIT_ONE, WAIT_TWO, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
--type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
+attribute syn_encoding of dissect_current_state: signal is "onehot";
type stats_states is (IDLE, LOAD_RECEIVED, LOAD_REPLY, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "safe,gray";
+attribute syn_encoding of stats_current_state : signal is "onehot";
signal saved_target_ip : std_logic_vector(31 downto 0);
signal data_ctr : integer range 0 to 30;
signal tc_wr : std_logic;
signal state : std_logic_vector(3 downto 0);
+signal saved_hdr_1 : std_logic_vector(7 downto 0) := x"ab";
+signal saved_hdr_2 : std_logic_vector(7 downto 0) := x"cd";
+signal saved_hdr_ctr : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
begin
if rising_edge(CLK) then
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then
rx_fifo_wr <= '1';
else
rx_fifo_wr <= '0';
end if;
end process RX_FIFO_WR_SYNC;
+SAVED_HDR_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then
+ saved_hdr_ctr <= "0001";
+ elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then
+ saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0';
+ else
+ saved_hdr_ctr <= saved_hdr_ctr;
+ end if;
+ end if;
+end process SAVED_HDR_CTR_PROC;
+
+SAVED_HDR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ if (saved_hdr_ctr = "0001") then
+ saved_hdr_1 <= PS_DATA_IN(7 downto 0);
+ saved_hdr_2 <= saved_hdr_2;
+ elsif (saved_hdr_ctr = "0010") then
+ saved_hdr_2 <= PS_DATA_IN(7 downto 0);
+ saved_hdr_1 <= saved_hdr_1;
+ else
+ saved_hdr_1 <= saved_hdr_1;
+ saved_hdr_2 <= saved_hdr_2;
+ end if;
+ else
+ saved_hdr_1 <= saved_hdr_1;
+ saved_hdr_2 <= saved_hdr_2;
+ end if;
+ end if;
+end process SAVED_HDR_PROC;
+
--RX_FIFO_RD_SYNC : process(CLK)
--begin
-- if rising_edge(CLK) then
if rising_edge(CLK) then
if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
tx_fifo_wr <= '1';
+ elsif (saved_hdr_ctr = "0010") then
+ tx_fifo_wr <= '1';
else
tx_fifo_wr <= '0';
end if;
- tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8);
- tx_fifo_data(8) <= '0';
- tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
- tx_fifo_data(17) <= '0';
+ if (saved_hdr_ctr = "010") then
+ tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02";
+ else
+ tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8);
+ tx_fifo_data(8) <= '0';
+ tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
+ tx_fifo_data(17) <= '0';
+ end if;
end if;
end process TX_FIFO_WR_SYNC;
end if;
end process TX_FIFO_SYNC_PROC;
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- tc_wr <= tx_fifo_rd;
---
--- TC_WR_EN_OUT <= tc_wr;
--- end if;
---end process TC_WR_PROC;
-
TC_DATA_PROC : process(CLK)
begin
if rising_edge(CLK) then
+
TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
--if (tx_loaded_ctr = tx_data_ctr + x"1" or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
begin
if rising_edge(CLK) then
if (RESET = '1' or dissect_current_state = IDLE) then
- tx_loaded_ctr <= (others => '0');
- --elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and (tx_frame_loaded /= g_MAX_FRAME_SIZE)) then -- TODO: change this to real wr signal
+ tx_loaded_ctr <= x"0000";
elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then
tx_loaded_ctr <= tx_loaded_ctr + x"1";
end if;
TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);
TC_SRC_MAC_OUT <= g_MY_MAC;
TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"a861";
+TC_SRC_UDP_OUT <= x"9065"; --x"a861";
TC_IP_PROTOCOL_OUT <= x"11";
TC_IDENT_OUT <= x"3" & reply_ctr(11 downto 0);
when WAIT_FOR_HUB =>
state <= x"5";
if (GSC_INIT_READ_IN = '1') then
--- if (rx_fifo_q(17) = '1') then
--- if (reset_detected = '0') then
--- dissect_next_state <= WAIT_FOR_RESPONSE;
--- else
--- dissect_next_state <= CLEANUP;
--- end if;
--- else
--- dissect_next_state <= LOAD_A_WORD;
--- end if;
dissect_next_state <= LOAD_TO_HUB;
else
dissect_next_state <= WAIT_FOR_HUB;
else
dissect_next_state <= WAIT_FOR_LOAD;
end if;
-
+
when LOAD_FRAME =>
state <= x"9";
if (tx_loaded_ctr = tx_data_ctr) then
else
dissect_next_state <= LOAD_FRAME;
end if;
--- if (tx_loaded_ctr = tx_data_ctr + x"1") then
--- dissect_next_state <= CLEANUP;
--- elsif (tx_frame_loaded = g_MAX_FRAME_SIZE) then
--- dissect_next_state <= DIVIDE;
--- else
--- dissect_next_state <= LOAD_FRAME;
--- end if;
-
--- when DIVIDE =>
--- state <= x"a";
--- if (PS_SELECTED_IN = '1') then
--- dissect_next_state <= LOAD_FRAME;
--- else
--- dissect_next_state <= DIVIDE;
--- end if;
when CLEANUP =>
state <= x"b";
dissect_next_state <= IDLE;
-
--- when others =>
--- state <= x"f";
--- dissect_next_state <= IDLE;
end case;
end process DISSECT_MACHINE;
-- reset request packet detection
-RESET_DETECTED_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1' or dissect_current_state = CLEANUP) then
- reset_detected <= '0';
- elsif (PS_DATA_IN(7 downto 0) = x"80" and dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- first byte as 0x80
- reset_detected <= '1';
- end if;
- end if;
-end process RESET_DETECTED_PROC;
-
-MAKE_RESET_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- make_reset <= '0';
- elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
- make_reset <= '1';
- end if;
- end if;
-end process MAKE_RESET_PROC;
+ RESET_DETECTED_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = CLEANUP) then
+ reset_detected <= '0';
+ elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then--and dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- first byte as 0x80
+ reset_detected <= '1';
+ end if;
+ end if;
+ end process RESET_DETECTED_PROC;
+
+ MAKE_RESET_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ make_reset <= '0';
+ elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
+ make_reset <= '1';
+ end if;
+ end if;
+ end process MAKE_RESET_PROC;
---- end of statistics
--
---- **** debug
-DEBUG_OUT(3 downto 0) <= state;
+--DEBUG_OUT(3 downto 0) <= state;
--DEBUG_OUT(4) <= '0';
--DEBUG_OUT(7 downto 5) <= "000";
--DEBUG_OUT(8) <= '0';
architecture trb_net16_gbe_response_constructor_TrbNetData of trb_net16_gbe_response_constructor_TrbNetData is
+attribute syn_encoding : string;
+
signal ip_cfg_start : std_logic;
signal ip_cfg_bank : std_logic_vector(3 downto 0);
signal ip_cfg_done : std_logic;
signal tc_data : std_logic_vector(8 downto 0);
signal tc_size : std_logic_vector(15 downto 0);
signal tc_sod : std_logic;
+signal pc_trig_type : std_logic_vector(3 downto 0);
type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP);
signal dissect_current_state, dissect_next_state : dissect_states;
+attribute syn_encoding of dissect_current_state : signal is "onehot";
+
signal event_bytes : std_logic_vector(15 downto 0);
signal loaded_bytes : std_logic_vector(15 downto 0);
signal sent_packets : std_logic_vector(15 downto 0);
PC_EOD_OUT => pc_eod,
PC_SUB_SIZE_OUT => pc_sub_size,
PC_TRIG_NR_OUT => pc_trig_nr,
+ PC_TRIGGER_TYPE_OUT => pc_trig_type,
PC_PADDING_OUT => pc_padding,
MONITOR_OUT => open,
DEBUG_OUT => open
PC_DECODING_IN => x"0002_0001", --pc_decoding,
PC_EVENT_ID_IN => x"0000_8000", --pc_event_id,
PC_TRIG_NR_IN => pc_trig_nr,
+ PC_TRIGGER_TYPE_IN => pc_trig_type,
PC_QUEUE_DEC_IN => x"0003_0062", --pc_queue_dec,
PC_MAX_FRAME_SIZE_IN => g_MAX_FRAME_SIZE,
PC_MAX_QUEUE_SIZE_IN => x"0000_0fd0",
architecture trb_net16_gbe_transmit_control2 of trb_net16_gbe_transmit_control2 is
+attribute syn_encoding : string;
+
type transmit_states is (IDLE, PREPARE_HEADERS, WAIT_FOR_H, TRANSMIT, SEND_ONE, SEND_TWO, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP);
signal transmit_current_state, transmit_next_state : transmit_states;
+attribute syn_encoding of transmit_current_state : signal is "onehot";
signal tc_rd, tc_rd_q, tc_rd_qq : std_logic;
signal local_end : std_logic_vector(15 downto 0);
signal ip_result : std_logic_vector(c_MAX_IP_PROTOCOLS - 1 downto 0);
signal udp_result : std_logic_vector(c_MAX_UDP_PROTOCOLS - 1 downto 0);
signal partially_valid : std_logic; -- only protocols, vlan to be checked
+signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0);
begin
-- DO NOT TOUCH
IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate
- ip_result(i) <= '1' when (
- IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and
- ALLOWED_IP_PROTOCOLS_IN(i) = '1'
- ) else '0';
-
-
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and ALLOWED_IP_PROTOCOLS_IN(i) = '1' then
+ ip_result(i) <= '1';
+ else
+ ip_result(i) <= '0';
+ end if;
+ end if;
+end process;
+-- ip_result(i) <= '1' when (
+-- IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and
+-- ALLOWED_IP_PROTOCOLS_IN(i) = '1'
+-- ) else '0';
end generate IP_RESULTS_GEN;
UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate
-
- udp_result(i) <= '1' when (
- UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and
- ALLOWED_UDP_PROTOCOLS_IN(i) = '1'
- ) else '0';
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and ALLOWED_UDP_PROTOCOLS_IN(i) = '1' then
+ udp_result(i) <= '1';
+ else
+ udp_result(i) <= '0';
+ end if;
+ end if;
+end process;
+-- udp_result(i) <= '1' when (
+-- UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and
+-- ALLOWED_UDP_PROTOCOLS_IN(i) = '1'
+-- ) else '0';
end generate UDP_RESULTS_GEN;
RESULT_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate
-
- result(i) <= '1' when (
- FRAME_TYPES(i) = FRAME_TYPE_IN and
- ALLOWED_TYPES_IN(i) = '1'
- ) else '0';
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if FRAME_TYPES(i) = FRAME_TYPE_IN and ALLOWED_TYPES_IN(i) = '1' then
+ result(i) <= '1';
+ else
+ result(i) <= '0';
+ end if;
+ end if;
+end process;
+-- result(i) <= '1' when (
+-- FRAME_TYPES(i) = FRAME_TYPE_IN and
+-- ALLOWED_TYPES_IN(i) = '1'
+-- ) else '0';
end generate RESULT_GEN;
else -- do not accept other protocols than udp and icmp inside ip
partially_valid <= '0';
end if;
- else -- other frame
- partially_valid <= or_all(result);
+ elsif (result /= zeros) then-- other frame
+ partially_valid <= '1'; --or_all(result);
+ else
+ partially_valid <= '0';
end if;
end if;
end process PARTIALLY_VALID_PROC;
-VALID_OUT_PROC : process(partially_valid, SAVED_VLAN_ID_IN, VLAN_ID_IN)
+VALID_OUT_PROC : process(CLK) --partially_valid, SAVED_VLAN_ID_IN, VLAN_ID_IN)
begin
- --if rising_edge(CLK) then
+ if rising_edge(CLK) then
-- if (RESET = '1') then
-- VALID_OUT <= '0';
if (partially_valid = '1') then
else
VALID_OUT <= '0';
end if;
- --end if;
+ end if;
end process VALID_OUT_PROC;
--if rising_edge(CLK) then
-- );\r
-- end component;\r
\r
-component sgmii_gbe_pcs36 -- sgmii_gbe_pcs35\r
+component sgmii_gbe_pcs35 --sgmii_gbe_pcs36 -- sgmii_gbe_pcs35\r
port( rst_n : in std_logic;\r
signal_detect : in std_logic;\r
gbe_mode : in std_logic;\r
\r
\r
\r
- SGMII_GBE_PCS : sgmii_gbe_pcs36 --sgmii_gbe_pcs35\r
+ SGMII_GBE_PCS : sgmii_gbe_pcs35 --sgmii_gbe_pcs36 --sgmii_gbe_pcs35\r
port map(\r
rst_n => GSR_N,\r
signal_detect => signal_detected,\r
PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
+ PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
PC_MAX_QUEUE_SIZE_IN : in std_logic_vector(31 downto 0);
PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
PC_PADDING_OUT : out std_logic;
+ PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0);
MONITOR_OUT : out std_logic_vector(223 downto 0);
DEBUG_OUT : out std_logic_vector(383 downto 0)
);
Q: out std_logic_vector(7 downto 0));
end component;
-component slv_mac_memory is
-port(
- CLK : in std_logic;
- RESET : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- MEM_CLK_IN : in std_logic;
- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
-);
-end component;
+--component slv_mac_memory is
+--port(
+-- CLK : in std_logic;
+-- RESET : in std_logic;
+-- BUSY_IN : in std_logic;
+-- -- Slave bus
+-- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+-- SLV_READ_IN : in std_logic;
+-- SLV_WRITE_IN : in std_logic;
+-- SLV_BUSY_OUT : out std_logic;
+-- SLV_ACK_OUT : out std_logic;
+-- SLV_DATA_IN : in std_logic_vector(31 downto 0);
+-- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+-- -- I/O to the backend
+-- MEM_CLK_IN : in std_logic;
+-- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
+-- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
+-- -- Status lines
+-- STAT : out std_logic_vector(31 downto 0) -- DEBUG
+--);
+--end component;
component fifo_32kx16x8_mb2
port(
--signal g_MAX_PACKET_SIZE : std_logic_vector(15 downto 0);
constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
-constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5; --4; --5;
+constant c_MAX_PROTOCOLS : integer range 1 to 16 := 4; --5; --4; --5;
constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4;
-- this are the destination ports of the incoming packet
type udp_protos_a is array(c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0);
-constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"61a8", x"7530", x"7531");
+constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531");
-- DHCP client, SCTRL, STATs
component trb_net16_gbe_response_constructor_Forward is
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