fix asserts for buffer sizes

diff --git a/special/handler_data.vhd b/special/handler_data.vhd
index 13a9b21e8a14dc08d769dfaa8f750583bdbc7954..e99639a66e2c6837cf40a21ecb3142c6b50e2886 100644 (file)
--- a/special/handler_data.vhd
+++ b/special/handler_data.vhd
@@ -150,7 +150,7 @@ architecture handler_data_arch of handler_data is
   signal fee_write_overflow        : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
 begin
 
-  assert DATA_BUFFER_FULL_THRESH < 2**DATA_BUFFER_DEPTH-2     report "Data buffer threshold too high" severity error;
+  assert DATA_BUFFER_FULL_THRESH >= (2**DATA_BUFFER_DEPTH)/2     report "Data buffer threshold too high" severity error;
   assert HEADER_BUFFER_FULL_THRESH < 2**HEADER_BUFFER_DEPTH-2 report "Header buffer threshold too high" severity error;
 
 ---------------------------------------------------------------------------

diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd
index d86f376c3573cdabfbb83c02913ffbbfb6ac2c6a..e3abd807a8eee8e32bd3eaef1686dd61ab0e8236 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_cts.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd
@@ -71,7 +71,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is
     INIT_CTRL_REGS          : std_logic_vector(2**(4)*32-1 downto 0) :=
                                          x"00000000_00000000_00000000_00000000" &
                                          x"00000000_00000000_00000000_00000000" &
-                                         x"00000000_00000000_00003077_00000000" &
+                                         x"00000000_00000000_000050FF_00000000" &
                                          x"FFFFFFFF_00000000_FFFFFFFF_FFFFFFFF"    
     );
 

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 0777d40b38f683ade66bacb27ecb387dc6c8f660..92ec0259876f8cdee815fdaf31740a09137c10aa 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -101,9 +101,9 @@ end entity;
 architecture trb_net16_regIO_arch of trb_net16_regIO is
 
   -- Placer Directives
-  attribute HGROUP : string;
+--   attribute HGROUP : string;
   -- for whole architecture
-  attribute HGROUP of trb_net16_regIO_arch : architecture  is "RegIO_group";
+--   attribute HGROUP of trb_net16_regIO_arch : architecture  is "RegIO_group";
 
   constant COMPILE_TIME_LIB : std_logic_vector(31 downto 0) := conv_std_logic_vector(VERSION_NUMBER_TIME,32);