brought 4-conn-addon (padiwa) project up-to-date

diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf
index 212e83bd908738b581bfc4af0b82b56e32c0154e..fba1f2a0243b663a1c882b7fd3696792d4795e7c 100644 (file)
--- a/base/trb3_periph_padiwa.lpf
+++ b/base/trb3_periph_padiwa.lpf
@@ -12,8 +12,8 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ;
-MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_internal_c" 2 X ;
+MULTICYCLE FROM CLKNET "clk_100_internal" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal" 2 X ;
 
 LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
 

diff --git a/wasa/config.vhd b/wasa/config.vhd
index 0bef662b91a1eded22a6f54e91ac5d36e5b274aa..171c07d2e52a19814dedfa32e799d11e6602caf4 100644 (file)
--- a/wasa/config.vhd
+++ b/wasa/config.vhd
@@ -12,8 +12,8 @@ package config is
 
 --TDC settings
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 49; -- number of tdc channels per module
-  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 65; -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 6;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,

diff --git a/wasa/currentRelease b/wasa/currentRelease
index 02a0ff9ca11f00331804ea34e7ccebad0f0f4713..b10de14e146095a43d6d81d32a41c5e48873e51d 120000 (symlink)
--- a/wasa/currentRelease
+++ b/wasa/currentRelease
@@ -1 +1 @@
-../tdc_releases/tdc_v2.1.1
\ No newline at end of file
+../../tdc/releases/tdc_v2.1.2
\ No newline at end of file

diff --git a/wasa/tdc_release b/wasa/tdc_release
index 02a0ff9ca11f00331804ea34e7ccebad0f0f4713..b10de14e146095a43d6d81d32a41c5e48873e51d 120000 (symlink)
--- a/wasa/tdc_release
+++ b/wasa/tdc_release
@@ -1 +1 @@
-../tdc_releases/tdc_v2.1.1
\ No newline at end of file
+../../tdc/releases/tdc_v2.1.2
\ No newline at end of file

diff --git a/wasa/unimportant_lines_constraints.lpf b/wasa/unimportant_lines_constraints.lpf
index 0c65598cc830b0c7ae1cb9803565ec46b65f55bc..b9b6e80237477450513e9d1e5aad09a5e05e6a95 100644 (file)
--- a/wasa/unimportant_lines_constraints.lpf
+++ b/wasa/unimportant_lines_constraints.lpf
@@ -1,4 +1,4 @@
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
+MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
 
-# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_internal TO CLKNET clk_100_internal 5x;