small correction to feature maps

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index 8d4f082ee9075a38fe3ecd952315f1f797be2631..cc5bd999bb3f14943d6113d8e5ab108730a3ec37 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -18,6 +18,7 @@ CTS registers. \\
  & 22       & GbeMultBuf  & GbE sctrl data can be split to multiple packets\\
  
  & 26 -- 24 & Sfp         & Number of SFP configured for TrbNet connections\\
+ & 42       & Spi         & Contains SPI on all relevant I/Os depending on AddOn board design\\
  & 43       & Uart        & Uart on RJ45\_CLOCK(4) (TTL)\\
  & 47 -- 44 & InpMonitor  & Monitoring of input signals. See register 0xcf8f for number of channels and number of fifos 
 \\
@@ -31,7 +32,9 @@ CTS registers. \\
 1-to-1, 2: every second input (e.g. Padiwa Amps fast-only), 3: every fourth input (HPTDC very high speed mode)\\
  & 11 -- 8  & DoubleEdge  & Double edge setup: 0: single edge only, 1: same channel, 2: alternating channels, 3: same 
 channel with stretcher \\
+ & 15       & TDC         & Contains a TDC \\
  & 42       & Spi         & Contains SPI on all relevant I/Os depending on AddOn board design\\
+ & 43       & Uart        & Contains an Uart\\
  & 47 -- 44 & InpMonitor  & See table 1. Pinout should match the one of the TDC\\
  & 51 -- 48 & TrgModule   & See table 1. Pinout should match the one of the TDC\\
  & 55 -- 52 & Clock       & See table 1\\

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 571b2af1bf02de68995cd451f835319189c01515..37c49e7aacce076170dc26c11d093f8700c360d3 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -78,13 +78,13 @@ register should only be used to describe hardware-related features, like the nee
 \begin{description*}
   \item[cXX0]  contains a CTS
   \item[cXX1]  contains a CTS, use with AddOn for trigger signals
-  \item[8XXX]  uses RX clock as main internal clock
-  \item[0e00]  contains a GbE link for slow control and read-out
-  \item[0d00]  contains a GbE link for read-out only
-  \item[0010]  accepts triggers from optical link SFP1
-  \item[0020]  accepts slow-control from optical link SFP1
-  \item[0040]  sends triggers to optical link SFP1
-  \item[0080]  sends slow-control to optical link SFP1
+  \item[8XXX]  {\color{darkgray}uses RX clock as main internal clock}
+  \item[0e00]  {\color{darkgray}contains a GbE link for slow control and read-out}
+  \item[0d00]  {\color{darkgray}contains a GbE link for read-out only}
+  \item[0010]  {\color{darkgray}accepts triggers from optical link SFP1}
+  \item[0020]  {\color{darkgray}accepts slow-control from optical link SFP1}
+  \item[0040]  {\color{darkgray}sends triggers to optical link SFP1}
+  \item[0080]  {\color{darkgray}sends slow-control to optical link SFP1}
 \end{description*}
 \item[Peripheral FPGA (also CBM-RICH and other derivates)]~
 \begin{description*}