------------------------------------
--X unused, / error+parity, + data
------------------------------------
---D16 data structure
--- 0+++++++1+++++++ 00
--- 2+++++++3+++++++ 01
--- 4+++++++5+++++++ 10
--- 6+++++++//////// 11
------------------------------------
-- Status and control port
STAT_BUFFER: out STD_LOGIC
);
- END component;
+ end component;
signal dbuf18_comb_dataready_in : std_logic;
signal dbuf18_next_read_out : std_logic;
--Direction 18 to 55
-----------------------------------------------------------
- D18to55_fsm : process(D55_READ_IN, buf_D55_DATAREADY_OUT, D18_READ_IN, D18_DATAREADY_IN,
+ D18to55_fsm : process(D55_READ_IN, buf_D55_DATAREADY_OUT, buf_D18_READ_OUT, D18_DATAREADY_IN,
D18to55_state, buf_D55_DATA_OUT, D18_DATA_IN)
variable dataisread18, dataisread55 : std_logic;
begin
next_D55_DATA_OUT <= buf_D55_DATA_OUT;
next_D18to55_state <= D18to55_state;
next_D18_READ_OUT <= '1';
+ next_D55_DATAREADY_OUT <= '0';
- if(D55_READ_IN = '1' AND buf_D55_DATAREADY_OUT = '1') then
- dataisread55 := '1';
- else
- dataisread55 := '0';
- end if;
-
- if(D18_READ_IN = '1' AND D18_DATAREADY_IN = '1') then
- dataisread18 := '1';
- else
- dataisread18 := '0';
- end if;
-
- if(dataisread55 = '1') then
- next_D55_DATAREADY_OUT <= '0';
- else
- next_D55_DATAREADY_OUT <= buf_D55_DATAREADY_OUT;
- end if;
+ dataisread55 := D55_READ_IN AND buf_D55_DATAREADY_OUT;
+ dataisread18 := buf_D18_READ_OUT AND D18_DATAREADY_IN;
case D18to55_state is
when IDLE =>
- next_D18_READ_OUT <= '1';
if(dataisread18 = '1') then
next_D55_DATA_OUT(55 downto 48) <= D18_DATA_IN(7 downto 0);
next_D18to55_state <= FIRST;
next_D18to55_state <= IDLE;
else
next_D18_READ_OUT <= '0';
+ next_D55_DATAREADY_OUT <= '1';
end if;
end case;
end process;
begin
if rising_edge(CLK) then
if RESET = '1' then
- buf_D55_DATA_OUT <= (others => '0');
- D18to55_state <= IDLE;
+ buf_D55_DATA_OUT <= (others => '0');
+ D18to55_state <= IDLE;
buf_D55_DATAREADY_OUT <= '0';
- buf_D18_READ_OUT <= '0';
+ buf_D18_READ_OUT <= '0';
else
- buf_D55_DATA_OUT <= next_D55_DATA_OUT;
- D18to55_state <= next_D18to55_state;
+ buf_D55_DATA_OUT <= next_D55_DATA_OUT;
+ D18to55_state <= next_D18to55_state;
buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT;
- buf_D18_READ_OUT <= next_D18_READ_OUT;
+ buf_D18_READ_OUT <= next_D18_READ_OUT;
end if;
- else
- buf_D55_DATA_OUT <= buf_D55_DATA_OUT;
- D18to55_state <= D18to55_state;
- buf_D55_DATAREADY_OUT <= buf_D55_DATAREADY_OUT;
- buf_D18_READ_OUT <= buf_D18_READ_OUT;
end if;
end process;
D55to18_fsm : process(buf_D18_DATA_OUT, buf_D18_PACKET_NUM_OUT, buf_D18_DATAREADY_OUT,
D18_READ_IN, D55_DATA_IN, D55_DATAREADY_IN, D55to18_state,
buf_D55_READ_OUT, buf_D55_DATA_IN, dataread55)
- variable dataisread : std_logic;
+ variable dataisread18, dataisread55 : std_logic;
begin
next_D18_DATA_OUT <= buf_D18_DATA_OUT;
next_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
next_D55to18_state <= D55to18_state;
next_D55_READ_OUT <= '0';
next_buf_D55_DATA_IN <= buf_D55_DATA_IN;
- next_dataread55 <= dataread55;
-
- if(D18_READ_IN = '1' AND buf_D18_DATAREADY_OUT = '1') then
- dataisread := '1';
- else
- dataisread := '0';
- end if;
+ dataisread18 := D18_READ_IN AND buf_D18_DATAREADY_OUT;
+ dataisread55 := D55_DATAREADY_IN AND buf_D55_READ_OUT;
- if(dataisread = '1') then
+ if(dataisread18 = '1') then
next_D18_DATAREADY_OUT <= '0';
else
next_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT;
case D55to18_state is
when IDLE =>
- --data available?
- if (D55_DATAREADY_IN = '1' AND buf_D55_READ_OUT = '1') then
- next_buf_D55_DATA_IN(55 downto 0) <= D55_DATA_IN(55 downto 0);
- next_D55_READ_OUT <= '0';
- --data available and ready to write
- if (dataisread = '1' OR buf_D18_DATAREADY_OUT = '0') then
+ if (dataisread18 = '1' OR buf_D18_DATAREADY_OUT = '0') then
+ next_D55_READ_OUT <= '1';
+ if dataisread55 = '1' then
+ next_buf_D55_DATA_IN(55 downto 0) <= D55_DATA_IN(55 downto 0);
+ next_D55_READ_OUT <= '0';
next_D18_DATA_OUT(7 downto 0) <= D55_DATA_IN(55 downto 48);
next_D18_DATA_OUT(15 downto 8) <= (others => '0');
next_D18_PACKET_NUM_OUT <= "00";
next_D18_DATAREADY_OUT <= '1';
next_D55to18_state <= FIRST;
- --data available but not ready to write
- else
- next_dataread55 <= '1';
end if;
- --data available before, now ready to write
- elsif dataisread = '1' and dataread55 = '1' then
- next_dataread55 <= '0';
- next_D18_DATA_OUT(7 downto 0) <= buf_D55_DATA_IN(55 downto 48);
- next_D18_DATA_OUT(15 downto 8) <= (others => '0');
- next_D18_PACKET_NUM_OUT <= "00";
- next_D18_DATAREADY_OUT <= '1';
- next_D55to18_state <= FIRST;
- --no data available
- elsif dataread55 = '0' then
- next_buf_D55_DATA_IN(55 downto 0) <= (others => '0');
- next_D55_READ_OUT <= '1';
end if;
-
when FIRST =>
- if(dataisread = '1') then
+ if(dataisread18 = '1') then
next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(47 downto 32);
next_D18_DATAREADY_OUT <= '1';
next_D18_PACKET_NUM_OUT <= "01";
next_D55to18_state <= SECOND;
end if;
when SECOND =>
- if(dataisread = '1') then
+ if(dataisread18 = '1') then
next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(31 downto 16);
next_D18_DATAREADY_OUT <= '1';
next_D18_PACKET_NUM_OUT <= "10";
next_D55to18_state <= THIRD;
end if;
when THIRD =>
- if(dataisread = '1') then
+ if(dataisread18 = '1') then
next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(15 downto 0);
next_D18_DATAREADY_OUT <= '1';
next_D18_PACKET_NUM_OUT <= "11";
next_D55to18_state <= IDLE;
next_D55_READ_OUT <= '1';
end if;
- when LAST =>
--- if(dataisread = '1') then
--- next_D18_DATA_OUT(15 downto 0) <= (others => '0');
--- next_D18_DATAREADY_OUT <= '0';
+ when others =>
next_D55to18_state <= IDLE;
--- next_D18_PACKET_NUM_OUT <= "00";
--- next_D55_READ_OUT <= '1';
--- end if;
end case;
end process;
buf_D18_DATAREADY_OUT <= '0';
buf_D18_PACKET_NUM_OUT <= "00";
D55to18_state <= IDLE;
- dataread55 <= '0';
else
buf_D18_DATA_OUT <= next_D18_DATA_OUT;
buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT;
buf_D55_DATA_IN <= next_buf_D55_DATA_IN;
buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT;
D55to18_state <= next_D55to18_state;
- dataread55 <= next_dataread55;
end if;
- else
- buf_D18_DATA_OUT <= buf_D18_DATA_OUT;
- buf_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT;
- buf_D55_READ_OUT <= buf_D55_READ_OUT;
- buf_D55_DATA_IN <= buf_D55_DATA_IN;
- buf_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
- D55to18_state <= D55to18_state;
- dataread55 <= dataread55;
end if;
end process;
STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
API_STAT_LOCKED: out std_logic_vector(31 downto 0);
API_STAT_INIT_BUFFER: out std_logic_vector(31 downto 0);
API_STAT_REPLY_BUFFER: out std_logic_vector(31 downto 0);
+ API_STAT_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0);
LVDS_STAT: out std_logic_vector(31 downto 0);
STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
signal API_MED_READ_OUT : std_logic;
signal API_MED_ERROR_OUT : std_logic_vector(2 downto 0);
signal API_ctrl : std_logic_vector(31 downto 0);
- --signal API_STAT_FIFO_TO_INT, API_STAT_FIFO_TO_APL : std_logic_vector(31 downto 0);
signal C5518_D55_DATA_IN, C5518_D55_DATA_OUT : std_logic_vector(55 downto 0);
-----------------------------------------------------------------------
CTRL => LVDS_CTRL
);
- LVDS_OUT(10 downto 0) <= LVDS_MED_DATA_OUT(10 downto 0);
+ LVDS_OUT(7 downto 0) <= LVDS_MED_DATA_OUT(7 downto 0);
+ LVDS_OUT(10) <= C5518_D55_DATA_OUT(48);
+ LVDS_OUT(9) <= LVDS_INT_DATA_OUT(0);
+ LVDS_OUT(8) <= LVDS_INT_DATAREADY_OUT;
LVDS_OUT(11) <= LVDS_MED_DATA_OUT(11) and not API_RESET;
LVDS_OUT(12) <= LVDS_MED_DATA_OUT(12);
LVDS_OUT(13) <= LVDS_MED_TRANSMISSION_CLK_OUT;
STAT_LOCKED => API_STAT_LOCKED,
STAT_INIT_BUFFER => API_STAT_INIT_BUFFER,
STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER,
-
+ STAT_api_control_signals => API_STAT_control_signals,
+ STAT_MPLEX => STAT_MPLEX,
STAT_CTRL_INIT_BUFFER => (others => '0'),
STAT_CTRL_REPLY_BUFFER => (others => '0'),
MPLEX_CTRL => MPLEX_CTRL,
STAT_LOCKED => API_STAT_LOCKED,
STAT_INIT_BUFFER => API_STAT_INIT_BUFFER,
STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER,
+ STAT_api_control_signals => API_STAT_control_signals,
+ STAT_MPLEX => STAT_MPLEX,
STAT_CTRL_INIT_BUFFER => (others => '0'),
STAT_CTRL_REPLY_BUFFER => (others => '0'),
MPLEX_CTRL => MPLEX_CTRL,
component trb_net_sbuf is
generic (DATA_WIDTH : integer := 56;
- VERSION: integer := 1);
+ VERSION: integer := 0);
port(
-- Misc
fifo_data_in <= MED_DATA_IN;
-- this process controls the writing of the media into the fifo
- FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN,
+ FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN,
fifo_full, is_locked, current_rec_buffer_size_out,
current_error_state, reg_read_out)
begin -- process
if MED_DATAREADY_IN = '1' and reg_read_out= '1' then
if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then
- -- BUGBUG: this causes trouble if the IBUF is full
+ -- BUGBUG: this causes trouble if the IBUF is full -> ack sent even if buffer overflow
got_ack_internal <= '1';
if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then
next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION);
end if;
end process;
- MED_READ_OUT <= reg_read_out;
+ MED_READ_OUT <= reg_read_out;
-reg_buffer: process(CLK)
+ reg_buffer: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => 51)
+ generic map (DATA_WIDTH => 51, Version => 0)
port map (
CLK => CLK,
RESET => RESET,
end if;
end process;
- STAT_BUFFER(31 downto 12) <= (others => '0');
+ STAT_BUFFER(31 downto 12) <= (others => '0');
end trb_net_ibuf_arch;
CTRL: in STD_LOGIC_VECTOR (31 downto 0);
STAT: out STD_LOGIC_VECTOR (31 downto 0)
);
-END trb_net_io_multiplexer;
+end trb_net_io_multiplexer;
architecture trb_net_io_multiplexer_arch of trb_net_io_multiplexer is
INPUT_IN : in STD_LOGIC_VECTOR (MULT_WIDTH-1 downto 0);
RESULT_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0)
);
- END component;
+ end component;
component trb_net_sbuf is
-- Status and control port
STAT_BUFFER: out STD_LOGIC
);
- END component;
+ end component;
component trb_net_priority_arbiter is
ENABLE : in std_logic;
CTRL: in STD_LOGIC_VECTOR (31 downto 0)
);
- END component;
+ end component;
signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
signal next_demux_dr, next_demux_dr_tmp: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
-------------------------------------------------------------------------------
-- DEMUX
-------------------------------------------------------------------------------
+------------------------------------------------------------------------------
-- the simpler part is the demux
G1: for i in 0 to 2**MULT_WIDTH-1 generate
DEMUX_SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH, VERSION => 1)
+ generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH, VERSION => 0)
port map (
CLK => CLK,
RESET => RESET,
);
end generate;
+ STAT(2 downto 0) <= MED_DATA_IN(50 downto 48);
+
MED_READ_OUT <= current_MED_READ_OUT;
comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN,
MUX_SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => BUS_WIDTH, VERSION => 1)
+ generic map (DATA_WIDTH => BUS_WIDTH, VERSION => 0)
port map (
CLK => CLK,
RESET => RESET,
-- Status and control port
STAT_BUFFER: out STD_LOGIC
);
- END component;
+ end component;
component FDDRCPE
port (
component trb_net_sbuf is
generic (DATA_WIDTH : integer := 56;
- VERSION : integer := 1);
+ VERSION : integer := 0);
port(
-- Misc
begin
SBUF: trb_net_sbuf
- generic map (DATA_WIDTH => 51, VERSION => 1)
+ generic map (DATA_WIDTH => 51, VERSION => 0)
port map (
CLK => CLK,
RESET => RESET,
-- increase and decrease transmitted buffers
- comb_TRANSMITTED_BUFFERS : process (increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS,TRANSMITTED_BUFFERS)
+ comb_TRANSMITTED_BUFFERS : process (increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS)
begin
if (increase_TRANSMITTED_BUFFERS = '1' and decrease_TRANSMITTED_BUFFERS = '0') then
next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS +1;
APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL_Send_IN: in STD_LOGIC; -- Release sending of the data
APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
-- the target (only for active APIs)
STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0);
CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
);
-END component;
+end component;
component trb_net_passive_api is
APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL_Send_IN: in STD_LOGIC; -- Release sending of the data
APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
-- the target (only for active APIs)
STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
);
-END component;
+end component;
component trb_net_io_multiplexer is
CTRL: in STD_LOGIC_VECTOR (31 downto 0);
STAT: out STD_LOGIC_VECTOR (31 downto 0)
);
-END component;
+end component;
signal apl_to_buf_INIT_DATAREADY: STD_LOGIC;
signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
APL_DTYPE_IN => APL_DTYPE_IN,
APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
+ APL_Send_IN => APL_Send_IN,
APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
-- Receiver port
STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
STAT_api_control_signals(3) <= APL_WRITE_IN;
-STAT_api_control_signals(4) <= APL_SEND_IN;
+STAT_api_control_signals(4) <= APL_Send_IN;
STAT_api_control_signals(7 downto 5) <= (others => '0');
STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
-STAT_api_control_signals(31 downto 13) <= (others => '0');
+STAT_api_control_signals(13) <= MED_INIT_DATAREADY_IN;
+STAT_api_control_signals(14) <= MED_REPLY_DATAREADY_IN;
+STAT_api_control_signals(15) <= MED_REPLY_DATA_IN(48);
+STAT_api_control_signals(16) <= MED_REPLY_DATA_IN(50);
+
+STAT_api_control_signals(31 downto 17) <= (others => '0');
INT_DATA_IN =>m_DATA_OUT,
INT_READ_OUT =>m_READ_IN,
- CTRL => MPLEX_CTRL
+ CTRL => MPLEX_CTRL,
+ STAT => STAT_MPLEX
);
use work.trb_net_std.all;
---Entity decalaration for clock generator
entity trb_net_pattern_gen is
generic (MULT_WIDTH : integer := 3);
jspc29 / trbnet.git / commitdiff