--- /dev/null
+version.vhd
+*.log
+*~
+.kateproject.d
+workdir
--- /dev/null
+{
+ "name": "Pexor"
+, "files": [ { "git": 1 } ]
+}
use warnings;
use strict;
+###################################################################################
+#Settings for this project
+my $TOPNAME = "pexor"; #Name of top-level entity
+my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64';
+#my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
+#my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+#my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
+my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+###################################################################################
-my $lattice_path = '/d/jspc29/lattice/diamond/1.4';
-my $synplify_path = '/d/jspc29/lattice/synplify/D-2010.03/';
use FileHandle;
$ENV{'SYNPLIFY'}=$synplify_path;
$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}="27000\@localhost";
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-my $TOPNAME="pexor";
-
my $FAMILYNAME="LatticeSCM";
my $DEVICENAME="LFSCM3GA40EP1";
my $PACKAGE="FFBGA1020";
}
#if (0){
-$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
execute($c);
my $tpmap = $TOPNAME . "_map" ;
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
execute($c);
#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
+
execute($c);
# IOR IO Timing Report
-n 1
-y
-s 12
--t 13
+-t 14
-c 1
-e 2
-m nodelist.txt
--- /dev/null
+-rem
+-distrce
+-log "pexor.log"
+-o "pexor.csv"
+-pr "pexor.prf"
add_file -vhdl -lib work "design/dma_core.vhd"
-add_file -verilog "/d/sugar/lattice/diamond/1.1/cae_library/synthesis/verilog/scm.v"
+add_file -verilog "/d/jspc29/lattice/diamond/2.1_x64/cae_library/synthesis/verilog/scm.v"
add_file -vhdl -lib work "design/cores/fifo_32to64x512_dualclock.vhd"
add_file -vhdl -lib work "design/cores/fifo_16x512_dualclock.vhd"
add_file -vhdl -lib work "design/cores/fifo_9x512_dualclock.vhd"
--- /dev/null
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 8
+-sphld m
\r
entity pexor is\r
generic(\r
- NUM_LINKS : integer range 1 to 4 := 2\r
+ NUM_LINKS : integer range 1 to 4 := 1\r
);\r
port(\r
--Clock and Reset\r
-- );\r
\r
\r
-med_stat_op(31 downto 16) <= x"000" & "0111";\r
+-- med_stat_op(31 downto 16) <= x"000" & "0111";\r
---------------------------------------------------------------------------\r
-- Active Endpoint\r
---------------------------------------------------------------------------\r
led(1) <= not med_stat_op(10);\r
led(2) <= not med_stat_op(11);\r
\r
- led(4) <= not med_stat_op(16+9);\r
- led(5) <= not med_stat_op(16+10);\r
+ led(4) <= '1'; --not med_stat_op(16+9);\r
+ led(5) <= '1'; --not med_stat_op(16+10);\r
\r
led(6) <= not make_reset_internal;\r
led(7) <= not send_network_reset_internal;\r
--- /dev/null
+\r
+# This file is used by the simulation model as well as the ispLEVER bitstream\r
+# generation process to automatically initialize the PCS quad to the mode\r
+# selected in the IPexpress. This file is expected to be modified by the\r
+# end user to adjust the PCS quad to the final design requirements.\r
+# channel_0 is in "PCI Express" mode\r
+# channel_1 is in "PCI Express" mode\r
+# channel_2 is in "PCI Express" mode\r
+# channel_3 is in "PCI Express" mode\r
+\r
+ch0 13 03 # Powerup Channel\r
+ch0 00 01\r
+ch1 13 03 # Powerup Channel\r
+ch1 00 01\r
+ch2 13 03 # Powerup Channel\r
+ch2 00 01\r
+ch3 13 03 # Powerup Channel\r
+ch3 00 01\r
+quad 28 50 # Reference clock multiplier\r
+quad 29 10 # FPGA sourced refclk\r
+# quad 02 00 # ref_pclk source is ch0\r
+quad 18 04 # PCI Express x4 Mode\r
+quad 14 7F # Word Alignment Mask\r
+quad 15 03 # +ve K\r
+quad 16 7C # -ve K\r
+# quad 0D 97 # Watermark level on CTC\r
+quad 0E 00 # insertion/deletion control of CTC\r
+quad 12 1C # pattern for CTC match\r
+quad 13 01\r
+quad 19 40 # MCA x4 alignment\r
+quad 01 00 # MCA mclk select to ch0\r
+# quad 04 00 # MCA enable 4 channels via ports\r
+quad 05 01 # MCA latency\r
+quad 06 06 # MCA depth\r
+# quad 07 FF # MCA alignment mask\r
+quad 08 BC # MCA alignment character\r
+quad 09 BC # MCA alignment character\r
+# quad 0A 15 # MCA k control\r
+quad 30 04 # Set TX Sync Bit\r
+ch0 15 10 # +6dB equalization\r
+ch1 15 10 # +6dB equalization\r
+ch2 15 10 # +6dB equalization\r
+ch3 15 10 # +6dB equalization\r
+ch0 14 93 # 16% Pre-emphasis\r
+ch1 14 93 # 16% Pre-emphasis\r
+ch2 14 93 # 16% Pre-emphasis\r
+ch3 14 93 # 16% Pre-emphasis\r
+quad 41 00 # de-assert serdes_rst\r
+\r
+\r
+\r