--- /dev/null
+Adder_304/impl/Adder_304_impl.ngo
\ No newline at end of file
+++ /dev/null
-Date=03/20/2015
-Time=11:44:26
-
+++ /dev/null
-(edif Adder_304
- (edifVersion 2 0 0)
- (edifLevel 0)
- (keywordMap (keywordLevel 0))
- (status
- (written
- (timestamp 2015 3 20 11 44 28)
- (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
- (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n Adder_304 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type add -width 64 -unsigned -output_reg -enable -pipeline 0 -fdc /home/cugur/Projects/TDC_on_TRB3/tdc/base/cores/ecp5/TDC/Adder_304/Adder_304.fdc ")
- (library ORCLIB
- (edifLevel 0)
- (technology
- (numberDefinition))
- (cell CCU2C
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port A0
- (direction INPUT))
- (port A1
- (direction INPUT))
- (port B0
- (direction INPUT))
- (port B1
- (direction INPUT))
- (port C0
- (direction INPUT))
- (port C1
- (direction INPUT))
- (port D0
- (direction INPUT))
- (port D1
- (direction INPUT))
- (port CIN
- (direction INPUT))
- (port S0
- (direction OUTPUT))
- (port S1
- (direction OUTPUT))
- (port COUT
- (direction OUTPUT)))))
- (cell FD1P3DX
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port D
- (direction INPUT))
- (port SP
- (direction INPUT))
- (port CK
- (direction INPUT))
- (port CD
- (direction INPUT))
- (port Q
- (direction OUTPUT)))))
- (cell VHI
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port Z
- (direction OUTPUT)))))
- (cell VLO
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port Z
- (direction OUTPUT)))))
- (cell Adder_304
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port (array (rename DataA "DataA(63:0)") 64)
- (direction INPUT))
- (port (array (rename DataB "DataB(63:0)") 64)
- (direction INPUT))
- (port Clock
- (direction INPUT))
- (port Reset
- (direction INPUT))
- (port ClockEn
- (direction INPUT))
- (port (array (rename Result "Result(63:0)") 64)
- (direction OUTPUT)))
- (property NGD_DRC_MASK (integer 1))
- (contents
- (instance FF_63
- (viewRef view1
- (cellRef FD1P3DX))
- (property GSR
- (string "ENABLED")))
- (instance FF_62
- (viewRef view1
- (cellRef FD1P3DX))
- (property GSR
- (string "ENABLED")))
- (instance FF_61
- (viewRef view1
- (cellRef FD1P3DX))
- (property GSR
- (string "ENABLED")))
- (instance FF_60
- (viewRef view1
- (cellRef FD1P3DX))
- (property GSR
- (string "ENABLED")))
- (instance FF_59
- (viewRef view1
- (cellRef FD1P3DX))
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- (string "ENABLED")))
- (instance FF_58
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- (string "ENABLED")))
- (instance FF_57
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- (cellRef FD1P3DX))
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- (string "ENABLED")))
- (instance FF_56
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- (instance FF_55
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- (instance FF_54
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- (instance FF_53
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- (cellRef FD1P3DX))
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- (cellRef FD1P3DX))
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- (string "ENABLED")))
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- (cellRef FD1P3DX))
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- (cellRef FD1P3DX))
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- (instance FF_18
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- (instance FF_17
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- (instance FF_16
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- (cellRef FD1P3DX))
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- (instance FF_15
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- (instance FF_14
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- (instance FF_13
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- (instance FF_12
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- (instance FF_11
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- (cellRef FD1P3DX))
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- (string "ENABLED")))
- (instance FF_10
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- (cellRef FD1P3DX))
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- (instance FF_9
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- (instance FF_8
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- (cellRef FD1P3DX))
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- (instance FF_7
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- (cellRef FD1P3DX))
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- (instance FF_6
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- (instance FF_5
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- (instance FF_4
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- (instance FF_3
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- (instance FF_2
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- (instance FF_1
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- (string "ENABLED")))
- (instance FF_0
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- (instance addsub_0
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- (cellRef CCU2C))
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- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_1
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- (property INJECT1_0
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- (string "0x66AA")))
- (instance addsub_2
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_3
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_4
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_5
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_6
- (viewRef view1
- (cellRef CCU2C))
- (property INJECT1_1
- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_7
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_8
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_9
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_10
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_11
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- (cellRef CCU2C))
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- (property INJECT1_0
- (string "NO"))
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- (string "0x66AA"))
- (property INIT0
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- (instance addsub_12
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- (property INJECT1_0
- (string "NO"))
- (property INIT1
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- (property INIT0
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- (instance addsub_13
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
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- (property INIT0
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- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_15
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- (string "NO"))
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- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_16
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- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_17
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_18
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_19
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_20
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_21
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- (cellRef CCU2C))
- (property INJECT1_1
- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_22
- (viewRef view1
- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_23
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_24
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_25
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_26
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_27
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_28
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_29
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- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_30
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance addsub_31
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (instance scuba_vhi_inst
- (viewRef view1
- (cellRef VHI)))
- (instance scuba_vlo_inst
- (viewRef view1
- (cellRef VLO)))
- (instance addsub_32
- (viewRef view1
- (cellRef CCU2C))
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- (string "NO"))
- (property INJECT1_0
- (string "NO"))
- (property INIT1
- (string "0x66AA"))
- (property INIT0
- (string "0x66AA")))
- (net tsum0
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- (net x
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- (portRef CIN (instanceRef addsub_0))))
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- (net tsum6
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- (net co2
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- (design Adder_304
- (cellRef Adder_304
- (libraryRef ORCLIB)))
-)
+++ /dev/null
-###==== Start Configuration
-
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="Adder_304" device="LFE5UM-85F-8BG381C" default_implementation="impl">
+ <Options/>
+ <Implementation title="impl" dir="impl" description="impl" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="Adder_304"/>
+ <Source name="../Adder_304.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="Adder_304"/>
+ </Source>
+ <Source name="Adder_304.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="Adder_3041.sty"/>
+</BaliProject>
+++ /dev/null
-[Device]
-Family=ecp5um
-PartType=LFE5UM-85F
-PartName=LFE5UM-85F-8MG285C
-SpeedGrade=8
-Package=CSFBGA285
-OperatingCondition=COM
-Status=C
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=Adder
-CoreRevision=3.4
-ModuleName=Adder_304
-SourceFormat=vhdl
-ParameterFileVersion=1.0
-Date=03/20/2015
-Time=11:44:26
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-InputWidth=64
-Representation=Unsigned
-UseCIport=0
-COport=None
-OutReg=1
-Complex=0
-Stage=0
-
-[Command]
-cmd_line= -w -n Adder_304 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type mgaddsub -width 64 -unsigned -output_reg -enable -pipeline 0
--- /dev/null
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+++ /dev/null
-Adder_304.vhd
+++ /dev/null
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Mar 20 11:44:28 2015
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n Adder_304 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type mgaddsub -width 64 -unsigned -output_reg -enable -pipeline 0 -fdc /home/cugur/Projects/TDC_on_TRB3/tdc/base/cores/ecp5/TDC/Adder_304/Adder_304.fdc
- Circuit name : Adder_304
- Module type : add
- Module Version : 3.4
- Width : 64
- Ports :
- Inputs : DataA[63:0], DataB[63:0], Clock, Reset, ClockEn
- Outputs : Result[63:0]
- I/O buffer : not inserted
- Representation : unsigned number
- EDIF output : Adder_304.edn
- VHDL output : Adder_304.vhd
- VHDL template : Adder_304_tmpl.vhd
- VHDL testbench : tb_Adder_304_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : Adder_304.srp
- Element Usage :
- CCU2C : 33
- FD1P3DX : 64
- Estimated Resource Usage:
- LUT : 66
- Reg : 64
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 3.4
---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n Adder_304 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type add -width 64 -unsigned -output_reg -enable -pipeline 0 -fdc /home/cugur/Projects/TDC_on_TRB3/tdc/base/cores/ecp5/TDC/Adder_304/Adder_304.fdc
-
--- Fri Mar 20 11:44:28 2015
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-library ecp5um;
-use ecp5um.components.all;
-
-entity Adder_304 is
- port (
- DataA: in std_logic_vector(63 downto 0);
- DataB: in std_logic_vector(63 downto 0);
- Clock: in std_logic;
- Reset: in std_logic;
- ClockEn: in std_logic;
- Result: out std_logic_vector(63 downto 0));
-end Adder_304;
-
-architecture Structure of Adder_304 is
-
- -- internal signal declarations
- signal r0_sum63: std_logic;
- signal r0_sum62: std_logic;
- signal r0_sum61: std_logic;
- signal r0_sum60: std_logic;
- signal r0_sum59: std_logic;
- signal r0_sum58: std_logic;
- signal r0_sum57: std_logic;
- signal r0_sum56: std_logic;
- signal r0_sum55: std_logic;
- signal r0_sum54: std_logic;
- signal r0_sum53: std_logic;
- signal r0_sum52: std_logic;
- signal r0_sum51: std_logic;
- signal r0_sum50: std_logic;
- signal r0_sum49: std_logic;
- signal r0_sum48: std_logic;
- signal r0_sum47: std_logic;
- signal r0_sum46: std_logic;
- signal r0_sum45: std_logic;
- signal r0_sum44: std_logic;
- signal r0_sum43: std_logic;
- signal r0_sum42: std_logic;
- signal r0_sum41: std_logic;
- signal r0_sum40: std_logic;
- signal r0_sum39: std_logic;
- signal r0_sum38: std_logic;
- signal r0_sum37: std_logic;
- signal r0_sum36: std_logic;
- signal r0_sum35: std_logic;
- signal r0_sum34: std_logic;
- signal r0_sum33: std_logic;
- signal r0_sum32: std_logic;
- signal r0_sum31: std_logic;
- signal r0_sum30: std_logic;
- signal r0_sum29: std_logic;
- signal r0_sum28: std_logic;
- signal r0_sum27: std_logic;
- signal r0_sum26: std_logic;
- signal r0_sum25: std_logic;
- signal r0_sum24: std_logic;
- signal r0_sum23: std_logic;
- signal r0_sum22: std_logic;
- signal r0_sum21: std_logic;
- signal r0_sum20: std_logic;
- signal r0_sum19: std_logic;
- signal r0_sum18: std_logic;
- signal r0_sum17: std_logic;
- signal r0_sum16: std_logic;
- signal r0_sum15: std_logic;
- signal r0_sum14: std_logic;
- signal r0_sum13: std_logic;
- signal r0_sum12: std_logic;
- signal r0_sum11: std_logic;
- signal r0_sum10: std_logic;
- signal r0_sum9: std_logic;
- signal r0_sum8: std_logic;
- signal r0_sum7: std_logic;
- signal r0_sum6: std_logic;
- signal r0_sum5: std_logic;
- signal r0_sum4: std_logic;
- signal r0_sum3: std_logic;
- signal r0_sum2: std_logic;
- signal r0_sum1: std_logic;
- signal r0_sum0: std_logic;
- signal tsum0: std_logic;
- signal tsum1: std_logic;
- signal tsum2: std_logic;
- signal co0: std_logic;
- signal tsum3: std_logic;
- signal tsum4: std_logic;
- signal co1: std_logic;
- signal tsum5: std_logic;
- signal tsum6: std_logic;
- signal co2: std_logic;
- signal tsum7: std_logic;
- signal tsum8: std_logic;
- signal co3: std_logic;
- signal tsum9: std_logic;
- signal tsum10: std_logic;
- signal co4: std_logic;
- signal tsum11: std_logic;
- signal tsum12: std_logic;
- signal co5: std_logic;
- signal tsum13: std_logic;
- signal tsum14: std_logic;
- signal co6: std_logic;
- signal tsum15: std_logic;
- signal tsum16: std_logic;
- signal co7: std_logic;
- signal tsum17: std_logic;
- signal tsum18: std_logic;
- signal co8: std_logic;
- signal tsum19: std_logic;
- signal tsum20: std_logic;
- signal co9: std_logic;
- signal tsum21: std_logic;
- signal tsum22: std_logic;
- signal co10: std_logic;
- signal tsum23: std_logic;
- signal tsum24: std_logic;
- signal co11: std_logic;
- signal tsum25: std_logic;
- signal tsum26: std_logic;
- signal co12: std_logic;
- signal tsum27: std_logic;
- signal tsum28: std_logic;
- signal co13: std_logic;
- signal tsum29: std_logic;
- signal tsum30: std_logic;
- signal co14: std_logic;
- signal tsum31: std_logic;
- signal tsum32: std_logic;
- signal co15: std_logic;
- signal tsum33: std_logic;
- signal tsum34: std_logic;
- signal co16: std_logic;
- signal tsum35: std_logic;
- signal tsum36: std_logic;
- signal co17: std_logic;
- signal tsum37: std_logic;
- signal tsum38: std_logic;
- signal co18: std_logic;
- signal tsum39: std_logic;
- signal tsum40: std_logic;
- signal co19: std_logic;
- signal tsum41: std_logic;
- signal tsum42: std_logic;
- signal co20: std_logic;
- signal tsum43: std_logic;
- signal tsum44: std_logic;
- signal co21: std_logic;
- signal tsum45: std_logic;
- signal tsum46: std_logic;
- signal co22: std_logic;
- signal tsum47: std_logic;
- signal tsum48: std_logic;
- signal co23: std_logic;
- signal tsum49: std_logic;
- signal tsum50: std_logic;
- signal co24: std_logic;
- signal tsum51: std_logic;
- signal tsum52: std_logic;
- signal co25: std_logic;
- signal tsum53: std_logic;
- signal tsum54: std_logic;
- signal co26: std_logic;
- signal tsum55: std_logic;
- signal tsum56: std_logic;
- signal co27: std_logic;
- signal tsum57: std_logic;
- signal tsum58: std_logic;
- signal co28: std_logic;
- signal tsum59: std_logic;
- signal tsum60: std_logic;
- signal co29: std_logic;
- signal tsum61: std_logic;
- signal tsum62: std_logic;
- signal co30: std_logic;
- signal tsum63: std_logic;
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
- signal co31: std_logic;
-
- attribute GSR : string;
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- FF_63: FD1P3DX
- port map (D=>tsum63, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum63);
-
- FF_62: FD1P3DX
- port map (D=>tsum62, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum62);
-
- FF_61: FD1P3DX
- port map (D=>tsum61, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum61);
-
- FF_60: FD1P3DX
- port map (D=>tsum60, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum60);
-
- FF_59: FD1P3DX
- port map (D=>tsum59, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum59);
-
- FF_58: FD1P3DX
- port map (D=>tsum58, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum58);
-
- FF_57: FD1P3DX
- port map (D=>tsum57, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum57);
-
- FF_56: FD1P3DX
- port map (D=>tsum56, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum56);
-
- FF_55: FD1P3DX
- port map (D=>tsum55, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum55);
-
- FF_54: FD1P3DX
- port map (D=>tsum54, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum54);
-
- FF_53: FD1P3DX
- port map (D=>tsum53, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum53);
-
- FF_52: FD1P3DX
- port map (D=>tsum52, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum52);
-
- FF_51: FD1P3DX
- port map (D=>tsum51, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum51);
-
- FF_50: FD1P3DX
- port map (D=>tsum50, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum50);
-
- FF_49: FD1P3DX
- port map (D=>tsum49, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum49);
-
- FF_48: FD1P3DX
- port map (D=>tsum48, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum48);
-
- FF_47: FD1P3DX
- port map (D=>tsum47, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum47);
-
- FF_46: FD1P3DX
- port map (D=>tsum46, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum46);
-
- FF_45: FD1P3DX
- port map (D=>tsum45, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum45);
-
- FF_44: FD1P3DX
- port map (D=>tsum44, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum44);
-
- FF_43: FD1P3DX
- port map (D=>tsum43, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum43);
-
- FF_42: FD1P3DX
- port map (D=>tsum42, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum42);
-
- FF_41: FD1P3DX
- port map (D=>tsum41, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum41);
-
- FF_40: FD1P3DX
- port map (D=>tsum40, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum40);
-
- FF_39: FD1P3DX
- port map (D=>tsum39, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum39);
-
- FF_38: FD1P3DX
- port map (D=>tsum38, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum38);
-
- FF_37: FD1P3DX
- port map (D=>tsum37, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum37);
-
- FF_36: FD1P3DX
- port map (D=>tsum36, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum36);
-
- FF_35: FD1P3DX
- port map (D=>tsum35, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum35);
-
- FF_34: FD1P3DX
- port map (D=>tsum34, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum34);
-
- FF_33: FD1P3DX
- port map (D=>tsum33, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum33);
-
- FF_32: FD1P3DX
- port map (D=>tsum32, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum32);
-
- FF_31: FD1P3DX
- port map (D=>tsum31, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum31);
-
- FF_30: FD1P3DX
- port map (D=>tsum30, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum30);
-
- FF_29: FD1P3DX
- port map (D=>tsum29, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum29);
-
- FF_28: FD1P3DX
- port map (D=>tsum28, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum28);
-
- FF_27: FD1P3DX
- port map (D=>tsum27, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum27);
-
- FF_26: FD1P3DX
- port map (D=>tsum26, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum26);
-
- FF_25: FD1P3DX
- port map (D=>tsum25, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum25);
-
- FF_24: FD1P3DX
- port map (D=>tsum24, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum24);
-
- FF_23: FD1P3DX
- port map (D=>tsum23, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum23);
-
- FF_22: FD1P3DX
- port map (D=>tsum22, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum22);
-
- FF_21: FD1P3DX
- port map (D=>tsum21, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum21);
-
- FF_20: FD1P3DX
- port map (D=>tsum20, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum20);
-
- FF_19: FD1P3DX
- port map (D=>tsum19, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum19);
-
- FF_18: FD1P3DX
- port map (D=>tsum18, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum18);
-
- FF_17: FD1P3DX
- port map (D=>tsum17, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum17);
-
- FF_16: FD1P3DX
- port map (D=>tsum16, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum16);
-
- FF_15: FD1P3DX
- port map (D=>tsum15, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum15);
-
- FF_14: FD1P3DX
- port map (D=>tsum14, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum14);
-
- FF_13: FD1P3DX
- port map (D=>tsum13, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum13);
-
- FF_12: FD1P3DX
- port map (D=>tsum12, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum12);
-
- FF_11: FD1P3DX
- port map (D=>tsum11, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum11);
-
- FF_10: FD1P3DX
- port map (D=>tsum10, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum10);
-
- FF_9: FD1P3DX
- port map (D=>tsum9, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum9);
-
- FF_8: FD1P3DX
- port map (D=>tsum8, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum8);
-
- FF_7: FD1P3DX
- port map (D=>tsum7, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum7);
-
- FF_6: FD1P3DX
- port map (D=>tsum6, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum6);
-
- FF_5: FD1P3DX
- port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum5);
-
- FF_4: FD1P3DX
- port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum4);
-
- FF_3: FD1P3DX
- port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum3);
-
- FF_2: FD1P3DX
- port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum2);
-
- FF_1: FD1P3DX
- port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum1);
-
- FF_0: FD1P3DX
- port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum0);
-
- addsub_0: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>scuba_vlo, A1=>DataA(0), B0=>scuba_vlo,
- B1=>DataB(0), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>tsum0, COUT=>co0);
-
- addsub_1: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(1), A1=>DataA(2), B0=>DataB(1), B1=>DataB(2),
- C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
- CIN=>co0, S0=>tsum1, S1=>tsum2, COUT=>co1);
-
- addsub_2: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(3), A1=>DataA(4), B0=>DataB(3), B1=>DataB(4),
- C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
- CIN=>co1, S0=>tsum3, S1=>tsum4, COUT=>co2);
-
- addsub_3: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(5), A1=>DataA(6), B0=>DataB(5), B1=>DataB(6),
- C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
- CIN=>co2, S0=>tsum5, S1=>tsum6, COUT=>co3);
-
- addsub_4: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(7), A1=>DataA(8), B0=>DataB(7), B1=>DataB(8),
- C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
- CIN=>co3, S0=>tsum7, S1=>tsum8, COUT=>co4);
-
- addsub_5: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(9), A1=>DataA(10), B0=>DataB(9),
- B1=>DataB(10), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co4, S0=>tsum9, S1=>tsum10, COUT=>co5);
-
- addsub_6: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(11), A1=>DataA(12), B0=>DataB(11),
- B1=>DataB(12), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co5, S0=>tsum11, S1=>tsum12, COUT=>co6);
-
- addsub_7: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(13), A1=>DataA(14), B0=>DataB(13),
- B1=>DataB(14), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co6, S0=>tsum13, S1=>tsum14, COUT=>co7);
-
- addsub_8: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(15), A1=>DataA(16), B0=>DataB(15),
- B1=>DataB(16), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co7, S0=>tsum15, S1=>tsum16, COUT=>co8);
-
- addsub_9: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(17), A1=>DataA(18), B0=>DataB(17),
- B1=>DataB(18), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co8, S0=>tsum17, S1=>tsum18, COUT=>co9);
-
- addsub_10: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(19), A1=>DataA(20), B0=>DataB(19),
- B1=>DataB(20), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co9, S0=>tsum19, S1=>tsum20, COUT=>co10);
-
- addsub_11: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(21), A1=>DataA(22), B0=>DataB(21),
- B1=>DataB(22), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co10, S0=>tsum21, S1=>tsum22, COUT=>co11);
-
- addsub_12: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(23), A1=>DataA(24), B0=>DataB(23),
- B1=>DataB(24), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co11, S0=>tsum23, S1=>tsum24, COUT=>co12);
-
- addsub_13: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(25), A1=>DataA(26), B0=>DataB(25),
- B1=>DataB(26), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co12, S0=>tsum25, S1=>tsum26, COUT=>co13);
-
- addsub_14: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(27), A1=>DataA(28), B0=>DataB(27),
- B1=>DataB(28), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co13, S0=>tsum27, S1=>tsum28, COUT=>co14);
-
- addsub_15: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(29), A1=>DataA(30), B0=>DataB(29),
- B1=>DataB(30), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co14, S0=>tsum29, S1=>tsum30, COUT=>co15);
-
- addsub_16: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(31), A1=>DataA(32), B0=>DataB(31),
- B1=>DataB(32), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co15, S0=>tsum31, S1=>tsum32, COUT=>co16);
-
- addsub_17: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(33), A1=>DataA(34), B0=>DataB(33),
- B1=>DataB(34), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co16, S0=>tsum33, S1=>tsum34, COUT=>co17);
-
- addsub_18: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(35), A1=>DataA(36), B0=>DataB(35),
- B1=>DataB(36), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co17, S0=>tsum35, S1=>tsum36, COUT=>co18);
-
- addsub_19: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(37), A1=>DataA(38), B0=>DataB(37),
- B1=>DataB(38), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co18, S0=>tsum37, S1=>tsum38, COUT=>co19);
-
- addsub_20: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(39), A1=>DataA(40), B0=>DataB(39),
- B1=>DataB(40), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co19, S0=>tsum39, S1=>tsum40, COUT=>co20);
-
- addsub_21: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(41), A1=>DataA(42), B0=>DataB(41),
- B1=>DataB(42), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co20, S0=>tsum41, S1=>tsum42, COUT=>co21);
-
- addsub_22: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(43), A1=>DataA(44), B0=>DataB(43),
- B1=>DataB(44), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co21, S0=>tsum43, S1=>tsum44, COUT=>co22);
-
- addsub_23: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(45), A1=>DataA(46), B0=>DataB(45),
- B1=>DataB(46), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co22, S0=>tsum45, S1=>tsum46, COUT=>co23);
-
- addsub_24: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(47), A1=>DataA(48), B0=>DataB(47),
- B1=>DataB(48), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co23, S0=>tsum47, S1=>tsum48, COUT=>co24);
-
- addsub_25: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(49), A1=>DataA(50), B0=>DataB(49),
- B1=>DataB(50), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co24, S0=>tsum49, S1=>tsum50, COUT=>co25);
-
- addsub_26: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(51), A1=>DataA(52), B0=>DataB(51),
- B1=>DataB(52), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co25, S0=>tsum51, S1=>tsum52, COUT=>co26);
-
- addsub_27: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(53), A1=>DataA(54), B0=>DataB(53),
- B1=>DataB(54), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co26, S0=>tsum53, S1=>tsum54, COUT=>co27);
-
- addsub_28: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(55), A1=>DataA(56), B0=>DataB(55),
- B1=>DataB(56), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co27, S0=>tsum55, S1=>tsum56, COUT=>co28);
-
- addsub_29: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(57), A1=>DataA(58), B0=>DataB(57),
- B1=>DataB(58), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co28, S0=>tsum57, S1=>tsum58, COUT=>co29);
-
- addsub_30: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(59), A1=>DataA(60), B0=>DataB(59),
- B1=>DataB(60), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co29, S0=>tsum59, S1=>tsum60, COUT=>co30);
-
- addsub_31: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(61), A1=>DataA(62), B0=>DataB(61),
- B1=>DataB(62), C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co30, S0=>tsum61, S1=>tsum62, COUT=>co31);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- addsub_32: CCU2C
- generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
- INIT0=> X"66AA")
- port map (A0=>DataA(63), A1=>scuba_vlo, B0=>DataB(63),
- B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
- D1=>scuba_vhi, CIN=>co31, S0=>tsum63, S1=>open, COUT=>open);
-
- Result(63) <= r0_sum63;
- Result(62) <= r0_sum62;
- Result(61) <= r0_sum61;
- Result(60) <= r0_sum60;
- Result(59) <= r0_sum59;
- Result(58) <= r0_sum58;
- Result(57) <= r0_sum57;
- Result(56) <= r0_sum56;
- Result(55) <= r0_sum55;
- Result(54) <= r0_sum54;
- Result(53) <= r0_sum53;
- Result(52) <= r0_sum52;
- Result(51) <= r0_sum51;
- Result(50) <= r0_sum50;
- Result(49) <= r0_sum49;
- Result(48) <= r0_sum48;
- Result(47) <= r0_sum47;
- Result(46) <= r0_sum46;
- Result(45) <= r0_sum45;
- Result(44) <= r0_sum44;
- Result(43) <= r0_sum43;
- Result(42) <= r0_sum42;
- Result(41) <= r0_sum41;
- Result(40) <= r0_sum40;
- Result(39) <= r0_sum39;
- Result(38) <= r0_sum38;
- Result(37) <= r0_sum37;
- Result(36) <= r0_sum36;
- Result(35) <= r0_sum35;
- Result(34) <= r0_sum34;
- Result(33) <= r0_sum33;
- Result(32) <= r0_sum32;
- Result(31) <= r0_sum31;
- Result(30) <= r0_sum30;
- Result(29) <= r0_sum29;
- Result(28) <= r0_sum28;
- Result(27) <= r0_sum27;
- Result(26) <= r0_sum26;
- Result(25) <= r0_sum25;
- Result(24) <= r0_sum24;
- Result(23) <= r0_sum23;
- Result(22) <= r0_sum22;
- Result(21) <= r0_sum21;
- Result(20) <= r0_sum20;
- Result(19) <= r0_sum19;
- Result(18) <= r0_sum18;
- Result(17) <= r0_sum17;
- Result(16) <= r0_sum16;
- Result(15) <= r0_sum15;
- Result(14) <= r0_sum14;
- Result(13) <= r0_sum13;
- Result(12) <= r0_sum12;
- Result(11) <= r0_sum11;
- Result(10) <= r0_sum10;
- Result(9) <= r0_sum9;
- Result(8) <= r0_sum8;
- Result(7) <= r0_sum7;
- Result(6) <= r0_sum6;
- Result(5) <= r0_sum5;
- Result(4) <= r0_sum4;
- Result(3) <= r0_sum3;
- Result(2) <= r0_sum2;
- Result(1) <= r0_sum1;
- Result(0) <= r0_sum0;
-end Structure;
+++ /dev/null
-Starting process:
-
-Configuration data saved
-
-
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Mar 20 11:44:26 2015
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n Adder_304 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type mgaddsub -width 64 -unsigned -output_reg -enable -pipeline 0
- Circuit name : Adder_304
- Module type : add
- Module Version : 3.4
- Width : 64
- Ports :
- Inputs : DataA[63:0], DataB[63:0], Clock, Reset, ClockEn
- Outputs : Result[63:0]
- I/O buffer : not inserted
- Representation : unsigned number
- EDIF output : Adder_304.edn
- VHDL output : Adder_304.vhd
- VHDL template : Adder_304_tmpl.vhd
- VHDL testbench : tb_Adder_304_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : Adder_304.srp
- Estimated Resource Usage:
- LUT : 66
- Reg : 64
-
-END SCUBA Module Synthesis
-
-File: Adder_304.lpc created.
-
-
-End process: completed successfully.
-
-
-Total Warnings: 0
-
-Total Errors: 0
-
-
+++ /dev/null
-[ActiveSupport NGD]
+++ /dev/null
--- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 3.4
--- Fri Mar 20 11:44:28 2015
-
--- parameterized module component declaration
-component Adder_304
- port (DataA: in std_logic_vector(63 downto 0);
- DataB: in std_logic_vector(63 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result: out std_logic_vector(63 downto 0));
-end component;
-
--- parameterized module component instance
-__ : Adder_304
- port map (DataA(63 downto 0)=>__, DataB(63 downto 0)=>__, Clock=>__,
- Reset=>__, ClockEn=>__, Result(63 downto 0)=>__);
+++ /dev/null
-#!/usr/local/bin/wish
-
-proc GetPlatform {} {
- global tcl_platform
-
- set cpu $tcl_platform(machine)
-
- switch $cpu {
- intel -
- i*86* {
- set cpu ix86
- }
- x86_64 {
- if {$tcl_platform(wordSize) == 4} {
- set cpu ix86
- }
- }
- }
-
- switch $tcl_platform(platform) {
- windows {
- if {$cpu == "amd64"} {
- # Do not check wordSize, win32-x64 is an IL32P64 platform.
- set cpu x86_64
- }
- if {$cpu == "x86_64"} {
- return "nt64"
- } else {
- return "nt"
- }
- }
- unix {
- if {$tcl_platform(os) == "Linux"} {
- if {$cpu == "x86_64"} {
- return "lin64"
- } else {
- return "lin"
- }
- } else {
- return "sol"
- }
- }
- }
- return "nt"
-}
-
-proc GetCmdLine {lpcfile} {
- global Para
-
- if [catch {open $lpcfile r} fileid] {
- puts "Cannot open $para_file file!"
- exit -1
- }
-
- seek $fileid 0 start
- set default_match 0
- while {[gets $fileid line] >= 0} {
- if {[string first "\[Command\]" $line] == 0} {
- set default_match 1
- continue
- }
- if {[string first "\[" $line] == 0} {
- set default_match 0
- }
- if {$default_match == 1} {
- if [regexp {([^=]*)=(.*)} $line match parameter value] {
- if [regexp {([ |\t]*;)} $parameter match] {continue}
- if [regexp {(.*)[ |\t]*;} $value match temp] {
- set Para($parameter) $temp
- } else {
- set Para($parameter) $value
- }
- }
- }
- }
- set default_match 0
- close $fileid
-
- return $Para(cmd_line)
-}
-
-set platformpath [GetPlatform]
-set Para(sbp_path) [file dirname [info script]]
-set Para(install_dir) $env(TOOLRTF)
-set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
-
-set scuba "$Para(FPGAPath)/scuba"
-set modulename "Adder_304"
-set lang "vhdl"
-set lpcfile "$Para(sbp_path)/$modulename.lpc"
-set arch "sa5p00m"
-set cmd_line [GetCmdLine $lpcfile]
-set fdcfile "$Para(sbp_path)/$modulename.fdc"
-if {[file exists $fdcfile] == 0} {
- append scuba " " $cmd_line
-} else {
- append scuba " " $cmd_line " " -fdc " " $fdcfile
-}
-set Para(result) [catch {eval exec "$scuba"} msg]
-#puts $msg
+++ /dev/null
-#!/usr/local/bin/wish
-
-proc GetPlatform {} {
- global tcl_platform
-
- set cpu $tcl_platform(machine)
-
- switch $cpu {
- intel -
- i*86* {
- set cpu ix86
- }
- x86_64 {
- if {$tcl_platform(wordSize) == 4} {
- set cpu ix86
- }
- }
- }
-
- switch $tcl_platform(platform) {
- windows {
- if {$cpu == "amd64"} {
- # Do not check wordSize, win32-x64 is an IL32P64 platform.
- set cpu x86_64
- }
- if {$cpu == "x86_64"} {
- return "nt64"
- } else {
- return "nt"
- }
- }
- unix {
- if {$tcl_platform(os) == "Linux"} {
- if {$cpu == "x86_64"} {
- return "lin64"
- } else {
- return "lin"
- }
- } else {
- return "sol"
- }
- }
- }
- return "nt"
-}
-
-set platformpath [GetPlatform]
-set Para(sbp_path) [file dirname [info script]]
-set Para(install_dir) $env(TOOLRTF)
-set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
-set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
-
-set Para(ModuleName) "Adder_304"
-set Para(Module) "Adder"
-set Para(libname) ecp5um
-set Para(arch_name) sa5p00m
-set Para(PartType) "LFE5UM-85F"
-
-set Para(tech_syn) ecp5um
-set Para(tech_cae) ecp5um
-set Para(Package) "CSFBGA285"
-set Para(SpeedGrade) "8"
-set Para(FMax) "100"
-set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
-
-#edif2ngd
-set edif2ngd "$Para(FPGAPath)/edif2ngd"
-set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
-#puts $msg
-
-#ngdbuild
-set ngdbuild "$Para(FPGAPath)/ngdbuild"
-set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
-#puts $msg
+++ /dev/null
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Mar 20 11:44:26 2015
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
-
-BEGIN SCUBA Module Synthesis
-
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n Adder_304 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type mgaddsub -width 64 -unsigned -output_reg -enable -pipeline 0
- Circuit name : Adder_304
- Module type : add
- Module Version : 3.4
- Width : 64
- Ports :
- Inputs : DataA[63:0], DataB[63:0], Clock, Reset, ClockEn
- Outputs : Result[63:0]
- I/O buffer : not inserted
- Representation : unsigned number
- EDIF output : Adder_304.edn
- VHDL output : Adder_304.vhd
- VHDL template : Adder_304_tmpl.vhd
- VHDL testbench : tb_Adder_304_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : Adder_304.srp
- Estimated Resource Usage:
- LUT : 66
- Reg : 64
-
-END SCUBA Module Synthesis
-
+++ /dev/null
--- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-use IEEE.math_real.all;
-
-use IEEE.numeric_std.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component Adder_304
- port (DataA : in std_logic_vector(63 downto 0);
- DataB : in std_logic_vector(63 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result : out std_logic_vector(63 downto 0)
- );
- end component;
-
- signal DataA : std_logic_vector(63 downto 0) := (others => '0');
- signal DataB : std_logic_vector(63 downto 0) := (others => '0');
- signal Clock: std_logic := '0';
- signal Reset: std_logic := '0';
- signal ClockEn: std_logic := '0';
- signal Result : std_logic_vector(63 downto 0);
-begin
- u1 : Adder_304
- port map (DataA => DataA, DataB => DataB, Clock => Clock, Reset => Reset,
- ClockEn => ClockEn, Result => Result
- );
-
- process
-
- begin
- DataA <= (others => '0') ;
- for i in 0 to 200 loop
- wait until Clock'event and Clock = '1';
- DataA <= DataA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataB <= (others => '0') ;
- for i in 0 to 200 loop
- wait until Clock'event and Clock = '1';
- DataB <= DataB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- Clock <= not Clock after 5.00 ns;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ClockEn <= '1' ;
- wait;
- end process;
-
-end architecture test;
jspc29 / tdc.git / commitdiff