]> jspc29.x-matter.uni-frankfurt.de Git - TOMcat.git/commitdiff
DHCP works now
authorMichael Boehmer <mboehmer@ph.tum.de>
Fri, 15 Jul 2022 19:20:00 +0000 (21:20 +0200)
committerMichael Boehmer <mboehmer@ph.tum.de>
Fri, 15 Jul 2022 19:20:00 +0000 (21:20 +0200)
code/clock_reset_handler.vhd
gbe/linkdesignfiles.sh [new file with mode: 0755]
gbe/tomcat_gbe.prj
gbe/tomcat_gbe.vhd

index ea801cbca307392054fee1388f9c5cccca3315d4..3f40f415b9efb76debc3bc48836c1166bf580388 100644 (file)
@@ -9,116 +9,79 @@ library work;
   use work.config.all;
 
 entity clock_reset_handler is
-  port (
-    CLOCK_IN        : in  std_logic;  -- oscillator
-    GLOBAL_RESET_IN : in  std_logic;
-
-    RESET_OUT       : out std_logic;
-    CLEAR_OUT       : out std_logic;
-    GSR_OUT         : out std_logic;
-    
-    RAW_CLK_OUT     : out std_logic;  -- 200/240 MHz for FPGA fabric
-    SYS_CLK_OUT     : out std_logic;  -- 100/120 MHz for FPGA fabric
-    REF_CLK_OUT     : out std_logic;  -- 200/240 internal reference clock
-    
-    DEBUG_OUT       : out std_logic_vector(31 downto 0)
-    );
+  port(
+    CLK_IN            : in  std_logic;
+    GLOBAL_RESET_IN   : in  std_logic := '0';
+    RESET_FROM_NET_IN : in  std_logic := '0';
+    --
+    CLK_OUT           : out std_logic;
+    RESET_OUT         : out std_logic;
+    RESET_N_OUT       : out std_logic;
+    CLEAR_OUT         : out std_logic;
+    CLEAR_N_OUT       : out std_logic;
+    --
+    LED_RED_OUT       : out std_logic;
+    LED_GREEN_OUT     : out std_logic
+  );
 end entity;
 
 architecture clock_reset_handler_arch of clock_reset_handler is
 
-attribute syn_keep         : boolean;
-attribute syn_preserve     : boolean;
-
-signal clock_100           : std_logic;
-signal clock_120           : std_logic;
-signal clock_200           : std_logic;
-signal clock_240           : std_logic;
-signal clock_200_raw       : std_logic;
-signal sys_clk_i           : std_logic;
-signal timer               : unsigned(24 downto 0) := (others => '0');
-signal clear_n_i           : std_logic := '0';
-signal reset_i             : std_logic;
-signal reset_rising        : std_logic;
-signal last_reset_i        : std_logic;
-signal debug_reset_handler : std_logic_vector(15 downto 0);
-signal pll_lock            : std_logic;
+signal timer                        : unsigned(15 downto 0) := (others => '0');
+signal clear_n_i                    : std_logic;
+signal reset_i                      : std_logic;
 
+attribute syn_keep                  : boolean;
+attribute syn_preserve              : boolean;
 attribute syn_keep of clear_n_i     : signal is true;
 attribute syn_preserve of clear_n_i : signal is true;
+attribute syn_keep of reset_i       : signal is true;
+attribute syn_preserve of reset_i   : signal is true;
 
 begin
 
-SYS_CLK_OUT <= sys_clk_i;
-GSR_OUT     <= not pll_lock or clear_n_i;
-
-THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input!
-  port map(
-    CLKI   => CLOCK_IN,
-    CLKOP  => clock_200_raw,
-    CLKOS  => clock_100,
-    CLKOS2 => clock_200, --clock_240,
-    CLKOS3 => clock_120,
-    LOCK   => pll_lock
-    );  
-
-gen_slow_clock : if USE_120_MHZ = 0 generate
-  RAW_CLK_OUT <= clock_200_raw;
-  sys_clk_i   <= clock_100;
-  REF_CLK_OUT <= clock_200_raw;
-end generate;
-gen_fast_clock : if USE_120_MHZ = 1 generate
-  RAW_CLK_OUT <= clock_240;
-  sys_clk_i   <= clock_120;
-  REF_CLK_OUT <= clock_240;
-end generate;
-
-clear_n_i <= timer(22) when rising_edge(clock_200_raw);
-
-process begin
-  wait until rising_edge(sys_clk_i);
-
-  if timer(22) = '1' then
-    timer <= timer;
-  elsif reset_rising = '1' then
-    timer <= (others => '0');
-  elsif pll_lock = '1' then
-    timer <= timer + 1;
-  end if;
-end process;
-
+  CLK_OUT <= CLK_IN;
 
 ---------------------------------------------------------------------------
--- Reset generation
+-- Startup timer, generates inital reset
+---------------------------------------------------------------------------          
+  THE_START_TIMER_PROC: process 
+  begin
+    wait until rising_edge(CLK_IN);
+    if( timer(15) = '1' ) then
+      timer <= timer;
+    else  
+      timer <= timer + 1;
+    end if;
+  end process THE_START_TIMER_PROC;
+
+  -- asserted only at power up!
+  clear_n_i <= timer(15) when rising_edge(CLK_IN);
+
+  CLEAR_OUT <= not clear_n_i;
+  
+  CLEAR_N_OUT <= clear_n_i;
+  
+---------------------------------------------------------------------------
+-- these resets can be triggered
 ---------------------------------------------------------------------------
-THE_RESET_HANDLER : trb_net_reset_handler
-  generic map(
-    RESET_DELAY     => x"FEEE"
-  )
+  THE_RESET_HANDLER: entity reset_handler 
   port map(
-    CLEAR_IN        => GLOBAL_RESET_IN, -- reset input (high active, async)
-    CLEAR_N_IN      => clear_n_i,       -- reset input (low active, async)
-    CLK_IN          => clock_200_raw,   -- raw master clock, NOT from PLL/DLL!
-    SYSCLK_IN       => sys_clk_i,       -- PLL/DLL remastered clock
-    PLL_LOCKED_IN   => pll_lock,        -- master PLL lock signal (async)
-    RESET_IN        => '0',             -- general reset signal (SYSCLK)
-    TRB_RESET_IN    => '0',             -- TRBnet reset signal (SYSCLK)
-    CLEAR_OUT       => CLEAR_OUT,       -- async reset out, USE WITH CARE!
-    RESET_OUT       => reset_i,         -- synchronous reset out (SYSCLK)
-    DEBUG_OUT       => debug_reset_handler
-  );  
-
-RESET_OUT <= reset_i;
-
-last_reset_i <= reset_i when rising_edge(clock_200_raw);
-reset_rising <= reset_i and not last_reset_i;
+    CLEAR_IN        => GLOBAL_RESET_IN,
+    CLEAR_N_IN      => clear_n_i,
+    CLK_IN          => CLK_IN,
+    PLL_LOCKED_IN   => '1',
+    RESET_IN        => RESET_FROM_NET_IN,
+    TRB_RESET_IN    => '0', -- unused,
+    CLEAR_OUT       => open,
+    RESET_OUT       => reset_i
+  );
+
+  RESET_OUT <= reset_i;
   
----------------------------------------------------------------------------
--- Slow clock for DCDC converters
----------------------------------------------------------------------------  
-DEBUG_OUT(0)  <= pll_lock;
-DEBUG_OUT(1)  <= clear_n_i;
-DEBUG_OUT(15 downto 2) <= debug_reset_handler(15 downto 2);
-DEBUG_OUT(31 downto 16) <= (others => '0');
+  RESET_N_OUT <= not reset_i;
+  
+  LED_RED_OUT      <= not reset_i;
+  LED_GREEN_OUT    <= not '0';
 
-end architecture;
+end architecture clock_reset_handler_arch;
diff --git a/gbe/linkdesignfiles.sh b/gbe/linkdesignfiles.sh
new file mode 100755 (executable)
index 0000000..afc23e6
--- /dev/null
@@ -0,0 +1,20 @@
+#!/bin/bash
+#These files should be linked in your workdir for new projects
+#they have to be in the directory were all the reports and bitfiles end up!
+#usually ./workdir (command line script) or ./$PROJECTNAME (Diamond)
+
+#it is assumed, that pwd is the first dir in the designs directory, e.g.
+#trb3/DESIGN/workdir. If this is not the case pass as first parameter a
+#path suffix to get to this level. For instance if you're in
+#trb3/DESIGN/project/TOPNAME call "../../../base/linkdesignfiles.sh .."
+
+if [ $1 ]
+then
+   prefix=$1
+else
+   prefix="."
+fi
+
+ln -sf $prefix/../../../trbnet/gbe_trb_ecp5/media/ecp5-5g/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo
+ln -sf $prefix/../../../trbnet/gbe_trb_ecp5/media/ecp5-5g/tsmac_gbe.ngo
+ln -sf $prefix/../../../trbnet/gbe_trb_ecp5/media/ecp5-5g/sgmii_gbe_core.ngo
index 53b0f9c4fd98ba557a587f0d679b6074475aaa53..e90064de33f02a9d4c1f1f41ee6a9e05647435f2 100644 (file)
@@ -65,9 +65,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
 
 #Basic Infrastructure
-add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../trb3sc/gbe_hub/reset_handler.vhd"
 add_file -vhdl -lib work "../../TOMcat/code/clock_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 
 #Fifos
@@ -162,9 +161,20 @@ add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_standalone_sctrl.vhd"
 
 #GbE
-add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper_single.vhd"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_lsm.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/scatter_ports.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gather_ports.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_fifo.vhd"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/gbe_med_fifo_single.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/rb_4k_9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/fifo_4k_9.vhd"
+
+
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
index b2fa122d9e465b2c3bd7b28cf2ce9dbf6869cb98..b41ad02443c3b68d88b8b70fd6a9d8d8317818de 100644 (file)
@@ -62,11 +62,11 @@ architecture arch of tomcat_gbe is
   attribute syn_preserve            : boolean;
 
   signal clk_sys                    : std_logic;
-  signal clk_full                   : std_logic;
-  signal clk_full_osc               : std_logic;
   signal GSR_N                      : std_logic;
   signal reset_i                    : std_logic;
+  signal reset_n_i                  : std_logic;
   signal clear_i                    : std_logic;
+  signal clear_n_i                  : std_logic;
   
   signal sd_led_green               : std_logic;
   signal sd_led_yellow              : std_logic;
@@ -91,7 +91,7 @@ architecture arch of tomcat_gbe is
   
   attribute syn_keep of GSR_N       : signal is true;
   attribute syn_preserve of GSR_N   : signal is true;  
-
+    
   signal debug                      : std_logic_vector(127 downto 0);
   signal status                     : std_logic_vector(15 downto 0);
 
@@ -111,11 +111,45 @@ architecture arch of tomcat_gbe is
   signal flash_miso_i               : std_logic;
   signal flash_mosi_i               : std_logic;
 
+  signal pcs_an_ready               : std_logic;
+  signal link_active                : std_logic;
+
+  -- the new FIFO interface
+  
+  -- 10: frame_start
+  -- 9 : fifo_wr
+  -- 8 : fifo_eof
+  -- 7..0: fifo_data
+  type dl_rx_data_t is array(0 to 0) of std_logic_vector(10 downto 0);
+  signal dl_rx_data : dl_rx_data_t;
+  signal dl_rx_frame_req            : std_logic_vector(0 downto 0);
+  signal dl_rx_frame_ack            : std_logic_vector(0 downto 0);
+  signal dl_rx_frame_avail          : std_logic_vector(0 downto 0);
+  signal dl_tx_fifofull             : std_logic_vector(0 downto 0);
+  
+  -- 10: frame_start
+  -- 9 : fifo_wr
+  -- 8 : fifo_eof
+  -- 7..0: data
+  signal ul_rx_data                 : std_logic_vector(10 downto 0);
+  signal ul_tx_data                 : std_logic_vector(10 downto 0);
+  signal ul_tx_data_q               : std_logic_vector(10 downto 0);
+  signal ul_tx_fifofull             : std_logic;
+  signal ul_rx_frame_avail          : std_logic;
+  signal ul_rx_frame_req            : std_logic;
+  signal ul_rx_frame_ack            : std_logic;
+  signal ul_rx_fifofull             : std_logic;
+  
+  signal port_sel                   : std_logic_vector(0 downto 0);
+
+  signal scatter_cycle_done         : std_logic;
+  signal gather_cycle_done          : std_logic;
+  
 begin
 
--------------------------------------------------------------------------------
+---------------------------------------------------------------------------
 -- Important pins
--------------------------------------------------------------------------------
+---------------------------------------------------------------------------
 --  PROGRAMN       <= '1';
 --  FLASH_OVERRIDE <= '1';
 --  FLASH_SCLK     <= 'Z';
@@ -123,62 +157,168 @@ begin
 --  FLASH_MOSI     <= '0';
 --  FLASH_HOLD     <= '1';
 --  FLASH_WP       <= '1';
-  
--------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
 -- Clock & Reset Handling
--------------------------------------------------------------------------------
-  THE_CLOCK_RESET : entity work.clock_reset_handler
-    port map(
-      CLOCK_IN        => CLK_200,
-      GLOBAL_RESET_IN => '0',
-      RESET_OUT       => reset_i,
-      CLEAR_OUT       => clear_i,
-      GSR_OUT         => GSR_N,
-      REF_CLK_OUT     => clk_full,
-      SYS_CLK_OUT     => clk_sys,
-      RAW_CLK_OUT     => clk_full_osc,
-      DEBUG_OUT       => open
-    );
+---------------------------------------------------------------------------
+  THE_CLOCK_RESET_HANDLER: entity clock_reset_handler
+  port map(
+    CLK_IN            => CLK_125,
+    GLOBAL_RESET_IN   => '0', -- for sync operation
+    RESET_FROM_NET_IN => '0', -- unused
+    --
+    CLK_OUT           => clk_sys,
+    RESET_OUT         => reset_i,
+    RESET_N_OUT       => reset_n_i,
+    CLEAR_OUT         => clear_i,
+    CLEAR_N_OUT       => clear_n_i,
+    --
+    LED_RED_OUT       => open,
+    LED_GREEN_OUT     => open
+  );
+  
 
--------------------------------------------------------------------------------
+---------------------------------------------------------------------------
 -- GbE interface
--------------------------------------------------------------------------------
-  GBE : entity work.gbe_wrapper_single
+---------------------------------------------------------------------------
+  GBE_MED_INTERFACE: entity gbe_med_fifo_single
+  port map(
+    RESET                 => reset_i,
+    RESET_N               => reset_n_i,
+    CLEAR                 => clear_i,
+    CLEAR_N               => clear_n_i,
+    CLK_125               => clk_sys,
+    -- FIFO interface RX
+    FIFO_FULL_IN          => ul_rx_fifofull,
+    FIFO_WR_OUT           => ul_rx_data(9),
+    FIFO_DATA_OUT         => ul_rx_data(8 downto 0),
+    FRAME_START_OUT       => ul_rx_data(10),
+    FRAME_REQ_IN          => ul_rx_frame_req,
+    FRAME_ACK_OUT         => ul_rx_frame_ack,
+    FRAME_AVAIL_OUT       => ul_rx_frame_avail,
+    -- FIFO interface TX           
+    FIFO_WR_IN            => ul_tx_data_q(9),
+    FIFO_DATA_IN          => ul_tx_data_q(8 downto 0),
+    FRAME_START_IN        => ul_tx_data_q(10),
+    FIFO_FULL_OUT         => ul_tx_fifofull,
+    --SFP Connection
+    SD_PRSNT_N_IN         => SFP_MOD_0,
+    SD_LOS_IN             => SFP_LOS,
+    SD_TXDIS_OUT          => SFP_TX_DIS,
+    -- Status
+    PCS_AN_READY_OUT      => pcs_an_ready,
+    LINK_ACTIVE_OUT       => link_active,
+    -- Debug
+    STATUS_OUT            => status(7 downto 0),
+    DEBUG_OUT             => open --debug(63 downto 0) 
+  );
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+  
+  debug(7 downto 0)    <= ul_rx_data(7 downto 0);
+  debug(15 downto 8)   <= ul_tx_data_q(7 downto 0);
+  debug(16)            <= ul_rx_data(9);
+  debug(17)            <= ul_tx_data_q(9);
+  debug(18)            <= ul_rx_data(10);
+  debug(19)            <= ul_tx_data_q(10);
+  debug(20) <= ul_rx_data(8);
+  debug(21) <= ul_tx_data_q(8);
+  debug(22) <= ul_rx_frame_req;
+  debug(23) <= ul_rx_frame_ack;
+  debug(24) <= ul_rx_frame_avail;
+  debug(25) <= dl_rx_frame_req(0);
+  debug(26) <= dl_rx_frame_ack(0);
+  debug(27) <= dl_rx_frame_avail(0);
+  debug(28) <= port_sel(0);
+  debug(29) <= ul_rx_fifofull;
+  debug(30) <= ul_tx_fifofull;
+  debug(31) <= scatter_cycle_done;
+  debug(32) <= gather_cycle_done;
+  debug(33) <= clk_sys;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
+  -- scattering: data from uplink is distributed to downlinks
+  THE_SCATTER: entity scatter_ports
+  port map(
+    CLK                       => clk_sys,
+    RESET                     => reset_i,
+    --
+    FIFO_FULL_IN(0 downto 0)  => dl_tx_fifofull(0 downto 0),
+    FIFO_FULL_OUT             => ul_rx_fifofull,
+    FRAME_AVAIL_IN            => ul_rx_frame_avail,
+    FRAME_REQ_OUT             => ul_rx_frame_req,
+    FRAME_ACK_IN              => ul_rx_frame_ack,
+    CYCLE_DONE_OUT            => scatter_cycle_done, --open,
+    --                        
+    DEBUG                     => open
+  );
+
+  THE_GATHER: entity gather_ports
+  port map(
+    CLK                          => clk_sys,
+    RESET                        => reset_i,
+    --
+    FRAME_AVAIL_IN(0 downto 0)   => dl_rx_frame_avail(0 downto 0),
+    FRAME_REQ_OUT(0 downto 0)    => dl_rx_frame_req(0 downto 0),
+    FRAME_ACK_IN(0 downto 0)     => dl_rx_frame_ack(0 downto 0),
+    PORT_SELECT_OUT(0 downto 0)  => port_sel,
+    CYCLE_DONE_OUT               => gather_cycle_done, --open,
+    --
+    DEBUG                        => open
+  );
+
+  THE_QUICK_MUX: process( port_sel, dl_rx_data )
+  begin
+    case port_sel is
+      when b"1"    => ul_tx_data <= dl_rx_data(0);
+      when others  => ul_tx_data <= (others => '0');
+    end case;
+  end process THE_QUICK_MUX;
+  
+  ul_tx_data_q <= ul_tx_data when rising_edge(clk_sys);
+
+---------------------------------------------------------------------------
+-- GbE wrapper without med interface
+---------------------------------------------------------------------------    
+  GBE: entity work.gbe_wrapper_fifo
     generic map(
-      DO_SIMULATION             => 0,
-      INCLUDE_DEBUG             => 0,
-      USE_INTERNAL_TRBNET_DUMMY => 0,
-      USE_EXTERNAL_TRBNET_DUMMY => 0,
-      RX_PATH_ENABLE            => 1,
-      FIXED_SIZE_MODE           => 1,
-      INCREMENTAL_MODE          => 1,
-      FIXED_SIZE                => 100,
-      FIXED_DELAY_MODE          => 1,
-      UP_DOWN_MODE              => 0,
-      UP_DOWN_LIMIT             => 100,
-      FIXED_DELAY               => 100,
-
-      NUMBER_OF_GBE_LINKS       => 1,
-      LINKS_ACTIVE              => "0001",
-
-      LINK_HAS_READOUT          => "0000",
-      LINK_HAS_SLOWCTRL         => "0001",
-      LINK_HAS_DHCP             => "0001",
-      LINK_HAS_ARP              => "0001",
-      LINK_HAS_PING             => "0001",
-      LINK_HAS_FWD              => "0000"
+      LINK_HAS_READOUT          => '0',
+      LINK_HAS_SLOWCTRL         => '1',
+      LINK_HAS_DHCP             => '1',
+      LINK_HAS_ARP              => '1',
+      LINK_HAS_PING             => '1',
+      LINK_HAS_FWD              => '0'
     )
     port map(
-      CLK_SYS_IN               => clk_sys,
-      CLK_125_IN               => CLK_125,
+      CLK_125_IN               => clk_sys,
       RESET                    => reset_i,
-      GSR_N                    => GSR_N,
+      GSR_N                    => reset_n_i,
       -- Trigger
       TRIGGER_IN               => '0',
-      -- SFP
-      SD_PRSNT_N_IN(0)         => SFP_MOD_0,
-      SD_LOS_IN(0)             => SFP_LOS,
-      SD_TXDIS_OUT(0)          => SFP_TX_DIS,
+      -- we connect to FIFO interface directly
+      -- FIFO interface RX
+      FIFO_DATA_OUT            => dl_rx_data(0)(8 downto 0),
+      FIFO_FULL_IN             => ul_tx_fifofull,
+      FIFO_WR_OUT              => dl_rx_data(0)(9),
+      FRAME_REQ_IN             => dl_rx_frame_req(0),
+      FRAME_ACK_OUT            => dl_rx_frame_ack(0),
+      FRAME_AVAIL_OUT          => dl_rx_frame_avail(0),
+      FRAME_START_OUT          => dl_rx_data(0)(10),
+      -- FIFO interface TX
+      FIFO_FULL_OUT            => dl_tx_fifofull(0),
+      FIFO_WR_IN               => ul_rx_data(9),
+      FIFO_DATA_IN             => ul_rx_data(8 downto 0),
+      FRAME_START_IN           => ul_rx_data(10),
+      --
+      PCS_AN_READY_IN          => link_active, --pcs_an_ready,
+      LINK_ACTIVE_IN           => link_active,
+      --                        
       -- unique adresses
       MC_UNIQUE_ID_IN          => timer.uid,
       MY_TRBNET_ADDRESS_IN     => timer.network_address,
@@ -193,22 +333,29 @@ begin
       GSC_REPLY_DATA_IN        => gsc_reply_data,       
       GSC_REPLY_PACKET_NUM_IN  => gsc_reply_packet_num, 
       GSC_REPLY_READ_OUT       => gsc_reply_read,       
-      GSC_BUSY_IN              => gsc_busy,
+      GSC_BUSY_IN              => gsc_busy,            
       -- readout
-      BUS_IP_RX                => busgbeip_rx, -- registers inside GbE
-      BUS_IP_TX                => busgbeip_tx, -- registers inside GbE
-      BUS_REG_RX               => busgbereg_rx, -- registers inside GbE
-      BUS_REG_TX               => busgbereg_tx, -- registers inside GbE
+      BUS_IP_RX                => busgbeip_rx,
+      BUS_IP_TX                => busgbeip_tx,
+      BUS_REG_RX               => busgbereg_rx,
+      BUS_REG_TX               => busgbereg_tx,
       -- reset
-      MAKE_RESET_OUT           => reset_via_gbe, -- reset by GbE
-      -- debug and status
-      STATUS_OUT               => status,
-      DEBUG_OUT                => open --debug --open
+      MAKE_RESET_OUT           => reset_via_gbe,
+      -- debug
+      STATUS_OUT               => status(15 downto 8),
+      DEBUG_OUT                => debug(95 downto 64)
     );
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
  
--------------------------------------------------------------------------------
+---------------------------------------------------------------------------
 -- SCTRL endpoint for GbE standalone
--------------------------------------------------------------------------------
+---------------------------------------------------------------------------
   THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
     generic map(
       FIFO_TO_INT_DEPTH            => 6,
@@ -260,17 +407,6 @@ begin
     );
     
   common_stat_reg <= (others => '0');
-
-  debug(3 downto 0)   <= gsc_init_data(3 downto 0);
-  debug(6 downto 4)   <= gsc_init_packet_num; -- is shifted
-  debug(7)            <= gsc_init_dataready;
-  debug(8)            <= gsc_init_read;
-  debug(9)            <= timer.tick_ms; --'0';
-  debug(13 downto 10) <= gsc_reply_data(3 downto 0);
-  debug(16 downto 14) <= gsc_reply_packet_num;
-  debug(17)           <= gsc_reply_dataready;
-  debug(18)           <= gsc_reply_read;
-  debug(19)           <= gsc_busy;
   
 -------------------------------------------------------------------------------
 -- Bus Handler
@@ -349,7 +485,10 @@ begin
   
 --  GPIO                <= (others => '0');
   GPIO(15 downto 14)  <= (others => '0');
-  GPIO(13 downto 0)   <= debug(33 downto 20);
+--  GPIO(13 downto 0)   <= debug(33 downto 20);
+  GPIO(8 downto 0)    <= debug(28 downto 20);
+  GPIO(12 downto 9)   <= debug(71 downto 68);
+  GPIO(13 downto 13)  <= debug(33 downto 33);
 --  GPIO                <= (others => 'Z');
   
   TIMING_TEST         <= reset_via_gbe; --'0';
@@ -359,7 +498,7 @@ begin
 -------------------------------------------------------------------------------
   LED_SFP_GREEN   <= not (status(0) and status(1) and status(2)); --'0';
   LED_SFP_YELLOW  <= not status(5); --'0';
-  LED_SFP_RED     <= not status(8); --'0';
+  LED_SFP_RED     <= not status(6); --'0';
   LED(3)          <= not additional_reg(31); --'0';
   LED(2)          <= not additional_reg(30); --'0';
   LED(1)          <= not additional_reg(29); --'0';