LOCATE COMP "TRIGGER_OUT" SITE "V7";
IOBUF PORT "TRIGGER_OUT" IO_TYPE=LVDS25 ;
-LOCATE COMP "TRIGGER_OUT2" SITE "W8"; #was EXT_TRIG_4
+LOCATE COMP "TRIGGER_OUT2" SITE "W4"; #was EXT_TRIG_2
+LOCATE COMP "TRIGGER_OUT3" SITE "W8"; #was EXT_TRIG_4
IOBUF PORT "TRIGGER_OUT2" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_OUT3" IO_TYPE=LVDS25 ;
#Additional lines on Trigger-RJ-45
LOCATE COMP "TRIGGER_EXT_2" SITE "W2";
-LOCATE COMP "TRIGGER_EXT_3" SITE "W4"; #was EXT_TRIG_2
+# LOCATE COMP "TRIGGER_EXT_3" SITE "W4"; #was EXT_TRIG_2
#LOCATE COMP "TRIGGER_EXT_4" SITE "W8"; #was EXT_TRIG_4
DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ;
IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25;
TOPNAME => "trb3_central_gbe",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
+lattice_path => '/d/jspc29/lattice/diamond/3.11_x64',
synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
# synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
-# synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
+synplify_command => "/d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier",
nodelist_file => '../nodes_lxhadeb07.txt',
-- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45
TRIGGER_OUT : out std_logic; --trigger to second input of fan-out
TRIGGER_OUT2 : out std_logic; --trigger output on RJ45
+ TRIGGER_OUT3 : out std_logic; --trigger output on RJ45
--Serdes
CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible
gen_no_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
- TRIGGER_OUT2 <= TRIGGER_RIGHT;
+ TRIGGER_OUT3 <= TRIGGER_RIGHT;
end generate;
gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
TRIGGER_OUT2 <= trig_gen_out_i(0);
- CLK_EXT(3) <= trig_gen_out_i(1);
- CLK_EXT(4) <= trig_gen_out_i(2);
+ TRIGGER_OUT3 <= trig_gen_out_i(1);
+ CLK_EXT(3) <= trig_gen_out_i(2);
+ CLK_EXT(4) <= trig_gen_out_i(3);
end generate;
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