\section{TRB3 \& AddOn}
-I/O from the TRB is provided via an 4conn-AddOn with four connectors and 20 wire pairs each.
-Alternatively, the ADA-AddOn provides two connectors with 40 wire pairs each. Appendix
-\ref{ADApinout} shows, that the pin-out of the 4conn-AddOn fits better with respect to the
-possibility to connect two identical CB to one FPGA.
+I/O from the TRB is provided via an ADA-AddOn with two connectors with 40 wire pairs each.
+Appendix \ref{ADApinout} shows, that the pin-out of the 4conn-AddOn fits better with respect to the
+possibility to connect two identical CB to one FPGA, but the available connections on the ADA AddOn
+are sufficient.
Using the standard AddOns from GSI with their standard connector (KEL 8925E series) saves us from
building new boards.
The 40-pair twisted pair flat cable used for TDC applications at GSI provides all connectivity for
one converter board. The cables can be made in any length, so we can do studies about the maximum
length. \final{The final setup will most likely use different cables with better shielding and
-improved handling.} Cables as well as connectors will be bought by GSI.
+improved handling.} Cables as well as connectors will be bought by GSI and are available in
+Frankfurt.
Table \ref{iocount} gives a rough count of necessary I/O. The final number of connections required
will strongly depend on the realization of the converter board, mainly with respect to the data
Note that this setup is for M26 sensors only where we will not have any ladders larger than 2
sensors. The number of I/O for the final sensor will be different.
-The available AddOns for TRB3 have up to 15 differential outputs for each CB available. If we
-connect the power supply and switch IC via single ended connections, the number of required
-differential ports fits this number.
+Not all signals need a direct connection to the FPGA. To reduce the number of lines, all ADC, DAC
+and switches are operated by a microcontroller on the CB. Communication with the FPGA is
+implemented as SPI or UART.
\begin{table}[hbtp]
\centering
\hline
JTAG: TDI,TMS,TCK, TDO & 1 & 3 & 0 & 0\\
Sensor Data: Clock, Marker, 2x Data per sensor & 0 & 0 & 8 & 0\\
-Sensor Control: Clock, Start, Reset. & 0 & 3 (2) & 0 & 0\\
-ADC for voltages and currents (SPI) & 0 & 2 & 2 & 2 \\
-Voltage and JTAG switch (Bus) & 0 & 3 (3) & 0 & 1 (1) \\
-DAC & 0 & 3 (3) & 0 & 0 \\
-Fast Overcurrent Sense & 0 & 0 & 2 (2) & 0 \\
+Sensor Control: Clock, Start, Reset. & 0 & 3 & 0 & 0\\
+ADC for voltages and currents (SPI) & 0 & 0 & (1) & (3) \\
+Voltage and JTAG switch (Bus) & 0 & 0 & 0 & (4) \\
+DAC & 0 & (3) & 0 & 0 \\
+Fast Overcurrent Sense & 0 & 0 & 2 & 0 \\
+Microcontoller & 4 & 3 & 0 & 0 \\
\hline
-Total & 1 & 14 (8) & 12 (2) & 3 (1)\\
-Proposal for 4conn-AddOn & 1 & 11 + 3 & 12 & 2 + 1 \\
+Total & 5 & 9 (3) & 10 (1) & 0 (7)\\
\end{tabularx}
-\caption{Inputs/Outputs from the FPGA to the converter board. The number in
-parentheses shows the number of I/O that could be replaced by a non-differential connection.}
+\caption{Inputs/Outputs from the FPGA to the converter board. Numbers in parantheses are signals
+operated by the microcontroller which are not connected to the FPGA.}
\label{iocount}
\end{table}
sensor (i.e. analog and digital VDD as well as the clamping voltage), the 8 internally generated
bias voltages, the temperature and ground sense.
-The temperature measurement needs an external differential amplification. The signal of the
-temperature diode can only be measured using a sense line for the actual ground level on the sensor
-with a dedicated sense wire. The amplifier has to work on the difference between this ground sense
-wire and the output of the temperature diode. This could also be implemented using a differential
-ADC channel.
+The signal of the temperature diode can only be measured using a sense line for the actual ground
+level on the sensor with a dedicated sense wire. This is provided by the ADC.
The 8 VDiscr signals must be analyzed both single ended and differential\footnote{The voltages
-are labeled 1A-1D and 2A-2D. We need both the absolute value of the voltages ($\approx$2V) as well
-as the differences between 1A-2A, 1B-2B etc. These are in the order of $\pm$ 32 mV.}. I.e. we should
-use a ADC that can switch input pairs from single ended to differential.
-
-In total, 16 ADC channels are needed per sensor. The on-board ADC should provide about 200 kSPS,
-14-16 Bit resolution and a SPI (or similar) interface. A candidate is LTC1863L.
+are labeled 1A-1D and 2A-2D. We need both the absolute value of the voltages '2' ($\approx$2V) as
+well as the differences between 1A-2A, 1B-2B etc. These are in the order of $\pm$ 32 mV.}.
+A instrumentation amplifier provides the differential amplification. Combined with an analog
+multiplexer, only two ADC channels are required for this.
+In total, 8 ADC channels are needed per sensor. The on-board ADC should provide about 200 kSPS,
+14-16 Bit resolution and a SPI (or similar) interface. A candidate is LTC1867L.
If necessary, an external monitoring board or oscilloscope can be connected for testing purposes.
Such a TRB3-AddOn is currently in preparation at GSI (52 channels, 12 Bit, 40 MSPS).
-Current sensing can be implemented with dedicated current monitors, e.g. TSC101 to reduce count of
-components. ZXCT1022 would be available from GSI for free.
+Current sensing is implemented with dedicated current monitors, e.g. ZXCT1022 are available
+from GSI for free.
For latch-up protection, fast discriminators with settable threshold (via DAC) provide a logical
signal to the FPGA about the current status of the current levels. Necessary action is taken by the
\subsection{Board Control}
-All voltages are switchable from FPGA. The JTAG chain needs the option to disable individual
-sensors. Both features can make use of a 74HC259 IC to reduce number of lines.
+All voltages are switchable from FPGA. The JTAG chain and sensor clock need the option to disable
+individual sensors, totaling in four signals per sensor.
For clamping voltages and current monitoring thresholds 4 configurable voltages are necessary per
sensor. The clamping can be provided by the previous method where it can be changed with a
-\subsection{Connectivity}
-All communication to the TRB3 should be differential, maybe despite some static signals. Test
-pads for most signals should be added to connect external, more precise instruments.
+\subsection{Connectivity}
+All communication to the TRB3 should be differential. Test pads for most signals should be added to
+connect external, more precise instruments.
All signals from and to the sensor should be fed through LVDS buffers to reduce the load on the
sensors' output drivers and to improve signal quality.
\subsection{Power Supply}
-The CB needs to generate three voltages for each sensor. They should be independent on the board,
-but as a test feature, one block should be able to serve both connected sensors. That is, provide
-jumpers to bridge power supplies of both sensors to test running several sensors in parallel on all
-three voltages.
+The CB needs to generate three voltages for each sensor.
Estimated power consumption of the converter board (per sensor):
\begin{itemize*}
\item VDD Analog: 3.3~V, 170~mA
\item VDD Digital: 3.3~V, 60 - 100~mA
- \item V Clamping: $\approx$ 0~V, 2~mA
+ \item V Clamping: $\approx$ 2.1~V, <1~uA
\item VCC Board: 3.3~V, t.b.d.~mA
\end{itemize*}
-To improve the noise environment and the stability of voltages, linear regulators can be used.
-Using a supply voltage of e.g. 4~V for the CB would result in an estimated 0.5~W higher power loss
-on the board as compared to switching converters. This seems acceptable since cooling with fans
-will be possible (if needed) even in the final set-up with many sensors.
-
-
+The clamping voltage can be produced in two ways: A potentiometer or an output from the DAC. Both
+are buffered by an OpAmp before sent to the Front-end board where additional methods are foreseen
+for testing purposes.
+\subsection{Micro-controller}
+ADC, DAC and Switches are controlled by a STM32F103RC micro-controller.
\subsection{Other Remarks}
\begin{itemize*}
The form-factor of the FEB will be similar to the current one, without the two connectors on the
short sides and with an additional broad connector on the side towards the CB.
+Clamping can be generated in different ways:
+\begin{itemize*}
+ \item As coming from the CB, filtered with a large capacity, a series resistor of roughly 1k and
+an additional termination resistor of 1k.
+ \item From a voltage divider on the front-end board (keeps ratio between GNDA/VCCA and Vclp stable)
+ \item With a current source relative to GNDA (keeps the absolute value of Vclp stable)
+ \item With a current source relative to VCCA (keeps the difference to VCCA stable)
+\end{itemize*}
+
+
+
\subsection{Jtag}
The switches for bridging of sensors will be located on the CB as before, so no active
components are necessary for Jtag. \discuss{Termination might be foreseen if necessary}. Using
final board and there is no harm if such a circuit fails.
+
\section{Cable FEB to Sensors}
There is no need to develop a new sensor flex print cable at the current stage. The final length of
this cable is likely to be about 15 cm.
FPGA. Unfortunately, pin-out at the FPGA of the two connectors of the AddOn is slightly different.
Hence, there are 12 differential outputs available on both connectors only.
-The better choice is to use the 4-conn AddOn with four 40-pin connectors and slightly shuffled
-connections on the FPGA if pin-out fits better. One CB can be connected to ports 1 and 3, the other
-to 2 and 4. In total, this yields 15 differential outputs.
-An additional ground cable is required between the power supplies for the CB and the stack of TRBs.
+\begin{table}[ht]
+\small
+ \centering
+\begin{tabular}{c|c|c|c|cc|c|c}
+ & \multicolumn{2}{c|}{\textbf{single}} & \multicolumn{3}{c|}{\textbf{differ.}} &
+\multicolumn{2}{c}{\textbf{Groups}}\\
+\textbf{Pair} & \textbf{I} & \textbf{O} & \textbf{I} & \multicolumn{2}{c|}{\textbf{O}} & \textbf{Con
+1} & \textbf{Con 2}\\
+\hline
+1 & X & X & X & -- & X & 0 & 0 \\
+2 & X & X & X & -- & X & 0 & 0 \\
+3 & X & X & X & X & -- & 0 & 0 C \\
+4 & X & X & X & -- & -- & 0 C & 0 \\
+5 & X & X & X & X & X & 0 & 0 \\
+6 & X & - & X & X & -- & 0 & 0 \\
+7 & X & X & X & -- & -- & 1 & 1 \\
+8 & X & X & X & X & X & 1 & 1 \\
+9 & X & X & X & -- & X & 1 & 1 \\
+10 & X & X & X & -- & -- & 1 C & 1 C \\
+11 & X & X & X & X & X & 1 & 1 \\
+12 & X & X & X & X & -- & 1 & 1 \\
+13 & X & X & X & -- & X & 2 & 2 \\
+14 & X & X & X & X & -- & 2 & 2 \\
+15 & X & X & X & -- & X & 2 & 2 \\
+16 & X & X & X & -- & -- & 2 C & 2 C \\
+17 & X & X & X & -- & -- & 3 & 3 \\
+18 & X & X & X & X & X & 3 & 3 \\
+19 & X & X & X & X & -- & 3 & 3 \\
+20 & X & X & X & -- & -- & 3 C & 3 C \\
+21 & X & X & X & -- & -- & 3 & 3 \\
+22 & X & X & X & X & X & 3 & 3 \\
+23 & X & X & X & -- & -- & 4 & 4 \\
+24 & X & X & X & X & X & 4 & 4 \\
+25 & X & X & X & -- & X & 4 & 4 \\
+26 & X & X & X & -- & -- & 4 C & 4 C \\
+27 & X & X & X & X & -- & 4 & 4 \\
+28 & X & X & X & X & X & 4 & 4 \\
+29 & X & X & X & -- & -- & 5 & 5 \\
+30 & X & X & X & X & X & 5 & 5 \\
+31 & X & X & X & X & X & 5 & 5 \\
+32 & X & X & X & -- & -- & 5 C & 5 C \\
+33 & - & - & - & -- & -- & GND & GND \\
+34 & X & X & X & -- & -- & 6 C & 2 \\
+35 & X & X & X & X & X & 6 & 2 \\
+36 & X & X & X & X & X & 6 & 5 \\
+37 & X & X & X & X & X & 6 & 5 \\
+38 & - & - & - & -- & -- & F5 & F5 \\
+39 & X & - & X & -- & -- & Spare & Spare \\
+40 & - & - & - & -- & -- & F5 & F5 \\
+\end{tabular}
+\caption{Pin-out of ADA AddOn and cable between FPGA and CB.}
+\end{table}
%
% \begin{table}[ht]
% \small
% \centering
-% \begin{tabular}{c|c|c|c|cc|c|c}
-% & \multicolumn{2}{c|}{\textbf{single}} & \multicolumn{3}{c|}{\textbf{differ.}} &
-% \multicolumn{2}{c}{\textbf{Groups}}\\
-% \textbf{Pair} & \textbf{I} & \textbf{O} & \textbf{I} & \multicolumn{2}{c|}{\textbf{O}} & \textbf{Con
-% 1} & \textbf{Con 2}\\
+% \begin{tabular}{c|c|cc|cc|c|c|c|c}
+% & \textbf{single} & \multicolumn{4}{c|}{\textbf{differ. Out}}
+% &
+% \multicolumn{4}{c}{\textbf{Groups}}\\
+% \textbf{Pair} & \textbf{Out} &
+% \textbf{C1} & \textbf{C2} &\textbf{C3} &\textbf{C4} &\textbf{C1} & \textbf{C2} &
+% \textbf{C3} & \textbf{C4}\\
% \hline
-% 1 & X & X & X & -- & X & 0 & 0 \\
-% 2 & X & X & X & -- & X & 0 & 0 \\
-% 3 & X & X & X & X & -- & 0 & 0 C \\
-% 4 & X & X & X & -- & -- & 0 C & 0 \\
-% 5 & X & X & X & X & X & 0 & 0 \\
-% 6 & X & - & X & X & -- & 0 & 0 \\
-% 7 & X & X & X & -- & -- & 1 & 1 \\
-% 8 & X & X & X & X & X & 1 & 1 \\
-% 9 & X & X & X & -- & X & 1 & 1 \\
-% 10 & X & X & X & -- & -- & 1 C & 1 C \\
-% 11 & X & X & X & X & X & 1 & 1 \\
-% 12 & X & X & X & X & -- & 1 & 1 \\
-% 13 & X & X & X & -- & X & 2 & 2 \\
-% 14 & X & X & X & X & -- & 2 & 2 \\
-% 15 & X & X & X & -- & X & 2 & 2 \\
-% 16 & X & X & X & -- & -- & 2 C & 2 C \\
-% 17 & X & X & X & -- & -- & 3 & 3 \\
-% 18 & X & X & X & X & X & 3 & 3 \\
-% 19 & X & X & X & X & -- & 3 & 3 \\
-% 20 & X & X & X & -- & -- & 3 C & 3 C \\
-% 21 & X & X & X & -- & -- & 3 & 3 \\
-% 22 & X & X & X & X & X & 3 & 3 \\
-% 23 & X & X & X & -- & -- & 4 & 4 \\
-% 24 & X & X & X & X & X & 4 & 4 \\
-% 25 & X & X & X & -- & X & 4 & 4 \\
-% 26 & X & X & X & -- & -- & 4 C & 4 C \\
-% 27 & X & X & X & X & -- & 4 & 4 \\
-% 28 & X & X & X & X & X & 4 & 4 \\
-% 29 & X & X & X & -- & -- & 5 & 5 \\
-% 30 & X & X & X & X & X & 5 & 5 \\
-% 31 & X & X & X & X & X & 5 & 5 \\
-% 32 & X & X & X & -- & -- & 5 C & 5 C \\
-% 33 & - & - & - & -- & -- & GND & GND \\
-% 34 & X & X & X & -- & -- & 6 C & 2 \\
-% 35 & X & X & X & X & X & 6 & 2 \\
-% 36 & X & X & X & X & X & 6 & 5 \\
-% 37 & X & X & X & X & X & 6 & 5 \\
-% 38 & - & - & - & -- & -- & F5 & F5 \\
-% 39 & X & - & X & -- & -- & Spare & Spare \\
-% 40 & - & - & - & -- & -- & F5 & F5 \\
+% 1 & X & -- & -- & X & -- & 0 & 0 & 0 & 0 \\
+% 2 & X & -- & X & X & X & 0 & 0 & 0 & 0 \\
+% 3 & X & X & X & -- & -- & 0 & 0 & 0 C & 0 \\
+% 4 & X & -- & -- & -- & -- & 0 C & 0 C & 0 & 0 C \\
+% 5 & X & X & -- & X & -- & 0 & 0 & 0 & 0 \\
+% 6 & --& X & X & -- & X & 0 & 0 & 0 & 0 \\
+% 7 & X & -- & -- & -- & -- & 1 & 1 & 1 & 1 \\
+% 8 & X & X & X & X & X & 1 & 1 & 1 & 1 \\
+% 9 & X & -- & -- & X & X & 1 & 1 & 1 & 1 \\
+% 10 & X & -- & -- & -- & -- & 1 C & 1 C & 1 C & 1 C \\
+% 11 & X & X & X & X & -- & 1 & 1 & 1 & 1 \\
+% 12 & X & X & X & -- & X & 1 & 1 & 1 & 1 \\
+% 13 & X & -- & -- & X & -- & 2 & 2 & 2 & 2 \\
+% 14 & X & -- & -- & -- & X & 2 & 2 C & 2 & 2 \\
+% 15 & X & -- & -- & X & X & 2 C & 2 & 2 & 2 \\
+% 16 & X & -- & -- & -- & -- & 2 & 3 & 2 C & 2 C \\
+% 17 & X & -- & -- & -- & -- & & & & \\
+% 18 & X & X & X & X & X & & & & \\
+% 19 & X & X & X & X & X & & & & \\
+% 20 & X & X & X & X & X & & & & \\
+%
% \end{tabular}
-% \caption{Pin-out of ADA AddOn and cable between FPGA and CB.}
+% \caption{Pin-out of 4-conn AddOn and cable between FPGA and CB. First CB
+% connects to C1/C3, second board to C2/C4.}
% \end{table}
-\begin{table}[ht]
-\small
- \centering
-\begin{tabular}{c|c|cc|cc|c|c|c|c}
- & \textbf{single} & \multicolumn{4}{c|}{\textbf{differ. Out}}
-&
-\multicolumn{4}{c}{\textbf{Groups}}\\
-\textbf{Pair} & \textbf{Out} &
-\textbf{C1} & \textbf{C2} &\textbf{C3} &\textbf{C4} &\textbf{C1} & \textbf{C2} &
-\textbf{C3} & \textbf{C4}\\
-\hline
-1 & X & -- & -- & X & -- & 0 & 0 & 0 & 0 \\
-2 & X & -- & X & X & X & 0 & 0 & 0 & 0 \\
-3 & X & X & X & -- & -- & 0 & 0 & 0 C & 0 \\
-4 & X & -- & -- & -- & -- & 0 C & 0 C & 0 & 0 C \\
-5 & X & X & -- & X & -- & 0 & 0 & 0 & 0 \\
-6 & --& X & X & -- & X & 0 & 0 & 0 & 0 \\
-7 & X & -- & -- & -- & -- & 1 & 1 & 1 & 1 \\
-8 & X & X & X & X & X & 1 & 1 & 1 & 1 \\
-9 & X & -- & -- & X & X & 1 & 1 & 1 & 1 \\
-10 & X & -- & -- & -- & -- & 1 C & 1 C & 1 C & 1 C \\
-11 & X & X & X & X & -- & 1 & 1 & 1 & 1 \\
-12 & X & X & X & -- & X & 1 & 1 & 1 & 1 \\
-13 & X & -- & -- & X & -- & 2 & 2 & 2 & 2 \\
-14 & X & -- & -- & -- & X & 2 & 2 C & 2 & 2 \\
-15 & X & -- & -- & X & X & 2 C & 2 & 2 & 2 \\
-16 & X & -- & -- & -- & -- & 2 & 3 & 2 C & 2 C \\
-17 & X & -- & -- & -- & -- & & & & \\
-18 & X & X & X & X & X & & & & \\
-19 & X & X & X & X & X & & & & \\
-20 & X & X & X & X & X & & & & \\
-
-\end{tabular}
-\caption{Pin-out of 4-conn AddOn and cable between FPGA and CB. First CB
-connects to C1/C3, second board to C2/C4.}
-\end{table}
-
-
\input{intermediatetrb3}
jspc29 / mvd_docu.git / commitdiff