Correction to the ex trigger mode operation in TDC

diff --git a/trb3/TdcFeatures.tex b/trb3/TdcFeatures.tex
index 0bebb138fec65eeb6e6daf41233bd36a45395e93..6dffe20c6aef5d3ab7348b5e63c2d6ead684be36 100644 (file)
--- a/trb3/TdcFeatures.tex
+++ b/trb3/TdcFeatures.tex
@@ -21,4 +21,5 @@ Trigger mode is controlled by register 0xc800 bit 12. If it is set to triggered
 mode ('1'), the epoch and coarse counters are reset after each trigger
 window. If this bit is set to trigger-less mode ('0'), the epoch and coarse
 counters are never reset, unless there is a system wide reset. They will run
-until they have an overflow.
+until they have an overflow. \textbf{This feature is disabled the after tdc 
+version 2.0.0}