lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1710\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.11_x64',
-synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
+synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/',
nodelist_file => '../nodelist_frankfurt.txt',
pinout_file => 'dbo',
BLOCK PATH TO PORT "LED*";
BLOCK PATH TO PORT "PROGRAMN";
-FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
-FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+# FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
REGION "MEDIA" "R57C34D" 13 30;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
-UGROUP "TDC0" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC1" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC2" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC3" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC4" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC5" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC6" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC7" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC8" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC9" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC10" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC11" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC12" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC13" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC14" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC15" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC16" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC17" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC18" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC19" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC20" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC21" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC22" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC23" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC24" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC25" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC26" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC27" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC28" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC29" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC30" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC31" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC32" BBOX 1 2
- BLKNAME GND;
-
-
-
-LOCATE UGROUP "TDC0" SITE "R59C86D" ;
-LOCATE UGROUP "TDC0s" SITE "R59C84D" ;
-
-LOCATE UGROUP "TDC1" SITE "R62C86D" ;
-LOCATE UGROUP "TDC1s" SITE "R62C84D" ;
-
-LOCATE UGROUP "TDC2" SITE "R63C86D" ;
-LOCATE UGROUP "TDC2s" SITE "R63C84D" ;
-
-LOCATE UGROUP "TDC3" SITE "R36C86D" ;
-LOCATE UGROUP "TDC3s" SITE "R36C84D" ;
-
-LOCATE UGROUP "TDC4" SITE "R42C86D" ;
-LOCATE UGROUP "TDC4s" SITE "R42C84D" ;
-
-LOCATE UGROUP "TDC5" SITE "R68C86D" ;
-LOCATE UGROUP "TDC5s" SITE "R68C84D" ;
-
-LOCATE UGROUP "TDC6" SITE "R65C86D" ;
-LOCATE UGROUP "TDC6s" SITE "R65C84D" ;
-
-LOCATE UGROUP "TDC7" SITE "R45C86D" ;
-LOCATE UGROUP "TDC7s" SITE "R45C84D" ;
-
-LOCATE UGROUP "TDC8" SITE "R29C86D" ;
-LOCATE UGROUP "TDC8s" SITE "R29C84D" ;
-
-LOCATE UGROUP "TDC9" SITE "R26C86D" ;
-LOCATE UGROUP "TDC9s" SITE "R26C84D" ;
-
-LOCATE UGROUP "TDC10" SITE "R32C86D" ;
-LOCATE UGROUP "TDC10s" SITE "R32C84D" ;
-
-LOCATE UGROUP "TDC11" SITE "R25C86D" ;
-LOCATE UGROUP "TDC11s" SITE "R25C84D" ;
-
-LOCATE UGROUP "TDC12" SITE "R32C86D" ;
-LOCATE UGROUP "TDC12s" SITE "R32C84D" ;
-
-LOCATE UGROUP "TDC13" SITE "R23C86D" ;
-LOCATE UGROUP "TDC13s" SITE "R23C84D" ;
-
-LOCATE UGROUP "TDC14" SITE "R36C86D" ;
-LOCATE UGROUP "TDC14s" SITE "R36C84D" ;
-
-LOCATE UGROUP "TDC15" SITE "R14C86D" ;
-LOCATE UGROUP "TDC15s" SITE "R14C84D" ;
-
-LOCATE UGROUP "TDC16" SITE "R62C3D" ;
-LOCATE UGROUP "TDC16s" SITE "R62C5D" ;
-
-LOCATE UGROUP "TDC17" SITE "R65C3D" ;
-LOCATE UGROUP "TDC17s" SITE "R65C5D" ;
-
-LOCATE UGROUP "TDC18" SITE "R41C3D" ;
-LOCATE UGROUP "TDC18s" SITE "R41C5D" ;
-
-LOCATE UGROUP "TDC19" SITE "R68C3D" ;
-LOCATE UGROUP "TDC19s" SITE "R68C5D" ;
-
-LOCATE UGROUP "TDC20" SITE "R63C3D" ;
-LOCATE UGROUP "TDC20s" SITE "R63C5D" ;
-
-LOCATE UGROUP "TDC21" SITE "R38C3D" ;
-LOCATE UGROUP "TDC21s" SITE "R38C5D" ;
-
-LOCATE UGROUP "TDC22" SITE "R36C3D" ;
-LOCATE UGROUP "TDC22s" SITE "R36C5D" ;
-
-LOCATE UGROUP "TDC23" SITE "R35C3D" ;
-LOCATE UGROUP "TDC23s" SITE "R35C5D" ;
-
-LOCATE UGROUP "TDC24" SITE "R12C3D" ;
-LOCATE UGROUP "TDC24s" SITE "R12C5D" ;
-
-LOCATE UGROUP "TDC25" SITE "R11C3D" ;
-LOCATE UGROUP "TDC25s" SITE "R11C5D" ;
-
-LOCATE UGROUP "TDC26" SITE "R32C3D" ;
-LOCATE UGROUP "TDC26s" SITE "R32C5D" ;
-
-LOCATE UGROUP "TDC27" SITE "R14C3D" ;
-LOCATE UGROUP "TDC27s" SITE "R14C5D" ;
-
-LOCATE UGROUP "TDC28" SITE "R26C3D" ;
-LOCATE UGROUP "TDC28s" SITE "R26C5D" ;
-
-LOCATE UGROUP "TDC29" SITE "R15C3D" ;
-LOCATE UGROUP "TDC29s" SITE "R15C5D" ;
-
-LOCATE UGROUP "TDC30" SITE "R17C3D" ;
-LOCATE UGROUP "TDC30s" SITE "R17C5D" ;
-
-LOCATE UGROUP "TDC31" SITE "R23C3D" ;
-LOCATE UGROUP "TDC31s" SITE "R23C5D" ;
-
-LOCATE UGROUP "TDC32" SITE "R12C86D" ;
-LOCATE UGROUP "TDC32s" SITE "R12C84D" ;
-
-
-UGROUP "TDC0s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC1s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC2s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC3s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC4s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC5s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC6s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC7s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC8s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC9s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC10s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC11s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC12s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC13s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC14s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC15s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC16s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC17s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC18s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC19s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC20s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC21s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC22s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC23s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC24s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC25s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC26s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC27s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC28s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC29s" BBOX 1 2
- BLKNAME GND;
-
-UGROUP "TDC30s" BBOX 1 2
- BLKNAME GND;
-UGROUP "TDC31s" BBOX 1 2
- BLKNAME GND;
-UGROUP "TDC32s" BBOX 1 2
- BLKNAME GND;
+# USE PRIMARY NET THE_TDC/calibration_pulse ;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.0.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.1.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.2.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.3.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.4.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.5.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.6.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.7.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.8.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.9.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.10.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.11.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.12.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.13.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.14.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.15.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.16.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.17.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.18.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.19.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.20.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.21.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.22.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.23.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.24.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.25.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.26.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.27.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.28.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.29.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.30.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.31.THE_CHANNEL/gated_inp 100;
+
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/gated_inp" 0.500000 ns ;
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_INP/InpLut" SITE "R59C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_FF/FFregs" SITE "R59C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_FFF/FFregs" SITE "R59C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_FF2/FFregs2" SITE "R59C82D";##
+PROHIBIT SITE "R59C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_INP/InpLut" SITE "R61C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_FF/FFregs" SITE "R61C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_FFF/FFregs" SITE "R61C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_FF2/FFregs2" SITE "R61C82D";##
+PROHIBIT SITE "R61C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_INP/InpLut" SITE "R63C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_FF/FFregs" SITE "R63C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_FFF/FFregs" SITE "R63C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_FF2/FFregs2" SITE "R63C82D";##
+PROHIBIT SITE "R63C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_INP/InpLut" SITE "R39C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_FF/FFregs" SITE "R39C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_FFF/FFregs" SITE "R39C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_FF2/FFregs2" SITE "R39C82D";##
+PROHIBIT SITE "R39C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_INP/InpLut" SITE "R42C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_FF/FFregs" SITE "R42C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_FFF/FFregs" SITE "R42C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_FF2/FFregs2" SITE "R42C82D";##
+PROHIBIT SITE "R42C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_INP/InpLut" SITE "R68C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_FF/FFregs" SITE "R68C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_FFF/FFregs" SITE "R68C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_FF2/FFregs2" SITE "R68C82D";##
+PROHIBIT SITE "R68C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_INP/InpLut" SITE "R65C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_FF/FFregs" SITE "R65C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_FFF/FFregs" SITE "R65C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_FF2/FFregs2" SITE "R65C82D";##
+PROHIBIT SITE "R65C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_INP/InpLut" SITE "R44C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_FF/FFregs" SITE "R44C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_FFF/FFregs" SITE "R44C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_FF2/FFregs2" SITE "R44C82D";##
+PROHIBIT SITE "R44C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_INP/InpLut" SITE "R28C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_FF/FFregs" SITE "R28C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_FFF/FFregs" SITE "R28C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_FF2/FFregs2" SITE "R28C82D" ;
+PROHIBIT SITE "R28C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_INP/InpLut" SITE "R27C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_FF/FFregs" SITE "R27C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_FFF/FFregs" SITE "R27C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_FF2/FFregs2" SITE "R27C82D";##
+PROHIBIT SITE "R27C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_INP/InpLut" SITE "R35C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_FF/FFregs" SITE "R35C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_FFF/FFregs" SITE "R35C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_FF2/FFregs2" SITE "R35C82D";##
+PROHIBIT SITE "R35C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_INP/InpLut" SITE "R25C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_FF/FFregs" SITE "R25C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_FFF/FFregs" SITE "R25C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_FF2/FFregs2" SITE "R25C82D";##
+PROHIBIT SITE "R25C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_INP/InpLut" SITE "R31C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_FF/FFregs" SITE "R31C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_FFF/FFregs" SITE "R31C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_FF2/FFregs2" SITE "R31C82D";##
+PROHIBIT SITE "R31C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_INP/InpLut" SITE "R23C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_FF/FFregs" SITE "R23C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_FFF/FFregs" SITE "R23C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_FF2/FFregs2" SITE "R23C82D";##
+PROHIBIT SITE "R23C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_INP/InpLut" SITE "R37C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_FF/FFregs" SITE "R37C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_FFF/FFregs" SITE "R37C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_FF2/FFregs2" SITE "R37C82D";##
+PROHIBIT SITE "R37C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_INP/InpLut" SITE "R15C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_FF/FFregs" SITE "R15C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_FFF/FFregs" SITE "R15C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_FF2/FFregs2" SITE "R15C82D";##
+PROHIBIT SITE "R15C86C";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_INP/InpLut" SITE "R61C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_FF/FFregs" SITE "R61C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_FFF/FFregs" SITE "R61C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_FF2/FFregs2" SITE "R61C8D";
+# PROHIBIT SITE "R61C3B";
+# PROHIBIT SITE "R61C3C";
+# PROHIBIT SITE "R61C4B";
+# PROHIBIT SITE "R61C4C";
+# PROHIBIT SITE "R61C6B";
+# PROHIBIT SITE "R61C6C";
+# PROHIBIT SITE "R61C7B";
+# PROHIBIT SITE "R61C7C";
+PROHIBIT SITE "R61C5C";
+# PROHIBIT SITE "R61C5B";
+# PROHIBIT SITE "R61C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_INP/InpLut" SITE "R65C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_FF/FFregs" SITE "R65C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_FFF/FFregs" SITE "R65C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_FF2/FFregs2" SITE "R65C8D";
+# PROHIBIT SITE "R65C3B";
+# PROHIBIT SITE "R65C3C";
+# PROHIBIT SITE "R65C4B";
+# PROHIBIT SITE "R65C4C";
+# PROHIBIT SITE "R65C6B";
+# PROHIBIT SITE "R65C6C";
+# PROHIBIT SITE "R65C7B";
+# PROHIBIT SITE "R65C7C";
+PROHIBIT SITE "R65C5C";
+# PROHIBIT SITE "R65C5B";
+# PROHIBIT SITE "R65C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_INP/InpLut" SITE "R41C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_FF/FFregs" SITE "R41C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_FFF/FFregs" SITE "R41C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_FF2/FFregs2" SITE "R41C8D";
+# PROHIBIT SITE "R41C3B";
+# PROHIBIT SITE "R41C3C";
+# PROHIBIT SITE "R41C4B";
+# PROHIBIT SITE "R41C4C";
+# PROHIBIT SITE "R41C6B";
+# PROHIBIT SITE "R41C6C";
+# PROHIBIT SITE "R41C7B";
+# PROHIBIT SITE "R41C7C";
+PROHIBIT SITE "R41C5C";
+# PROHIBIT SITE "R41C5B";
+# PROHIBIT SITE "R41C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_INP/InpLut" SITE "R68C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_FF/FFregs" SITE "R68C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_FFF/FFregs" SITE "R68C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_FF2/FFregs2" SITE "R68C8D";
+# PROHIBIT SITE "R68C3B";
+# PROHIBIT SITE "R68C3C";
+# PROHIBIT SITE "R68C4B";
+# PROHIBIT SITE "R68C4C";
+# PROHIBIT SITE "R68C6B";
+# PROHIBIT SITE "R68C6C";
+# PROHIBIT SITE "R68C7B";
+# PROHIBIT SITE "R68C7C";
+PROHIBIT SITE "R68C5C";
+# PROHIBIT SITE "R68C5B";
+# PROHIBIT SITE "R68C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_INP/InpLut" SITE "R63C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_FF/FFregs" SITE "R63C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_FFF/FFregs" SITE "R63C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_FF2/FFregs2" SITE "R63C8D";
+# PROHIBIT SITE "R63C3B";
+# PROHIBIT SITE "R63C3C";
+# PROHIBIT SITE "R63C4B";
+# PROHIBIT SITE "R63C4C";
+# PROHIBIT SITE "R63C6B";
+# PROHIBIT SITE "R63C6C";
+# PROHIBIT SITE "R63C7B";
+# PROHIBIT SITE "R63C7C";
+PROHIBIT SITE "R63C5C";
+# PROHIBIT SITE "R63C5B";
+# PROHIBIT SITE "R63C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_INP/InpLut" SITE "R39C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_FF/FFregs" SITE "R39C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_FFF/FFregs" SITE "R39C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_FF2/FFregs2" SITE "R39C8D";
+# PROHIBIT SITE "R39C3B";
+# PROHIBIT SITE "R39C3C";
+# PROHIBIT SITE "R39C4B";
+# PROHIBIT SITE "R39C4C";
+# PROHIBIT SITE "R39C6B";
+# PROHIBIT SITE "R39C6C";
+# PROHIBIT SITE "R39C7B";
+# PROHIBIT SITE "R39C7C";
+PROHIBIT SITE "R39C5C";
+# PROHIBIT SITE "R39C5B";
+# PROHIBIT SITE "R39C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_INP/InpLut" SITE "R37C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_FF/FFregs" SITE "R37C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_FFF/FFregs" SITE "R37C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_FF2/FFregs2" SITE "R37C8D";
+# PROHIBIT SITE "R37C3B";
+# PROHIBIT SITE "R37C3C";
+# PROHIBIT SITE "R37C4B";
+# PROHIBIT SITE "R37C4C";
+# PROHIBIT SITE "R37C6B";
+# PROHIBIT SITE "R37C6C";
+# PROHIBIT SITE "R37C7B";
+# PROHIBIT SITE "R37C7C";
+PROHIBIT SITE "R37C5C";
+# PROHIBIT SITE "R37C5B";
+# PROHIBIT SITE "R37C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_INP/InpLut" SITE "R35C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_FF/FFregs" SITE "R35C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_FFF/FFregs" SITE "R35C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_FF2/FFregs2" SITE "R35C8D";
+# PROHIBIT SITE "R35C3B";
+# PROHIBIT SITE "R35C3C";
+# PROHIBIT SITE "R35C4B";
+# PROHIBIT SITE "R35C4C";
+# PROHIBIT SITE "R35C6B";
+# PROHIBIT SITE "R35C6C";
+# PROHIBIT SITE "R35C7B";
+# PROHIBIT SITE "R35C7C";
+PROHIBIT SITE "R35C5C";
+# PROHIBIT SITE "R35C5B";
+# PROHIBIT SITE "R35C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_INP/InpLut" SITE "R11C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_FF/FFregs" SITE "R11C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_FFF/FFregs" SITE "R11C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_FF2/FFregs2" SITE "R11C8D";
+# PROHIBIT SITE "R11C3B";
+# PROHIBIT SITE "R11C3C";
+# PROHIBIT SITE "R11C4B";
+# PROHIBIT SITE "R11C4C";
+# PROHIBIT SITE "R11C6B";
+# PROHIBIT SITE "R11C6C";
+# PROHIBIT SITE "R11C7B";
+# PROHIBIT SITE "R11C7C";
+PROHIBIT SITE "R11C5C";
+# PROHIBIT SITE "R11C5B";
+# PROHIBIT SITE "R11C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_INP/InpLut" SITE "R8C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_FF/FFregs" SITE "R8C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_FFF/FFregs" SITE "R8C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_FF2/FFregs2" SITE "R8C8D";
+# PROHIBIT SITE "R8C3B";
+# PROHIBIT SITE "R8C3C";
+# PROHIBIT SITE "R8C4B";
+# PROHIBIT SITE "R8C4C";
+# PROHIBIT SITE "R8C6B";
+# PROHIBIT SITE "R8C6C";
+# PROHIBIT SITE "R8C7B";
+# PROHIBIT SITE "R8C7C";
+PROHIBIT SITE "R8C5C";
+# PROHIBIT SITE "R8C5B";
+# PROHIBIT SITE "R8C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_INP/InpLut" SITE "R32C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_FF/FFregs" SITE "R32C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_FFF/FFregs" SITE "R32C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_FF2/FFregs2" SITE "R32C8D";
+# PROHIBIT SITE "R32C3B";
+# PROHIBIT SITE "R32C3C";
+# PROHIBIT SITE "R32C4B";
+# PROHIBIT SITE "R32C4C";
+# PROHIBIT SITE "R32C6B";
+# PROHIBIT SITE "R32C6C";
+# PROHIBIT SITE "R32C7B";
+# PROHIBIT SITE "R32C7C";
+PROHIBIT SITE "R32C5C";
+# PROHIBIT SITE "R32C5B";
+# PROHIBIT SITE "R32C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_INP/InpLut" SITE "R14C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_FF/FFregs" SITE "R14C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_FFF/FFregs" SITE "R14C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_FF2/FFregs2" SITE "R14C8D";
+# PROHIBIT SITE "R14C3B";
+# PROHIBIT SITE "R14C3C";
+# PROHIBIT SITE "R14C4B";
+# PROHIBIT SITE "R14C4C";
+# PROHIBIT SITE "R14C6B";
+# PROHIBIT SITE "R14C6C";
+# PROHIBIT SITE "R14C7B";
+# PROHIBIT SITE "R14C7C";
+PROHIBIT SITE "R14C5C";
+# PROHIBIT SITE "R14C5B";
+# PROHIBIT SITE "R14C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_INP/InpLut" SITE "R26C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_FF/FFregs" SITE "R26C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_FFF/FFregs" SITE "R26C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_FF2/FFregs2" SITE "R26C8D";
+# PROHIBIT SITE "R26C3B";
+# PROHIBIT SITE "R26C3C";
+# PROHIBIT SITE "R26C4B";
+# PROHIBIT SITE "R26C4C";
+# PROHIBIT SITE "R26C6B";
+# PROHIBIT SITE "R26C6C";
+# PROHIBIT SITE "R26C7B";
+# PROHIBIT SITE "R26C7C";
+PROHIBIT SITE "R26C5C";
+# PROHIBIT SITE "R26C5B";
+# PROHIBIT SITE "R26C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_INP/InpLut" SITE "R16C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_FF/FFregs" SITE "R16C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_FFF/FFregs" SITE "R16C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_FF2/FFregs2" SITE "R16C8D";
+# PROHIBIT SITE "R16C3B";
+# PROHIBIT SITE "R16C3C";
+# PROHIBIT SITE "R16C4B";
+# PROHIBIT SITE "R16C4C";
+# PROHIBIT SITE "R16C6B";
+# PROHIBIT SITE "R16C6C";
+# PROHIBIT SITE "R16C7B";
+# PROHIBIT SITE "R16C7C";
+PROHIBIT SITE "R16C5C";
+# PROHIBIT SITE "R16C5B";
+# PROHIBIT SITE "R16C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_INP/InpLut" SITE "R18C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_FF/FFregs" SITE "R18C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_FFF/FFregs" SITE "R18C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_FF2/FFregs2" SITE "R18C8D";
+# PROHIBIT SITE "R18C3B";
+# PROHIBIT SITE "R18C3C";
+# PROHIBIT SITE "R18C4B";
+# PROHIBIT SITE "R18C4C";
+# PROHIBIT SITE "R18C6B";
+# PROHIBIT SITE "R18C6C";
+# PROHIBIT SITE "R18C7B";
+# PROHIBIT SITE "R18C7C";
+PROHIBIT SITE "R18C5C";
+# PROHIBIT SITE "R18C5B";
+# PROHIBIT SITE "R18C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_INP/InpLut" SITE "R23C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_FF/FFregs" SITE "R23C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_FFF/FFregs" SITE "R23C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_FF2/FFregs2" SITE "R23C8D";
+# PROHIBIT SITE "R23C3B";
+# PROHIBIT SITE "R23C3C";
+# PROHIBIT SITE "R23C4B";
+# PROHIBIT SITE "R23C4C";
+# PROHIBIT SITE "R23C6B";
+# PROHIBIT SITE "R23C6C";
+# PROHIBIT SITE "R23C7B";
+# PROHIBIT SITE "R23C7C";
+PROHIBIT SITE "R23C5C";
+# PROHIBIT SITE "R23C5B";
+# PROHIBIT SITE "R23C5D";
+
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_INP/InpLut" SITE "R12C86D" ;
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_FF/FFregs" SITE "R12C84D" ;
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_FFF/FFregs" SITE "R12C87D" ;
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_FF2/FFregs2" SITE "R12C82D";##
+
+# REGION "TDCLEFT" "R2C16D" 68 4;
+# PROHIBIT REGION "TDCLEFT";
+# REGION "TDCRIGHT" "R2C68D" 68 4;
+# PROHIBIT REGION "TDCRIGHT";
+
+REGION "DECODERLEFT" "R9C2D" 60 10;
+REGION "DECODERRIGHT" "R7C78D" 60 10;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
set_option -symbolic_fsm_compiler 1
set_option -top_module "mdctdc"
set_option -resource_sharing false
+set_option -vhdl2008 true
# map options
set_option -frequency 120
add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
-
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd"
#Flash & Reload, Tools
add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/clocked_tdc_pkg.vhd"
+add_file -vhdl -lib work "../cores/PLL_TDC/PLL_TDC.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/TDC_FF.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/ChannelRegs.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/FFregs.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/FFregs2.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/InpLut.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/Decoder.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/HitBuffer.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/ReadoutHandler.vhd"
+
+
+
add_file -vhdl -lib work "./mdctdc.vhd"
#add_file -fpga_constraint "./synplify.fdc"
attribute syn_useioff of FLASH_SCLK : signal is true;
attribute syn_useioff of FLASH_MOSI : signal is true;
attribute syn_useioff of FLASH_MISO : signal is true;
+ attribute syn_useioff of OUTP : signal is false;
end entity;
signal readout_rx : READOUT_RX;
- signal readout_tx : readout_tx_array_t(0 to 0);
+ signal readout_tx : readout_tx_array_t(0 to 1);
signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX;
signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out : CTRLBUS_RX;
signal timer : TIMERS;
signal led_off : std_logic;
--TDC
- signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1);
+ signal hit_in_i : std_logic_vector(31 downto 0);
signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
+ signal calibration_pulse: std_logic;
+
+ signal dummy_i : std_logic;
begin
REGIO_USE_1WIRE_INTERFACE => c_I2C,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
- DATA_INTERFACE_NUMBER => 1,
+ DATA_INTERFACE_NUMBER => 2,
DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
DATA_BUFFER_WIDTH => 32,
DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
---------------------------------------------------------------------------
monitor_inputs_i <= OUTP(MONITOR_INPUT_NUM-1 downto 0);
trigger_inputs_i <= OUTP(TRIG_GEN_INPUT_NUM-1 downto 0);
- hit_in_i <= OUTP(NUM_TDC_CHANNELS-2 downto 0);
-
+ hit_in_i <= OUTP;
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
LED(0) <= (med2int(0).stat_op(10) or med2int(0).stat_op(11)) and not led_off;
LED(1) <= med2int(0).stat_op(9) and not led_off;
- LED(2) <= FLASH_SELECT and not led_off;
+ LED(2) <= (LVDS(1) or LVDS(0) or dummy_i or FLASH_SELECT) and not led_off;
--------------------------------------------------------------------------
---------------------------------------------------------------------------
PTEN <= "11";
INJ <= additional_reg(19 downto 16); --"0000";
- TEST <= additional_reg(27 downto 24); --"0000";
+ TEST <= additional_reg(27 downto 24) or (calibration_pulse & calibration_pulse & calibration_pulse & calibration_pulse); --"0000";
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
--- THE_TDC : entity work.TDC_FF
--- generic map(
--- CHANNELS => 17
--- )
--- port map(
--- CLK => CLK_125,
--- SYSCLK => clk_sys,
--- RESET_IN => reset_i,
--- SIGNAL_IN => INP(16 downto 0),
---
--- BUS_RX => bustdc_rx,
--- BUS_TX => bustdc_tx,
---
--- READOUT_RX => readout_rx,
--- READOUT_TX => readout_tx
---
--- );
---
---
+THE_TDC : entity work.TDC_FF
+
+ port map(
+ CLK_FAST => CLK_TDC,
+ CLK_SYS => clk_sys,
+ RESET_IN => reset_i,
+ SIGNAL_IN => hit_in_i(31 downto 0),
+ TRIGGER_IN => TRG,
+ CALIBRATION_OUT => calibration_pulse,
+
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx(0 to 1),
+
+ DUMMY => dummy_i
+
+ );
+
+
-------------------------------------------------------------------------------
-- No trigger/data endpoint included
-------------------------------------------------------------------------------
-readout_tx(0).data_finished <= '1';
-readout_tx(0).data_write <= '0';
-readout_tx(0).busy_release <= '1';
+-- readout_tx(0).data_finished <= '1';
+-- readout_tx(0).data_write <= '0';
+-- readout_tx(0).busy_release <= '1';
end architecture;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="mdctdc" device="LFE5UM-45F-8BG381C" default_implementation="mdctdc">
+ <Options/>
+ <Implementation title="mdctdc" dir="mdctdc" description="Automatically generated implemenatation" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="mdctdc" top="mdctdc"/>
+ <Source name="../workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../workdir/version.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../config.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../dirich/cores/pll_240_100/pll_240_100.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../dirich/code/clock_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../vhdlbasics/ecp5/sedcheck.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/trb3sc_tools.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/lcd.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/debuguart.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/uart.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/load_settings.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/spi_master_generic.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3/base/code/input_to_trigger_logic_record.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3/base/code/input_statistics.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_regio_bus_handler_record.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/sci_reader.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/sync/med_sync_control.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp5/pcs.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp5/pcs2.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/bus_register_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/trb_net_i2cwire.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../vhdlbasics/interface/i2c_gstart.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../vhdlbasics/interface/i2c_sendb.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../vhdlbasics/interface/i2c_slim.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../mdctdc.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work" top_module="mdctdc"/>
+ </Source>
+ <Source name="../../cores/PLL_TDC/PLL_TDC.sbx" type="sbx" type_short="SBX">
+ <Options/>
+ </Source>
+ <Source name="../../../clocked_tdc/code/ChannelRegs.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../clocked_tdc/code/FFregs.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../clocked_tdc/code/TDC_FF.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../clocked_tdc/code/FFregs2.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="untitled.lpf" type="Logic Preference" type_short="LPF" excluded="TRUE">
+ <Options/>
+ </Source>
+ <Source name="../workdir/mdctdc.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="auto_strat.sty"/>
+</BaliProject>
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-45F
+PartName=LFE5UM-45F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=PLL_TDC
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=07/04/2021
+Time=13:29:21
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=156.25
+CLKI_DIV=1
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=312.5
+CLKOP_TOL=0.0
+CLKOP_DIV=2
+CLKOP_ACTUAL_FREQ=312.500000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=312.5
+CLKOS_TOL=0.0
+CLKOS_DIV=2
+CLKOS_ACTUAL_FREQ=312.500000
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=ENABLED
+CLKOS2_FREQ=312.5
+CLKOS2_TOL=0.0
+CLKOS2_DIV=2
+CLKOS2_ACTUAL_FREQ=312.500000
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=ENABLED
+CLKOS3_FREQ=312.5
+CLKOS3_TOL=0.0
+CLKOS3_DIV=2
+CLKOS3_ACTUAL_FREQ=312.500000
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=2
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=625.000
+PLL_BW=10.504
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=45
+CLKOS_APHASE=45.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=90
+CLKOS2_APHASE=90.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=135
+CLKOS3_APHASE=135.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n PLL_TDC -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 156.25 -fclkop 312.5 -fclkop_tol 0.0 -fclkos 312.5 -fclkos_tol 0.0 -phases 45 -fclkos2 312.5 -fclkos2_tol 0.0 -phases2 90 -fclkos3 312.5 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1
--- /dev/null
+<!DOCTYPE PLL_TDC>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>PLL</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./PLL_TDC.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./PLL_TDC.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-45F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2021-07-04.13:29:29</lattice:date>
+ <lattice:modified>2021-07-04.13:29:29</lattice:modified>
+ <lattice:diamond>3.11.2.446</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-45F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">07/04/2021</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">PLL_TDC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:29:21</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">156.25</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.500000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.5</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.500000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">90.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">90</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.5</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.500000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">135.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">135</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.5</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.500000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">45.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">45</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">312.5</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_BW</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10.504</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>REFERENCE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VCO_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">625.000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n PLL_TDC -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 156.25 -fclkop 312.5 -fclkop_tol 0.0 -fclkos 312.5 -fclkos_tol 0.0 -phases 45 -fclkos2 312.5 -fclkos2_tol 0.0 -phases2 90 -fclkos3 312.5 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>PLL_TDC</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n PLL_TDC -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 156.25 -fclkop 312.5 -fclkop_tol 0.0 -fclkos 312.5 -fclkos_tol 0.0 -phases 45 -fclkos2 312.5 -fclkos2_tol 0.0 -phases2 90 -fclkos3 312.5 -fclkos3_tol 0.0 -phases3 135 -phase_cntl STATIC -fb_mode 1 -fdc /local/trb/git/mdcupgrade/cores/PLL_TDC/PLL_TDC.fdc
+
+-- Sun Jul 4 13:29:29 2021
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity PLL_TDC is
+ port (
+ CLKI: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ CLKOS2: out std_logic;
+ CLKOS3: out std_logic);
+end PLL_TDC;
+
+architecture Structure of PLL_TDC is
+
+ -- internal signal declarations
+ signal REFCLK: std_logic;
+ signal LOCK: std_logic;
+ signal CLKOS3_t: std_logic;
+ signal CLKOS2_t: std_logic;
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ attribute FREQUENCY_PIN_CLKOS3 : string;
+ attribute FREQUENCY_PIN_CLKOS2 : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute ICP_CURRENT : string;
+ attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "312.500000";
+ attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "312.500000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "312.500000";
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "312.500000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "156.250000";
+ attribute ICP_CURRENT of PLLInst_0 : label is "10";
+ attribute LPF_RESISTOR of PLLInst_0 : label is "24";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLL
+ generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
+ STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
+ CLKOS3_FPHASE=> 6, CLKOS3_CPHASE=> 1, CLKOS2_FPHASE=> 4,
+ CLKOS2_CPHASE=> 1, CLKOS_FPHASE=> 2, CLKOS_CPHASE=> 1,
+ CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 1, PLL_LOCK_MODE=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
+ OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 2,
+ CLKOS2_DIV=> 2, CLKOS_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2,
+ CLKI_DIV=> 1, FEEDBK_PATH=> "CLKOP")
+ port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
+ PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
+ PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
+ STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
+ ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
+ ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
+ CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK,
+ INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
+
+ CLKOS3 <= CLKOS3_t;
+ CLKOS2 <= CLKOS2_t;
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
LOCATE COMP "TEST_1" SITE "B19";\r
LOCATE COMP "TEST_2" SITE "D9";\r
LOCATE COMP "TEST_3" SITE "C8";\r
-DEFINE PORT GROUP "Test_group" "TEST*";\r
+DEFINE PORT GROUP "TEST_group" "TEST*";\r
IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 ;\r
\r
LOCATE COMP "INJ_0" SITE "J17";\r
jspc29 / mdcupgrade.git / commitdiff