--- an active api together with an iobuf
+-- the full endpoint for HADES: trg, data, data, regio
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use work.trb_net_std.all;
---Entity decalaration for clock generator
+
entity trb_net16_endpoint_1_trg_2_api_1_regio is
generic (
USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE);
- IBUF_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6);
+ IBUF_DEPTH : channel_config_t := (0,6,6,6);
+ FIFO_TO_INT_DEPTH : channel_config_t := (0,6,6,6);
+ FIFO_TO_APL_DEPTH : channel_config_t := (0,6,6,6);
IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
LVL2_APL_DATAREADY_IN: in std_logic;
LVL2_APL_READ_OUT: out std_logic;
LVL2_APL_SHORT_TRANSFER_IN: in std_logic;
- LVL2_APL_DTYPE_IN: in std_logic_vector (3 downto 0);
+ LVL2_APL_DTYPE_IN: in std_logic_vector (3 downto 0);
LVL2_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0);
LVL2_APL_SEND_IN: in std_logic;
LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0);
LVL2_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
LVL2_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_TYP_OUT: out std_logic_vector (2 downto 0);
+ LVL2_APL_TYP_OUT: out std_logic_vector (2 downto 0);
LVL2_APL_DATAREADY_OUT: out std_logic;
LVL2_APL_READ_IN: in std_logic;
LVL2_APL_RUN_OUT: out std_logic;
CLK_EN : in std_logic;
-- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
+ MED_DATAREADY_IN: in STD_LOGIC;
MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
MED_READ_OUT: out STD_LOGIC;
- MED_DATAREADY_OUT: out STD_LOGIC;
+ MED_DATAREADY_OUT: out STD_LOGIC;
MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
MED_READ_IN: in STD_LOGIC;
);
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
INT_DATAREADY_OUT: out std_logic;
INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_OUT: out std_logic;
-
+
-- "mini" APL, just to see the triggers coming in
APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
);
end generate;
gentrgapi : if i = 0 generate
- trglvl1 : trb_net16_term
+ trglvl1 : trb_net16_term
generic map(
USE_APL_PORT => c_YES,
SECURE_MODE => std_TERM_SECURE_MODE
onewire_interface : trb_net_onewire
generic map(
- USE_TEMPERATURE_READOUT => 1,
+ USE_TEMPERATURE_READOUT => c_YES,
CLK_PERIOD => 10
)
port map(
INT_READ_OUT => MED_IO_READ_IN,
CTRL => MPLEX_CTRL
);
-
+
end architecture;
-
+
entity trb_net16_hub_base is
generic (
- --general settings
- MUX_SECURE_MODE : integer range 0 to 1 := c_NO;
--hub control
HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 3;--c_SLOW_CTRL_CHANNEL;
HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
-
+
--Media interfacces
MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); -- buffer reads a word from media
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0);
MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
TRG_ERROR_PATTERN_IN : in std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
TRG_RELEASE_IN : in std_logic_vector (VAL(TRG_NUMBER) downto 0);
ONEWIRE : inout std_logic;
- --Status ports (for debugging)
+ --Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0)
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+
+ --Debugging registers
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
);
end entity;
signal hub_to_buf_REPLY_PACKET_NUM :std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
signal hub_to_buf_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0);
-
+
signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
signal buf_to_hub_REPLY_PACKET_NUM :std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
signal buf_STAT_POINTS_locked : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0);
+ signal buf_STAT_DEBUG : std_logic_vector (31 downto 0);
+ signal buf_CTRL_DEBUG : std_logic_vector (31 downto 0);
+
signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
signal HC_READ_IN : std_logic;
signal HC_RUN_OUT : std_logic;
signal HC_SEQNR_OUT : std_logic_vector (7 downto 0);
- signal HC_STAT_REGS : std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
- signal HC_CTRL_REGS : std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
+ signal HC_STAT_REGS : std_logic_vector (2**3*32-1 downto 0);
+ signal HC_CTRL_REGS : std_logic_vector (2**3*32-1 downto 0);
+ signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0);
signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal IDRAM_WR_IN : std_logic;
signal IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
signal TEMP_OUT : std_logic_vector(11 downto 0);
-
+
component trb_net16_hub_logic is
generic (
--media interfaces
CLK_EN : in std_logic;
-- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
+ MED_DATAREADY_IN: in STD_LOGIC;
MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
MED_READ_OUT: out STD_LOGIC;
- MED_DATAREADY_OUT: out STD_LOGIC;
+ MED_DATAREADY_OUT: out STD_LOGIC;
MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
MED_READ_IN: in STD_LOGIC;
);
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- Media direction port
MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
);
end component;
-
-
+
+
component trb_net16_api_base is
generic (
API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_OUT: out std_logic;
-
+
-- "mini" APL, just to see the triggers coming in
APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
STAT : out std_logic_vector(31 downto 0)
);
end component;
-
+
component trb_net16_term_buf is
port(
-- Misc
end generate;
end generate;
end generate;
-
-
-
+
+
+
gen_ctrl_api : if 1 = 1 generate --just a dummy now
constant i : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER;
begin
begin
gen_pas_api : if API_TYPE(aploffset) = 0 generate
constant t : integer := 0;
- begin
+ begin
PAS_API : trb_net16_api_base
generic map(
API_TYPE => API_TYPE(aploffset),
end generate;
gen_act_api : if API_TYPE(aploffset) = 1 generate
constant t : integer := 0;
- begin
+ begin
ACT_API : trb_net16_api_base
generic map(
API_TYPE => API_TYPE(aploffset),
<= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
buf_to_hub_INIT_READ(buf_to_hub_num)
<= HUB_INIT_READ_OUT(hublogic_num);
-
+
hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
<= HUB_INIT_DATAREADY_OUT(hublogic_num);
hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
<= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
HUB_INIT_READ_IN (hublogic_num)
<= hub_to_buf_INIT_READ(buf_to_hub_num);
-
+
HUB_REPLY_DATAREADY_IN (hublogic_num)
<= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
<= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
buf_to_hub_REPLY_READ(buf_to_hub_num)
<= HUB_REPLY_READ_OUT(hublogic_num);
-
+
hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
<= HUB_REPLY_DATAREADY_OUT(hublogic_num);
hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
<= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
buf_to_hub_INIT_READ(buf_to_hub_num)
<= HUB_INIT_READ_OUT(hublogic_num);
-
+
hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
<= HUB_INIT_DATAREADY_OUT(hublogic_num);
hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
<= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
HUB_INIT_READ_IN (hublogic_num)
<= hub_to_buf_INIT_READ(buf_to_hub_num);
-
+
HUB_REPLY_DATAREADY_IN (hublogic_num)
<= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
<= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
buf_to_hub_REPLY_READ(buf_to_hub_num)
<= HUB_REPLY_READ_OUT(hublogic_num);
-
+
hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
<= HUB_REPLY_DATAREADY_OUT(hublogic_num);
hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
HUB_MED_CONNECTED(i) <= '1';
end if;
end process;
-
+
end generate;
ADDRESS_WIDTH => 16,
NUM_STAT_REGS => 3,
NUM_CTRL_REGS => 3,
- INIT_CTRL_REGS => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
- x"00000000_00000000_00000000_00000000",
- USED_CTRL_REGS => "11111111",
+ INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
+ USED_CTRL_REGS => "01111111",
USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
NO_DAT_PORT => '1',
MY_ADDRESS_OUT => HUB_ADDRESS,
REGISTERS_IN => HC_STAT_REGS,
REGISTERS_OUT => HC_CTRL_REGS,
- COMMON_STAT_REG_IN => HC_STAT_REGS(63 downto 0),
- COMMON_CTRL_REG_OUT => open,
+ COMMON_STAT_REG_IN => HC_COMMON_STAT_REGS,
+ COMMON_CTRL_REG_OUT => HC_COMMON_CTRL_REGS,
--Port to write Unique ID
IDRAM_DATA_IN => IDRAM_DATA_IN,
IDRAM_DATA_OUT => open,
);
---8x CTRL, 8x STAT
-
- buf_HUB_STAT_GEN(3 downto 0) <= MED_PACKET_NUM_IN(3 downto 0);
- buf_HUB_STAT_GEN(5 downto 4) <= MED_DATAREADY_IN(1 downto 0);
- buf_HUB_STAT_GEN(7 downto 6) <= HUB_MED_CONNECTED(1 downto 0);
- buf_HUB_STAT_GEN(15 downto 8) <= buf_STAT_POINTS_locked(7 downto 0);
- buf_HUB_STAT_GEN(19 downto 16) <= (others => '0');
- buf_HUB_STAT_GEN(31 downto 20) <= TEMP_OUT;
-
- HUB_STAT_GEN <= buf_HUB_STAT_GEN;
- HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
+ --debug Status and Control ports
+ buf_STAT_DEBUG(3 downto 0) <= MED_PACKET_NUM_IN(3 downto 0);
+ buf_STAT_DEBUG(5 downto 4) <= MED_DATAREADY_IN(1 downto 0);
+ buf_STAT_DEBUG(7 downto 6) <= HUB_MED_CONNECTED(1 downto 0);
+ buf_STAT_DEBUG(15 downto 8) <= buf_STAT_POINTS_locked(7 downto 0);
+ buf_STAT_DEBUG(19 downto 16) <= (others => '0');
+ buf_STAT_DEBUG(31 downto 20) <= TEMP_OUT;
- HC_STAT_REGS(31 downto 0) <= buf_HUB_STAT_GEN;
- HC_STAT_REGS(32+2**(c_MUX_WIDTH-1)*16-1 downto 32) <= buf_HUB_STAT_CHANNEL;
- HUB_CTRL_GEN <= HC_CTRL_REGS(31 downto 0);
- HUB_CTRL_CHANNEL <= HC_CTRL_REGS(32+2**(c_MUX_WIDTH-1)*16-1 downto 32);
- HUB_CTRL_activepoints <= HC_CTRL_REGS(128+2**(c_MUX_WIDTH-1)*32-1 downto 128);
+ buf_HUB_STAT_GEN <= (others => '0');
- HC_STAT_REGS(8*32-1 downto 96) <= (others => '0');
+ --Registers for RegIO
+ HC_COMMON_STAT_REGS(19 downto 0) <= (others => '0');
+ HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT;
+ HC_COMMON_STAT_REGS(63 downto 32) <= (others => '0');
+ HC_STAT_REGS(2**(c_MUX_WIDTH-1)*32-1 downto 0) <= buf_STAT_POINTS_locked;
+ HC_STAT_REGS(5*32-1 downto 4*32) <= buf_HUB_STAT_GEN;
+ HC_STAT_REGS(8*32-1 downto 5*32) <= (others => '0'); --unused regs
+ HUB_CTRL_activepoints <= HC_CTRL_REGS(2**(c_MUX_WIDTH-1)*32-1 downto 0);
+ HUB_CTRL_GEN <= HC_CTRL_REGS(159 downto 128);
+ HUB_CTRL_CHANNEL <= HC_CTRL_REGS(160+2**(c_MUX_WIDTH-1)*16-1 downto 160);
+ --map regio registers to stat & ctrl outputs
+ STAT_COMMON_STAT_REGS <= HC_COMMON_STAT_REGS;
+ STAT_COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS;
+ STAT_REGS <= HC_STAT_REGS;
+ STAT_CTRL_REGS <= HC_CTRL_REGS;
+ HUB_STAT_GEN <= buf_HUB_STAT_GEN;
+ HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
+ STAT_DEBUG <= buf_STAT_DEBUG;
end architecture;
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