--- /dev/null
+# Module: Channel Masking (Type 0x00)
+# This block contains only one control register that holds
+# the bitmask (bits 15:0) for the internal channel selection.
+# A trigger event is detected, if any of the masked channels is asserted.
+
+package CtsMod00;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+
+sub moduleName {"Channel Masking"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+# registers
+ $regs->{"trg_channel_mask"} = TrbRegister->new($address + 1, $trb, {
+ 'mask' => {'lower' => 0, 'len' => 16, 'type' => 'mask'}
+ }, {
+ 'accessmode' =>"rw",
+ 'monitor' => '1',
+ 'export' => '1',
+ 'label' => "Trigger Channel Mask"
+ });
+
+# properties
+ $prop->{"trg_channel_count"} = 16;
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Internal Channel Event Counter (Type: 0x01)
+# This block contains 32 status registers, that allow read access to
+# the level and edge counters of each internal trigger channel. Each channel has
+# its two 32 bit counters, that count the number of clock cycles the channel
+# is asserted / the number of rising edges. All counters work independently and
+# an overflow of one register does not affect the other registers.
+
+package CtsMod01;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+
+sub moduleName {"Channel Event Counter"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+ my $header = $self->getCTS->getTriggerEnum->{0x01}->read();
+
+
+# registers
+ for(my $i=0; $i < $header->{'len'} / 2; $i++) {
+ $regs->{"trg_channel_asserted_cnt$i"} = TrbRegister->new($address + 1 + 2*$i, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Trigger Channel Asserted Counter $i",
+ 'monitorrate' => 1
+ });
+
+ $regs->{"trg_channel_edge_cnt$i"} = TrbRegister->new($address + 1 + 2*$i + 1, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Trigger Channel Edge Counter $i",
+ 'monitorrate' => 1
+ });
+ }
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Input Module Configuration (Type 0x10)
+package CtsMod10;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+
+sub moduleName {"Input Module Configuration"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+ my $header = $self->{'_cts'}{'_enum'}{0x10}->read();
+
+# registers
+ for(my $i = 0; $i < $header->{'len'}; $i++) {
+ my $key = "trg_input_config$i";
+
+ $regs->{$key} = new TrbRegister($address + 1 + $i, $trb, {
+ 'delay' => {'lower' => 0, 'len' => 4},
+ 'spike_rej' => {'lower' => 4, 'len' => 4},
+ 'invert' => {'lower' => 8, 'len' => 1, 'type' => 'bool'},
+ 'override' => {'lower' => 9, 'len' => 2, 'type' => 'enum', 'enum' =>
+ {0 => 'off', 1 => 'to_low', 3 => 'to_high'}
+ }
+ }, {
+ 'accessmode' => "rw",
+ 'export' => 1,
+ 'monitor' => '1',
+ 'label' => "Trigger Input Module Configuration $i"
+ });
+ }
+
+ for(my $i = 0; $i < $header->{'itc_len'}; $i++) {
+ $self->{'_cts'}->getProperties->{'itc_assignments'}[$i + $header->{'itc_base'}] = "Trigger Input $i";
+ }
+
+# properties
+ $prop->{"trg_input_count"} = $header->{'len'};
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Input Event Counter (Type 0x11).
+# Similiarly to the Internal Channel Event Counters (Type 0x01)
+# this block contains one status register for each input channel. The here-mentioned
+# counters, however, use the unprocessed trigger inputs instead of the internal trigger
+# channels. Hence by comparing both counter types, one can infere the number of
+# events filtered by the spike rejection.
+
+
+package CtsMod11;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+
+sub moduleName {"Channel Event Counter"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $expo = $self->{'_exportRegs'};
+ my $prop = $self->{'_properties'};
+
+ my $header = $self->getCTS->getTriggerEnum->{0x11}->read();
+
+
+# registers
+ for(my $i=0; $i < $header->{'len'} / 2; $i++) {
+ $regs->{"trg_input_asserted_cnt$i"} = TrbRegister->new($address + 1 + 2*$i, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Trigger Input Asserted Counter $i",
+ 'monitorrate' => 1
+ });
+
+ $regs->{"trg_input_edge_cnt$i"} = TrbRegister->new($address + 1 + 2*$i + 1, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Trigger Input Edge Counter $i",
+ 'monitorrate' => 1
+ });
+ }
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Coincidence Configuration (Type 0x20)
+package CtsMod20;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+
+sub moduleName {"Coincidence Configuration"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+ my $header = $self->{'_cts'}{'_enum'}{0x20}->read();
+
+# registers
+ for(my $i = 0; $i < $header->{'len'}; $i++) {
+ my $key = "trg_coin_config$i";
+
+ $regs->{$key} = new TrbRegister($address + 1 + $i, $trb, {
+ 'coin_mask' => {'lower' => 0, 'len' => 8, 'type' => 'mask'},
+ 'inhibit_mask' => {'lower' => 8, 'len' => 8, 'type' => 'mask'},
+ 'window' => {'lower' => 16, 'len' => 4}
+ }, {
+ 'accessmode' => "rw",
+ 'label' => "Coincidence Configuration $i",
+ 'monitor' => '1',
+ 'export' => 1
+ });
+ }
+
+ for(my $i = 0; $i < $header->{'itc_len'}; $i++) {
+ $self->{'_cts'}->getProperties->{'itc_assignments'}[$i + $header->{'itc_base'}] = "Coincidence Module $i";
+ }
+
+# properties
+ $prop->{"trg_coin_count"} = $header->{'len'};
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Pulser (Type 0x30)
+# Each pulser has one register that stores its interval length. The
+# number represents the duration of the low-level in microseconds, which is followed
+# by an one clock high-pulse. Hence 0 results in a constant high channel.
+
+package CtsMod30;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+
+sub moduleName {"Periodical Counter"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+ my $header = $self->{'_cts'}{'_enum'}{0x30}->read();
+
+# registers
+ for(my $i = 0; $i < $header->{'len'}; $i++) {
+ my $key = "trg_pulser_config$i";
+
+ $regs->{$key} = new TrbRegister($address + 1 + $i, $trb, {
+ 'low_duration' => {'lower' => 0, 'len' => 32},
+ }, {
+ 'accessmode' => "rw",
+ 'label' => "Periodical Counter Configuration $i",
+ 'monitor' => '1',
+ 'export' => 1
+ });
+ }
+
+ for(my $i = 0; $i < $header->{'itc_len'}; $i++) {
+ $self->{'_cts'}->getProperties->{'itc_assignments'}[$i + $header->{'itc_base'}] = "Periodical Pulser $i";
+ }
+
+# properties
+ $prop->{"trg_pulser_count"} = $header->{'len'};
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Event types (Type 0x40)
+# This block contains exactly two registers, that assign a trigger
+# type id (4bit) to each internal trigger channel. Starting with the type of the first
+# channel at the lowest four bits of the first register, each word stores 8 types.
+
+package CtsMod40;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+use TrbSlicedRegister;
+
+sub moduleName {"Event Types"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+# registers
+ for(my $i = 0; $i < 2; $i++) {
+ my $key = "_trg_trigger_types$i";
+
+ my $enumDef = {
+ 0x0 => '0x0',
+ 0x1 => '0x1_pysics_trigger',
+ 0x2 => '0x2',
+ 0x3 => '0x3',
+ 0x4 => '0x4',
+ 0x5 => '0x5',
+ 0x6 => '0x6',
+ 0x7 => '0x7',
+
+ 0x8 => '0x8',
+ 0x9 => '0x9_mdc_calibration_trigger',
+ 0xa => '0xa_shower_calibration_trigger',
+ 0xb => '0xb_shower_pedestal_trigger',
+ 0xc => '0xc',
+ 0xd => '0xd',
+ 0xe => '0xe_status_information_trigger',
+ 0xf => '0xf'
+ };
+
+ $regs->{$key} = new TrbRegister($address + 1 + $i, $trb, {
+ 'type' . (8*$i + 0) => {'lower' => 0, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+ 'type' . (8*$i + 1) => {'lower' => 4, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+ 'type' . (8*$i + 2) => {'lower' => 8, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+ 'type' . (8*$i + 3) => {'lower' => 12, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+
+ 'type' . (8*$i + 4) => {'lower' => 16, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+ 'type' . (8*$i + 5) => {'lower' => 20, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+ 'type' . (8*$i + 6) => {'lower' => 24, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef},
+ 'type' . (8*$i + 7) => {'lower' => 28, 'len' => 4, 'type' => 'enum', 'enum' => $enumDef}
+ }, {
+ 'accessmode' => "rw",
+ 'label' => "Trigger Event Tpye $i",
+ 'monitor' => '1',
+ 'export' => 1
+ });
+ }
+
+ for(my $i=0; $i<16; $i++) {
+ $regs->{'trg_trigger_type' . $i} = new TrbSlicedRegister({
+ 'type' => $regs->{'_trg_trigger_types' . ($i < 8 ? '0' : '1')},
+ });
+ }
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# Module: Random Pulser (Type 0x50)
+# The random pulser generates irregular event patterns. As
+# the pulser is not configurable, the sole purpose of this block is to inform about the
+# presens of the unit and its mapping to the internal channel. The has no payload,
+# i.e. a fixed size of 0 words.
+
+package CtsMod50;
+
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+
+sub moduleName {"Random Pulser"}
+
+sub init {
+ my $self = $_[0];
+ my $address = $_[1];
+
+ my $trb = $self->{'_cts'}{'_trb'};
+
+ my $regs = $self->{'_registers'};
+ my $expo = $self->{'_exportRegs'};
+ my $prop = $self->{'_properties'};
+
+ my $header = $self->{'_cts'}{'_enum'}{0x50}->read();
+
+ for(my $i = 0; $i < $header->{'itc_len'}; $i++) {
+ $self->{'_cts'}->getProperties->{'itc_assignments'}[$i + $header->{'itc_base'}] = "Random Pulser";
+ }
+
+# registers
+ $prop->{"trg_random_pulser_count"} = 1;
+}
+
+1;
\ No newline at end of file
--- /dev/null
+# This module defines all registers, that are statically mapped,
+# i.e. have a fixed address, that does not have to be calculated
+# during evaluation.
+# By definition, these registers belong to the first address-block
+# (stating at 0xa000).
+
+package CtsModStatic;
+@ISA = (CtsBaseModule);
+
+use warnings;
+use strict;
+use TrbRegister;
+use CtsBaseModule;
+
+sub moduleName {"Base Registers"}
+
+sub init {
+ my $self = $_[0];
+
+ my $regs = $self->{'_registers'};
+ my $prop = $self->{'_properties'};
+
+ my $trb = $self->{'_cts'}->{'_trb'};
+
+ my $debug_block = 0xa000;
+
+ $regs->{'cts_cnt_trg_asserted'} = TrbRegister->new(0x00 + $debug_block, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Cycles with trigger asserted",
+ 'monitorrate' => 1
+ });
+
+ $regs->{'cts_cnt_trg_edges'} = TrbRegister->new(0x01 + $debug_block, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Trigger rising edges",
+ 'monitorrate' => 1
+ });
+
+ $regs->{'cts_cnt_trg_accepted'} = TrbRegister->new(0x02 + $debug_block, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Triggers accepted",
+ 'monitorrate' => 1
+ });
+
+ $regs->{'cts_cur_trg_state'} = TrbRegister->new(0x03 + $debug_block, $trb, {
+ 'mask' => {'lower' => 0, 'len' => 16, 'type' => 'mask'},
+ 'type' => {'lower' => 16, 'len' => 4, 'type' => 'hex'},
+ 'asserted' => {'lower' => 20, 'len' => 1, 'type' => 'bool'}
+ }, {
+ 'accessmode' => "ro",
+ 'monitor' => '1',
+ 'label' => "Current Trigger State"
+ });
+
+ $regs->{'cts_buf_trg_state'} = TrbRegister->new(0x04 + $debug_block, $trb, {
+ 'mask' => {'lower' => 0, 'len' => 16, 'type' => 'mask'},
+ 'type' => {'lower' => 16, 'len' => 4, 'type' => 'hex'}
+ }, {
+ 'accessmode' => "ro",
+ 'monitor' => '1',
+ 'label' => "Buffered Trigger State"
+ });
+
+ $regs->{'cts_td_fsm_state'} = TrbRegister->new(0x05 + $debug_block, $trb, {
+ 'state' => {'lower' => 0, 'len' => 32, 'type' => 'enum', 'enum' => {
+ 0x001 => 'TD_FSM_IDLE',
+ 0x002 => 'TD_FSM_SEND_TRIGGER',
+ 0x004 => 'TD_FSM_WAIT_FEE_RECV_TRIGGER',
+ 0x008 => 'TD_FSM_FEE_COMPLETE',
+ 0x010 => 'TD_FSM_WAIT_TRIGGER_BECOME_IDLE',
+ 0x020 => 'TD_FSM_DEBUG_LIMIT_REACHED',
+ 0x040 => 'TD_FSM_FEE_ENQUEUE_IDLE_COUNTER',
+ 0x080 => 'TD_FSM_FEE_ENQUEUE_DEAD_COUNTER',
+ 0x100 => 'TD_FSM_FEE_ENQUEUE_TRIGGER_ASSERTED_COUNTER',
+ 0x200 => 'TD_FSM_FEE_ENQUEUE_TRIGGER_EDGES_COUNTER',
+ 0x400 => 'TD_FSM_FEE_ENQUEUE_TRIGGER_ACCEPTED_COUNTER'
+ }}
+ }, {
+ 'accessmode' => "ro",
+ 'monitor' => '1',
+ 'label' => "TD FSM State"
+ });
+
+ $regs->{'cts_ro_fsm_state'} = TrbRegister->new(0x06 + $debug_block, $trb, {
+ 'state' => {'lower' => 0, 'len' => 32, 'type' => 'enum', 'enum' => {
+ 0x01 => 'RO_FSM_IDLE',
+ 0x02 => 'RO_FSM_SEND_REQUEST',
+ 0x04 => 'RO_FSM_WAIT_BECOME_BUSY',
+ 0x08 => 'RO_FSM_WAIT_BECOME_IDLE',
+ 0x10 => 'RO_FSM_DEBUG_LIMIT_REACHED'
+ }}
+ }, {
+ 'accessmode' => "ro",
+ 'monitor' => '1',
+ 'label' => "RO FSM State"
+ });
+
+ $regs->{'cts_ro_queue'} = TrbRegister->new(0x07 + $debug_block, $trb, {
+ 'count' => {'lower' => 0, 'len' => 16},
+ 'state' => {'lower' => 30, 'len' => 2, 'type' => 'enum', 'enum' => {
+ 0x0 => 'Active',
+ 0x1 => 'Empty',
+ 0x2 => 'Full'
+ }}
+ }, {
+ 'accessmode' => "ro",
+ 'monitor' => '1',
+ 'label' => "RO Queue State"
+ });
+
+ $regs->{'cts_fsm_limits'} = TrbRegister->new(0x08 + $debug_block, $trb, {
+ 'td' => {'lower' => 0, 'len' => 16},
+ 'ro' => {'lower' => 16, 'len' => 16}
+ }, {
+ 'accessmode' => "rw",
+ 'label' => "FSM Blocking (debug)",
+ 'monitor' => 1,
+ 'export' => 1
+ });
+
+ $regs->{'cts_readout_config'} = TrbRegister->new(0x09 + $debug_block, $trb, {
+ 'input_cnt' => {'lower' => 0, 'len' => 1, 'type' => 'bool'},
+ 'channel_cnt' => {'lower' => 1, 'len' => 1, 'type' => 'bool'},
+ 'idle_dead_cnt' => {'lower' => 2, 'len' => 1, 'type' => 'bool'},
+ 'trg_cnt' => {'lower' => 3, 'len' => 1, 'type' => 'bool'},
+ 'wasa' => {'lower' => 4, 'len' => 1, 'type' => 'bool'},
+ }, {
+ 'accessmode' => "rw",
+ 'label' => "Readout configuration",
+ 'monitor' => '1',
+ 'export' => 1
+ });
+
+ $regs->{'cts_cnt_dead_time'} = TrbRegister->new(0x0a + $debug_block, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Dead time counter",
+ 'monitor' => 1
+ });
+
+ $regs->{'cts_cnt_idle_time'} = TrbRegister->new(0x0b + $debug_block, $trb, {}, {
+ 'accessmode' => "ro",
+ 'label' => "Idle time counter",
+ 'monitor' => 1
+ });
+
+ $prop->{'cts_clock_frq'} = 1e8;
+ $prop->{'trb_endpoint'} = $trb->getEndpoint;
+ $prop->{'trb_compiletime'} = $trb->read(0x40);
+}
+
+1;
\ No newline at end of file
jspc29 / daqtools.git / commitdiff