added dirich5d_piggy1_trigger, mt

diff --git a/dirich5d_piggy1_trigger/.gitignore b/dirich5d_piggy1_trigger/.gitignore
new file mode 100644 (file)
index 0000000..7c6b138
--- /dev/null
+++ b/dirich5d_piggy1_trigger/.gitignore
@@ -0,0 +1,36 @@
+*~
+*.tcl
+*.log
+*.rpt
+netlists
+version.vhd
+*.jhd
+*.naf
+*.sort
+*.srp
+*.sym
+*tmpl.vhd
+*.log
+workdir
+workdir_*
+*.bit
+*.kate-swp*
+*.kate-swap*
+.run_manager.ini
+reportview.xml
+.kateproject.d
+*/project/
+*/project2/
+modelsim.ini
+*.mti
+*.bak
+work
+*.wlf
+*stacktrace.txt
+*edn
+licbug.txt
+old
+config_compile.pl
+._Real_._Math_.vhd
+diamond
+diamondwin

diff --git a/dirich5d_piggy1_trigger/README__________README b/dirich5d_piggy1_trigger/README__________README
new file mode 100644 (file)
index 0000000..c9905e3
--- /dev/null
+++ b/dirich5d_piggy1_trigger/README__________README
@@ -0,0 +1,3 @@
+To compile run:
+
+./compile.sh

diff --git a/dirich5d_piggy1_trigger/compile.sh b/dirich5d_piggy1_trigger/compile.sh
new file mode 100755 (executable)
index 0000000..33c8386
--- /dev/null
+++ b/dirich5d_piggy1_trigger/compile.sh
@@ -0,0 +1,26 @@
+#!/usr/bin/zsh
+
+###########################
+# generic
+LC_ALL=C
+LC_NUMERIC=C
+LANG=C
+LATTICE_LICENSE_FILE=1702@hadeb05.gsi.de
+MGLS_LICENSE_FILE=1702@hadeb05.gsi.de
+################################
+
+
+###########################################
+# special for each computer, please change
+DIAMOND_VERSION=3.13
+INSTALLATION_PATH="/opt/lattice/diamond"
+########################
+
+
+
+#########################################
+### standard
+bindir="$INSTALLATION_PATH/$DIAMOND_VERSION/bin/lin64"
+source "$INSTALLATION_PATH/$DIAMOND_VERSION/bin/lin64/diamond_env"
+
+pnmainc compile.tcl

diff --git a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.ldf b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.ldf
new file mode 100644 (file)
index 0000000..1139d21
--- /dev/null
+++ b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.ldf
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="dirich5d_piggy1_trigger" device="LCMXO3LF-6900C-6BG256C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="top"/>
+        <Source name="dirich5d_piggy1_trigger1.vhd" type="VHDL" type_short="VHDL">
+            <Options top_module="top"/>
+        </Source>
+        <Source name="dirich5d_piggy1_trigger.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="dirich5d_piggy1_trigger1.sty"/>
+</BaliProject>

diff --git a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf
new file mode 100644 (file)
index 0000000..5d41325
--- /dev/null
+++ b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf
@@ -0,0 +1,54 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "IN_MISC1" SITE "G5" ;
+IOBUF PORT "IN_MISC1" IO_TYPE=LVDS25 ;
+LOCATE COMP "PIGGY_CS" SITE "T15" ;
+LOCATE COMP "TRIG_OUT[1]" SITE "F9" ;
+LOCATE COMP "TRIG_OUT[2]" SITE "C12" ;
+LOCATE COMP "TRIG_OUT[3]" SITE "B13" ;
+LOCATE COMP "TRIG_OUT[4]" SITE "B11" ;
+LOCATE COMP "TRIG_OUT[5]" SITE "A9" ;
+LOCATE COMP "TRIG_OUT[6]" SITE "B7" ;
+LOCATE COMP "TRIG_OUT[7]" SITE "A5" ;
+LOCATE COMP "TRIG_OUT[8]" SITE "C4" ;
+LOCATE COMP "TRIG_OUT[9]" SITE "F10" ;
+LOCATE COMP "TRIG_OUT[10]" SITE "B14" ;
+LOCATE COMP "TRIG_OUT[11]" SITE "B9" ;
+LOCATE COMP "TRIG_OUT[12]" SITE "A11" ;
+LOCATE COMP "TRIG_OUT[13]" SITE "C8" ;
+LOCATE COMP "TRIG_OUT[14]" SITE "D6" ;
+LOCATE COMP "TRIG_OUT[15]" SITE "A4" ;
+LOCATE COMP "TRIG_OUT[16]" SITE "A3" ;
+IOBUF PORT "TRIG_OUT[1]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[2]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[3]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[4]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[5]" IO_TYPE=LVDS25E ;
+IOBUF PORT "TRIG_OUT[6]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[7]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[8]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[9]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[10]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[11]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[12]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[13]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[14]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[15]" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIG_OUT[16]" IO_TYPE=LVDS25 ;
+LOCATE COMP "TRIG_IN[1]" SITE "T13" ;
+LOCATE COMP "TRIG_IN[2]" SITE "T12" ;
+LOCATE COMP "TRIG_IN[3]" SITE "R12" ;
+LOCATE COMP "TRIG_IN[4]" SITE "R11" ;
+LOCATE COMP "TRIG_IN[5]" SITE "T10" ;
+LOCATE COMP "TRIG_IN[6]" SITE "R9" ;
+LOCATE COMP "TRIG_IN[7]" SITE "T8" ;
+LOCATE COMP "TRIG_IN[8]" SITE "P8" ;
+LOCATE COMP "TRIG_IN[9]" SITE "R7" ;
+LOCATE COMP "TRIG_IN[10]" SITE "R6" ;
+LOCATE COMP "TRIG_IN[11]" SITE "T5" ;
+LOCATE COMP "TRIG_IN[12]" SITE "T4" ;
+LOCATE COMP "TRIG_IN[13]" SITE "R4" ;
+LOCATE COMP "TRIG_IN[14]" SITE "T3" ;
+LOCATE COMP "TRIG_IN[15]" SITE "R3" ;
+LOCATE COMP "TRIG_IN[16]" SITE "T2" ;
+

diff --git a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.sty b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.sty
new file mode 100644 (file)
index 0000000..4404aba
--- /dev/null
+++ b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.sty
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ReportTrimmedUserNets" value="False" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>

diff --git a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd
new file mode 100644 (file)
index 0000000..0785e4c
--- /dev/null
+++ b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd
@@ -0,0 +1,64 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library machXO3lf;
+use machXO3lf.all;
+
+
+entity top is
+  PORT (
+    IN_MISC1    : in    std_logic;
+    TRIG_OUT    : out   std_logic_vector(16 downto 1);
+    TRIG_IN     : in    std_logic_vector(16 downto 1);
+    PIGGY_CS    : out   std_logic
+--    OUTPUT2     : out   std_logic
+  );
+  
+end top;
+
+architecture Behavioral of top is
+
+  component OSCH
+-- synthesis translate_off
+    GENERIC (NOM_FREQ: string := "7.00");
+-- synthesis translate_on
+    PORT (STDBY    :  IN  std_logic;
+          OSC      :  OUT std_logic;
+          SEDSTDBY :  OUT std_logic
+    );
+  END COMPONENT;
+
+
+-- attribute NOM_FREQ : string;
+-- attribute NOM_FREQ of internal_oscillator : label is "7.00";
+
+signal osc_int  : std_logic;
+signal i_in_misc1 : std_logic;
+
+
+begin
+
+internal_oscillator: OSCH
+  -- synthesis translate_off
+  GENERIC MAP( NOM_FREQ => "7.00" )
+  -- synthesis translate_on
+  PORT MAP (STDBY=> '1',
+            OSC      => osc_int,
+            SEDSTDBY => open
+  );    
+
+
+i_in_misc1 <= IN_MISC1;
+
+PIGGY_CS <= i_in_misc1;
+TRIG_OUT(16 downto 1) <= TRIG_IN(16 downto 1);
+
+--OUTPUT2 <= osc_int;
+--OUTPUT2 <= '0';
+
+end Behavioral;
+
+  
+ 

diff --git a/pinout/dirich5d1.lpf b/pinout/dirich5d1.lpf
new file mode 100644 (file)
index 0000000..209f89a
--- /dev/null
+++ b/pinout/dirich5d1.lpf
@@ -0,0 +1,198 @@
+SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
+# BANK 0 VCCIO 2.5 V;
+# BANK 1 VCCIO 2.5 V;
+BANK 2 VCCIO 2.5 V;
+BANK 3 VCCIO 2.5 V;
+BANK 6 VCCIO 2.5 V;
+BANK 7 VCCIO 2.5 V;
+BANK 8 VCCIO 3.3 V;
+
+
+LOCATE COMP "INPUT[1]"  SITE "E5";
+LOCATE COMP "INPUT[2]"  SITE "F4";
+LOCATE COMP "INPUT[3]"  SITE "E4";
+LOCATE COMP "INPUT[4]"  SITE "B5";
+LOCATE COMP "INPUT[5]"  SITE "A4";
+LOCATE COMP "INPUT[6]"  SITE "C4";
+LOCATE COMP "INPUT[7]"  SITE "A3";
+LOCATE COMP "INPUT[8]"  SITE "C3";
+LOCATE COMP "INPUT[9]"  SITE "A2";
+LOCATE COMP "INPUT[10]"  SITE "B2";
+LOCATE COMP "INPUT[11]" SITE "C1";
+LOCATE COMP "INPUT[12]" SITE "D2";
+LOCATE COMP "INPUT[13]" SITE "F2";
+LOCATE COMP "INPUT[14]" SITE "G3";
+LOCATE COMP "INPUT[15]" SITE "H4";
+LOCATE COMP "INPUT[16]" SITE "H5";
+LOCATE COMP "INPUT[17]" SITE "T19";
+LOCATE COMP "INPUT[18]" SITE "T20";
+LOCATE COMP "INPUT[19]" SITE "U19";
+LOCATE COMP "INPUT[20]" SITE "P20";
+LOCATE COMP "INPUT[21]" SITE "R16";
+LOCATE COMP "INPUT[22]" SITE "N19";
+LOCATE COMP "INPUT[23]" SITE "P19";
+LOCATE COMP "INPUT[24]" SITE "L18";
+LOCATE COMP "INPUT[25]" SITE "N18";
+LOCATE COMP "INPUT[26]" SITE "D18";
+LOCATE COMP "INPUT[27]" SITE "E16";
+LOCATE COMP "INPUT[28]" SITE "L16";
+LOCATE COMP "INPUT[29]" SITE "N16";
+LOCATE COMP "INPUT[30]" SITE "N17";
+LOCATE COMP "INPUT[31]" SITE "U16";
+LOCATE COMP "INPUT[32]" SITE "U18";
+DEFINE PORT GROUP "INP_group" "INP*" ;
+IOBUF GROUP  "INP_group" IO_TYPE=LVDS  DIFFRESISTOR=OFF BANK_VCCIO=2.5;
+
+LOCATE COMP "CLOCK_IN"       SITE "G2";  # This signal is called CLOCK_CORE in the schematics
+LOCATE COMP "CLOCK_CAL"      SITE "H2";
+
+LOCATE COMP "CLOCK_OUT"      SITE "C18";
+LOCATE COMP "CLOCK_CLEAN[0]" SITE "L20";
+LOCATE COMP "CLOCK_CLEAN[1]" SITE "B12";
+
+DEFINE PORT GROUP "CLK_group" "CL*" ;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+# not needed for dirich5d with Piggy. Done there.
+##LOCATE COMP "ASYNC_OR"       SITE "H18"; # 
+##IOBUF PORT  "ASYNC_OR" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+
+# Trigger_IN not existing directly for DiRICH5d1, has to be sent through
+#  Piggy-AddOn. Using PIGGY_CS1 => F18 for trigger. no TLVDS...
+#               or SIG_OUT[13]  => H1
+LOCATE COMP "TRIG_IN" SITE "F18"; 
+DEFINE PORT GROUP "TRIG_group" "TRIG*" ;
+IOBUF PORT  "TRIG_group" IO_TYPE=LVCMOS25  BANK_VCCIO=2.5;
+###IOBUF GROUP  "TRIG_group" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "LED_GREEN"                      SITE "G16";
+LOCATE COMP "LED_ORANGE"                     SITE "H16";
+LOCATE COMP "LED_RED"                        SITE "H18";
+LOCATE COMP "LED_YELLOW"                     SITE "H17";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP  "LED_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+LOCATE COMP "ADC_CS"                         SITE "J16";
+LOCATE COMP "ADC_DIN"                        SITE "K17";
+LOCATE COMP "ADC_DOUT"                       SITE "K16";
+LOCATE COMP "ADC_SCLK"                       SITE "J17";
+IOBUF PORT  "ADC_CS" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_DIN" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_DOUT" IO_TYPE=LVCMOS25  BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_SCLK" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "PROGRAMN"                       SITE "T1";
+IOBUF PORT  "PROGRAMN" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+
+LOCATE COMP "SFP1_TX_DIS"                           SITE "D9";
+
+#LOCATE COMP "SIG[1]"                           SITE "N4";
+#LOCATE COMP "SIG[2]"                           SITE "N5";
+#LOCATE COMP "SIG[3]"                           SITE "M5";
+#LOCATE COMP "SIG[4]"                           SITE "M4";
+#LOCATE COMP "SIG[5]"                           SITE "L5";
+#IOBUF PORT    "SIG[1]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5 PULLMODE=UP;
+#IOBUF PORT    "SIG[2]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5 ;
+#IOBUF PORT    "SIG[3]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+#IOBUF PORT    "SIG[4]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+#IOBUF PORT    "SIG[5]" IO_TYPE=LVCMOS25  DRIVE=4 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "FLASH_CLK"                        SITE "U1";
+LOCATE COMP "FLASH_CS"                         SITE "R2";
+LOCATE COMP "FLASH_IN"                         SITE "W2";
+LOCATE COMP "FLASH_OUT"                        SITE "V2";
+LOCATE COMP "FLASH_HOLD"                       SITE "W1";
+LOCATE COMP "FLASH_WP"                         SITE "Y2";
+IOBUF PORT  "FLASH_CLK" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_IN"  IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_OUT" IO_TYPE=LVTTL33   BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_CS"  IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_HOLD" IO_TYPE=LVTTL33   BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_WP" IO_TYPE=LVTTL33   BANK_VCCIO=3.3;
+
+
+LOCATE COMP "TEMP_LINE"                      SITE "R1";
+IOBUF PORT  "TEMP_LINE" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+
+
+#LOCATE COMP "TEST_LINE[1]"                          SITE "N3";
+#LOCATE COMP "TEST_LINE[2]"                          SITE "M3";
+#LOCATE COMP "TEST_LINE[3]"                          SITE "L3";
+#LOCATE COMP "TEST_LINE[4]"                          SITE "K3";
+#LOCATE COMP "TEST_LINE[5]"                          SITE "N2";
+#LOCATE COMP "TEST_LINE[6]"                          SITE "J3";
+#LOCATE COMP "TEST_LINE[7]"                          SITE "P1";
+#LOCATE COMP "TEST_LINE[8]"                          SITE "L2";
+#LOCATE COMP "TEST_LINE[9]"                          SITE "P2";
+#LOCATE COMP "TEST_LINE[10]"                         SITE "L1";
+#LOCATE COMP "TEST_LINE[11]"                         SITE "P3";
+#LOCATE COMP "TEST_LINE[12]"                         SITE "M1";
+#LOCATE COMP "TEST_LINE[13]"                         SITE "P4";
+#LOCATE COMP "TEST_LINE[14]"                         SITE "N1";
+#DEFINE PORT GROUP "TEST_group" "TEST*" ;
+#IOBUF GROUP  "TEST_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "MISO_IN[0]"          SITE "C8";    #DAC1_CTRL0
+LOCATE COMP "MISO_IN[1]"          SITE "A17";   #DAC2_CTRL0
+LOCATE COMP "MOSI_OUT[0]"         SITE "B8";    #DAC1_CTRL1
+LOCATE COMP "MOSI_OUT[1]"         SITE "A18";   #DAC2_CTRL1
+LOCATE COMP "SCLK_OUT[0]"         SITE "D7";    #DAC1_CTRL2
+LOCATE COMP "SCLK_OUT[1]"         SITE "B19";   #DAC2_CTRL2
+LOCATE COMP "CS_OUT[0]"           SITE "A6";    #DAC1_CTRL3
+LOCATE COMP "CS_OUT[1]"           SITE "B18";   #DAC2_CTRL3
+
+LOCATE COMP "SFP_MOD1"           SITE "E6";     # SFP I2C SCL
+LOCATE COMP "SFP_MOD2"           SITE "C9";     # SFP I2C SDA
+
+IOBUF PORT "MISO_IN[0]"   IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "MOSI_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "SCLK_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "CS_OUT[0]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "MISO_IN[1]"   IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "MOSI_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "SCLK_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "CS_OUT[1]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+
+
+LOCATE COMP "SIG_OUT[11]"    SITE "J4";
+LOCATE COMP "SIG_OUT[4]"     SITE "J5";
+LOCATE COMP "SIG_OUT[12]"    SITE "J3";
+LOCATE COMP "SIG_OUT[25]"    SITE "K3";
+LOCATE COMP "SIG_OUT[15]"    SITE "K2";
+LOCATE COMP "SIG_OUT[32]"    SITE "J1";
+### LOCATE COMP "SIG_OUT[13]"    SITE "H1";
+LOCATE COMP "SIG_OUT[16]"    SITE "K1";
+LOCATE COMP "SIG_OUT[10]"    SITE "K4";
+LOCATE COMP "SIG_OUT[5]"     SITE "K5";
+LOCATE COMP "SIG_OUT[24]"    SITE "L4";
+LOCATE COMP "SIG_OUT[6]"     SITE "L5";
+LOCATE COMP "SIG_OUT[9]"     SITE "M5";
+LOCATE COMP "SIG_OUT[22]"    SITE "M4";
+LOCATE COMP "SIG_OUT[7]"     SITE "N5";
+LOCATE COMP "SIG_OUT[8]"     SITE "N4";
+LOCATE COMP "SIG_OUT[17]"    SITE "P5";
+LOCATE COMP "SIG_OUT[21]"    SITE "N3";
+LOCATE COMP "SIG_OUT[29]"    SITE "M3";
+LOCATE COMP "SIG_OUT[23]"    SITE "L3";
+LOCATE COMP "SIG_OUT[14]"    SITE "L2";
+LOCATE COMP "SIG_OUT[26]"    SITE "N2";
+LOCATE COMP "SIG_OUT[30]"    SITE "M1";
+LOCATE COMP "SIG_OUT[31]"    SITE "L1";
+LOCATE COMP "SIG_OUT[28]"    SITE "N1";
+LOCATE COMP "SIG_OUT[27]"    SITE "P1";
+LOCATE COMP "SIG_OUT[20]"    SITE "P2";
+LOCATE COMP "SIG_OUT[19]"    SITE "P3";
+LOCATE COMP "SIG_OUT[18]"    SITE "P4";
+
+LOCATE COMP "SIG_OUT[1]"     SITE "E9";
+LOCATE COMP "SIG_OUT[2]"     SITE "E8";
+LOCATE COMP "SIG_OUT[3]"     SITE "E7";
+LOCATE COMP "SIG_OUT[4]"     SITE "J5";
+
+DEFINE PORT GROUP "SIG_OUT_group" "SIG_OUT*";
+IOBUF GROUP  "SIG_OUT_group" IO_TYPE=LVCMOS25  DRIVE=4 SLEWRATE=SLOW BANK_VCCIO=2.5;