first working standalone ADC design

diff --git a/cts/compile.pl b/adc_standalone/compile.pl
similarity index 100%
rename from cts/compile.pl
rename to adc_standalone/compile.pl

diff --git a/cts/config.vhd b/adc_standalone/config.vhd
similarity index 93%
rename from cts/config.vhd
rename to adc_standalone/config.vhd
index 66fde1761055e292d7f4142144c286679076c452..f6137bb48258f5716d2c808b4756e83fd6213ee0 100644 (file)
--- a/cts/config.vhd
+++ b/adc_standalone/config.vhd
@@ -2,6 +2,7 @@ library ieee;
 USE IEEE.std_logic_1164.ALL;
 use ieee.numeric_std.all;
 use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
 
 package config is
 
@@ -87,16 +88,21 @@ package config is
 --End of design configuration
 ------------------------------------------------------------------------------
 
-    constant INTERFACE_NUM        : integer;
-    constant IS_UPLINK            : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
-    constant IS_DOWNLINK          : hub_ct := (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
-    constant IS_UPLINK_ONLY       : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
+    type hub_ct    is array(0 to 16) of integer;
+    type intlist_t is array(0 to 7) of integer;
+
+
+    constant INTERFACE_NUM        : integer := 1;
+    constant IS_UPLINK            : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
+    constant IS_DOWNLINK          : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
+    constant IS_UPLINK_ONLY       : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
 
 
 ------------------------------------------------------------------------------
 --Select settings by configuration 
 ------------------------------------------------------------------------------
-    constant cts_rdo_additional_ports : integer := '1'; --for internal endpoint
+    constant ADC_ACTIVE_CHANNELS      : integer := 5;
+    constant cts_rdo_additional_ports : integer := ADC_ACTIVE_CHANNELS; --for internal endpoint
 
 
 

diff --git a/cts/config_compile_frankfurt.pl b/adc_standalone/config_compile_frankfurt.pl
similarity index 79%
rename from cts/config_compile_frankfurt.pl
rename to adc_standalone/config_compile_frankfurt.pl
index 1494d39a3cb7d1f32829d0301605b3ed4eb03b5c..eae689584719421819ba858ac09af3644984e3b2 100644 (file)
--- a/cts/config_compile_frankfurt.pl
+++ b/adc_standalone/config_compile_frankfurt.pl
@@ -4,11 +4,11 @@ Package     => 'CABGA756',
 Speedgrade  => '8',
 
 
-TOPNAME                      => "trb5sc_adc",
+TOPNAME                      => "trb5sc_cts",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1710\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.12',
-synplify_path                => '/d/jspc29/lattice/synplify/T-2022.09-SP2/',
+synplify_path                => '/d/jspc29/lattice/synplify/V-2023.09-SP1/',#T-2022.09-SP2/',
 
 nodelist_file                => '../nodelist_frankfurt.txt',
 pinout_file                  => 'trb5sc_adc',
@@ -17,7 +17,7 @@ par_options                  => '../par.p2t',
 
 #Include only necessary lpf files
 include_TDC                  => 0,
-include_GBE                  => 0,
+include_GBE                  => 1,
 
 #Report settings
 firefox_open                 => 0,

diff --git a/cts/par.p2t b/adc_standalone/par.p2t
similarity index 100%
rename from cts/par.p2t
rename to adc_standalone/par.p2t

diff --git a/cts/trb5sc_cts.lpf b/adc_standalone/trb5sc_cts.lpf
similarity index 97%
rename from cts/trb5sc_cts.lpf
rename to adc_standalone/trb5sc_cts.lpf
index 41e91a5cf140a0e22c9019cfd254dfa085aaa23a..fb85d6fa030fe08f33bd639a2bbc3ebd9b28d8a7 100644 (file)
--- a/cts/trb5sc_cts.lpf
+++ b/adc_standalone/trb5sc_cts.lpf
@@ -23,6 +23,9 @@ BLOCK PATH TO   PORT "TEMP_LINE";
 BLOCK PATH FROM PORT "TEMP_LINE";
 BLOCK PATH TO   PORT "TEST_LINE*";
 
+MULTICYCLE FROM CELL "THE_HUB/THE_HUB/reset_i" 15 ns;
+
+
 #MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
 #MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
 #MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;

diff --git a/cts/trb5sc_cts.prj b/adc_standalone/trb5sc_cts.prj
similarity index 91%
rename from cts/trb5sc_cts.prj
rename to adc_standalone/trb5sc_cts.prj
index e3099ede3f76df6c21f7590ce79876424592af53..81fd75c5ce7e0d7d3298fea78ec7a7138bd8740b 100644 (file)
--- a/cts/trb5sc_cts.prj
+++ b/adc_standalone/trb5sc_cts.prj
@@ -98,6 +98,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd"
 
 
 #Flash & Reload, Tools
@@ -132,8 +133,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
 # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
 # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
-# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
-# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
 # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
 # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
@@ -208,13 +209,12 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
 
 #Hub
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
 
 add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd"
 
@@ -232,7 +232,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_contro
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
@@ -241,7 +242,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.v
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
@@ -272,7 +274,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vh
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
-
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ram_dp_true_2kx9.vhd"
 
 
 add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd"
@@ -284,6 +286,18 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd"
 add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd"
 add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd"
 
+add_file -vhdl -lib work "../adc/source/adc_package.vhd"
+add_file -vhdl -lib work "../adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd"
+add_file -vhdl -lib work "../adc/cores/mulaccsub3/mulaccsub3.vhd"
+add_file -vhdl -lib work "../adc/cores/adc_pll/adc_pll.vhd"
+add_file -vhdl -lib work "../adc/cores/adc_1ch_clk/adc_1ch_clk.vhd"
+add_file -vhdl -lib work "../adc/cores/adc_1ch/adc_1ch_edited.vhd"
+add_file -vhdl -lib work "../adc/cores/input_4ch/input_4ch_edited.vhd"
+add_file -vhdl -lib work "../adc/source/adc_input.vhd"
+add_file -vhdl -lib work "../adc/source/adc_18bit_input.vhd"
+add_file -vhdl -lib work "../adc/source/adc_processor.vhd"
+add_file -vhdl -lib work "../adc/source/adc_addon.vhd"
+
 
 
 add_file -vhdl -lib work "./trb5sc_cts.vhd"

diff --git a/cts/trb5sc_cts.vhd b/adc_standalone/trb5sc_cts.vhd
similarity index 87%
rename from cts/trb5sc_cts.vhd
rename to adc_standalone/trb5sc_cts.vhd
index c7e1b967146066bd40d240ef99a0fe04e002c4f5..4712e1a214c633f1ad72f5e539b22c141e85f65d 100644 (file)
--- a/cts/trb5sc_cts.vhd
+++ b/adc_standalone/trb5sc_cts.vhd
@@ -8,7 +8,11 @@ use work.config.all;
 use work.trb_net_std.all;\r
 use work.trb_net_components.all;\r
 use work.trb3_components.all;\r
-use work.med_sync_define.all;\r
+-- use work.med_sync_define.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.trb_net_gbe_components.all;\r
+use work.cts_pkg.all;\r
+\r
 \r
 entity trb5sc_cts is\r
   port(\r
@@ -92,7 +96,7 @@ end entity;
 \r
 architecture arch of trb5sc_cts is\r
 \r
-  constant ACTIVE_CHANNELS : integer := 5;\r
+  -- constant ACTIVE_CHANNELS : integer := ADC_ACTIVE_CHANNELS;\r
 \r
   attribute syn_keep     : boolean;\r
   attribute syn_preserve : boolean;\r
@@ -115,13 +119,14 @@ architecture arch of trb5sc_cts is
   signal int2med                     : int2med_array_t(0 to 0);\r
   signal med_stat_debug              : std_logic_vector (1*64-1 downto 0);\r
   signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+  signal reboot_from_gbe             : std_logic;\r
+  signal reset_via_gbe               : std_logic;\r
 \r
+  -- signal readout_rx                  : READOUT_RX;\r
+  -- signal readout_tx                  : readout_tx_array_t(0 to ACTIVE_CHANNELS-1);\r
 \r
-  signal readout_rx                  : READOUT_RX;\r
-  signal readout_tx                  : readout_tx_array_t(0 to ACTIVE_CHANNELS-1);\r
-\r
-  signal ctrlbus_tx, bustools_tx, buscts_rx, bustc_tx, busgbeip_rx, busgbereg_rx, bus_master_in,  busadc_tx  : CTRLBUS_TX;\r
-  signal ctrlbus_rx, bustools_rx, buscts_tx, bustc_rx, busgbeip_tx, busgbereg_tx, bus_master_out, busadc_rx  : CTRLBUS_RX;\r
+  signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in,  busadc_tx  : CTRLBUS_TX;\r
+  signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busadc_rx  : CTRLBUS_RX;\r
 \r
   signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
   signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
@@ -148,7 +153,6 @@ architecture arch of trb5sc_cts is
   signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);\r
   signal trigger_busy_i              : std_logic;\r
   signal cts_trigger_out             : std_logic;\r
-  signal cts_monitor_out             : std_logic_vector(1 downto 0);\r
 \r
   signal gbe_cts_number                   : std_logic_vector(15 downto 0);\r
   signal gbe_cts_code                     : std_logic_vector(7 downto 0);\r
@@ -220,7 +224,7 @@ begin
   THE_CLOCK_RESET : entity work.clock_reset_handler\r
     port map(\r
       CLOCK_IN       => CLK_200,\r
-      RESET_FROM_NET => '0',--med2int(0).stat_op(13),\r
+      RESET_FROM_NET => reset_via_gbe,--med2int(0).stat_op(13),\r
       SEND_RESET_IN  => '0', --med2int(0).stat_op(15),\r
 \r
       BUS_RX => bustc_rx,\r
@@ -274,20 +278,20 @@ begin
       LINK_HAS_READOUT  => "0001",\r
       LINK_HAS_SLOWCTRL => "0001",\r
       LINK_HAS_DHCP     => "0001",\r
-      -- LINK_HAS_ARP      => "0001",\r
+      LINK_HAS_ARP      => "0001",\r
       LINK_HAS_PING     => "0001",\r
       LINK_HAS_FWD      => "0000"\r
       )\r
 \r
     port map(\r
       CLK_SYS_IN               => clk_sys,\r
-      CLK_125_IN               => CLK_SUPPL_PCLK,\r
+      CLK_125_IN               => CLK_125,\r
       RESET                    => reset_i,\r
       GSR_N                    => GSR_N,\r
 \r
       TRIGGER_IN               => cts_rdo_rx.data_valid,\r
 \r
-      SD_PRSNT_N_IN(0)         => SFP_MOD0,\r
+      SD_PRSNT_N_IN(0)         => SFP_MOD_0,\r
       SD_LOS_IN(0)             => SFP_LOS,\r
       SD_TXDIS_OUT(0)          => SFP_TX_DIS,\r
 \r
@@ -330,7 +334,7 @@ begin
       BUS_REG_TX => busgbereg_tx,\r
 \r
       MAKE_RESET_OUT           => reset_via_gbe,\r
-      STATUS_OUT               => status, --open,\r
+      STATUS_OUT               => gbe_status, --open,\r
       DEBUG_OUT                => open\r
       );\r
 \r
@@ -349,7 +353,7 @@ begin
       INIT_ENDPOINT_ID              => x"0001",\r
       BROADCAST_BITMASK             => x"7E",\r
       CLOCK_FREQUENCY               => 100,\r
-      USE_ONEWIRE                   => c_YES,\r
+      USE_ONEWIRE                   => c_I2C,\r
       BROADCAST_SPECIAL_ADDR        => BROADCAST_SPECIAL_ADDR,\r
       RDO_ADDITIONAL_PORT           => cts_rdo_additional_ports,\r
       RDO_DATA_BUFFER_DEPTH         => EVENT_BUFFER_SIZE,\r
@@ -361,7 +365,7 @@ begin
       CLK    => clk_sys,\r
       RESET  => reset_i,\r
       CLK_EN => '1',\r
-\r
+  \r
       -- Media interfacces ---------------------------------------------------------------\r
       MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0)  => open,\r
       MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0)      => open,\r
@@ -371,9 +375,10 @@ begin
       MED_DATA_IN(INTERFACE_NUM*16-1 downto 0)       => (others => '0'),\r
       MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0)  => (others => '0'),\r
       MED_READ_OUT(INTERFACE_NUM*1-1 downto 0)       => open,\r
-      MED_STAT_OP(INTERFACE_NUM*16-1 downto 0)       => open,\r
-      MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0)       => (others => '0'),\r
-\r
+      MED_STAT_OP(2 downto 0)                        => ERROR_NC,\r
+      MED_STAT_OP(INTERFACE_NUM*16-1 downto 3)       => (others => '0'),\r
+      MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0)       => open,\r
+  \r
      -- Gbe Read-out Path ---------------------------------------------------------------\r
       --Event information coming from CTS for GbE\r
       GBE_CTS_NUMBER_OUT          => gbe_cts_number,\r
@@ -390,7 +395,7 @@ begin
       GBE_FEE_READ_IN             => gbe_fee_read,\r
       GBE_FEE_STATUS_BITS_OUT     => gbe_fee_status_bits,\r
       GBE_FEE_BUSY_OUT            => gbe_fee_busy,\r
-\r
+  \r
       -- CTS Request Sending -------------------------------------------------------------\r
       --LVL1 trigger\r
       CTS_TRG_SEND_IN         => cts_trg_send,\r
@@ -409,7 +414,7 @@ begin
       -- Receiver port\r
       CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits,\r
       CTS_IPU_BUSY_OUT        => cts_ipu_busy,\r
-\r
+  \r
       -- CTS Data Readout ----------------------------------------------------------------\r
       --Trigger to CTS out\r
       RDO_TRIGGER_IN             => cts_trigger_out,\r
@@ -421,7 +426,7 @@ begin
       RDO_TRG_CODE_OUT           => cts_rdo_rx.trg_code,\r
       RDO_TRG_INFORMATION_OUT    => cts_rdo_rx.trg_information,\r
       RDO_TRG_NUMBER_OUT         => cts_rdo_rx.trg_number,\r
-\r
+  \r
       --Data from CTS in\r
       RDO_TRG_STATUSBITS_IN        => cts_rdo_trg_status_bits_cts,\r
       RDO_DATA_IN                  => cts_rdo_data,\r
@@ -432,12 +437,14 @@ begin
       RDO_ADDITIONAL_DATA          => cts_rdo_additional_data,\r
       RDO_ADDITIONAL_WRITE         => cts_rdo_additional_write,\r
       RDO_ADDITIONAL_FINISHED      => cts_rdo_additional_finished,\r
-\r
+  \r
       -- Slow Control --------------------------------------------------------------------\r
       COMMON_STAT_REGS    => open,\r
       COMMON_CTRL_REGS    => common_ctrl_reg,\r
-      ONEWIRE             => TEMPSENS,\r
+      ONEWIRE             => open,\r
       ONEWIRE_MONITOR_IN  => open,\r
+      I2C_SCL             => I2C_SCL,\r
+      I2C_SDA             => I2C_SDA,\r
       MY_ADDRESS_OUT      => timer.network_address,\r
       UNIQUE_ID_OUT       => timer.uid,\r
       BUS_MASTER_IN             => bus_master_in,\r
@@ -447,7 +454,7 @@ begin
       TIMER_TICKS_OUT(1)  => timer.tick_ms,\r
       TEMPERATURE_OUT     => timer.temperature,\r
       EXTERNAL_SEND_RESET => reset_via_gbe,\r
-\r
+  \r
       REGIO_ADDR_OUT            => ctrlbus_rx.addr,\r
       REGIO_READ_ENABLE_OUT     => ctrlbus_rx.read,\r
       REGIO_WRITE_ENABLE_OUT    => ctrlbus_rx.write,\r
@@ -458,7 +465,7 @@ begin
       REGIO_WRITE_ACK_IN        => wrack,\r
       REGIO_UNKNOWN_ADDR_IN     => ctrlbus_tx.unknown,\r
       REGIO_TIMEOUT_OUT         => ctrlbus_rx.timeout,\r
-\r
+  \r
       --Gbe Sctrl Input\r
       GSC_INIT_DATAREADY_IN    => gsc_init_dataready,\r
       GSC_INIT_DATA_IN         => gsc_init_data,\r
@@ -469,7 +476,7 @@ begin
       GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,\r
       GSC_REPLY_READ_IN        => gsc_reply_read,\r
       GSC_BUSY_OUT             => gsc_busy,\r
-\r
+  \r
       --status and control ports\r
       HUB_STAT_CHANNEL => open,\r
       HUB_STAT_GEN     => open,\r
@@ -477,26 +484,26 @@ begin
       MPLEX_STAT       => open,\r
       STAT_REGS        => open,\r
       STAT_CTRL_REGS   => open,\r
-\r
+  \r
       --Fixed status and control ports\r
       STAT_DEBUG => open,\r
       CTRL_DEBUG => (others => '0')\r
       );\r
-\r
-\r
+  \r
+  \r
   gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate\r
     cts_rdo_additional_data(31 + i*32 downto 32*i)            <= cts_rdo_additional(i).data;\r
     cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits;\r
-\r
+  \r
     cts_rdo_additional_write(i)                               <= cts_rdo_additional(i).data_write;\r
     cts_rdo_additional_finished(i)                            <= cts_rdo_additional(i).data_finished;\r
-\r
+  \r
   end generate;\r
-\r
-\r
+  \r
+  \r
   rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack;\r
   wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;\r
-\r
+  \r
 \r
 ---------------------------------------------------------------------------\r
 -- CTS\r
@@ -504,32 +511,32 @@ begin
     THE_CTS : CTS\r
       generic map (\r
         EXTERNAL_TRIGGER_ID => ETM_ID,  -- fill in trigger logic enumeration id of external trigger logic\r
-        PLATTFORM => 6, --TRB5sc\r
+        PLATTFORM => 5, --TRB5sc\r
         OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,\r
         ADDON_GROUPS      => 1,\r
-        ADDON_GROUP_UPPER => (12, others => 0)\r
+        ADDON_GROUP_UPPER => (11, others => 0)\r
         )\r
       port map (\r
         CLK   => clk_sys,\r
         RESET => reset_i,\r
-\r
+  \r
         TRIGGER_BUSY_OUT   => trigger_busy_i,\r
         TIME_REFERENCE_OUT => cts_trigger_out,\r
-\r
+  \r
         ADDON_TRIGGERS_IN        => cts_addon_triggers_in,\r
         ADDON_GROUP_ACTIVITY_OUT => open,\r
         ADDON_GROUP_SELECTED_OUT => open,\r
-\r
+  \r
         EXT_TRIGGER_IN     => '0',\r
         EXT_STATUS_IN      => (others => '0'),\r
         EXT_CONTROL_OUT    => open,\r
         EXT_HEADER_BITS_IN => (others => '0'),\r
         EXT_FORCE_TRIGGER_INFO_IN => (others => '0'),\r
-\r
+  \r
         PERIPH_TRIGGER_IN => (others => '0'),\r
-\r
+  \r
         OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out,\r
-\r
+  \r
         CTS_TRG_SEND_OUT        => cts_trg_send,\r
         CTS_TRG_TYPE_OUT        => cts_trg_type,\r
         CTS_TRG_NUMBER_OUT      => cts_trg_number,\r
@@ -537,7 +544,7 @@ begin
         CTS_TRG_RND_CODE_OUT    => cts_trg_code,\r
         CTS_TRG_STATUS_BITS_IN  => cts_trg_status_bits,\r
         CTS_TRG_BUSY_IN         => cts_trg_busy,\r
-\r
+  \r
         CTS_IPU_SEND_OUT        => cts_ipu_send,\r
         CTS_IPU_TYPE_OUT        => cts_ipu_type,\r
         CTS_IPU_NUMBER_OUT      => cts_ipu_number,\r
@@ -545,7 +552,7 @@ begin
         CTS_IPU_RND_CODE_OUT    => cts_ipu_code,\r
         CTS_IPU_STATUS_BITS_IN  => cts_ipu_status_bits,\r
         CTS_IPU_BUSY_IN         => cts_ipu_busy,\r
-\r
+  \r
         CTS_REGIO_ADDR_IN          => buscts_rx.addr,\r
         CTS_REGIO_DATA_IN          => buscts_rx.data,\r
         CTS_REGIO_READ_ENABLE_IN   => buscts_rx.read,\r
@@ -554,21 +561,21 @@ begin
         CTS_REGIO_DATAREADY_OUT    => buscts_tx.rack,\r
         CTS_REGIO_WRITE_ACK_OUT    => buscts_tx.wack,\r
         CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown,\r
-\r
+  \r
         LVL1_TRG_DATA_VALID_IN     => cts_rdo_rx.data_valid,\r
         LVL1_VALID_TIMING_TRG_IN   => cts_rdo_rx.valid_timing_trg,\r
         LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg,\r
         LVL1_INVALID_TRG_IN        => cts_rdo_rx.invalid_trg,\r
-\r
+  \r
         FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts,\r
         FEE_DATA_OUT           => cts_rdo_data,\r
         FEE_DATA_WRITE_OUT     => cts_rdo_write,\r
         FEE_DATA_FINISHED_OUT  => cts_rdo_finished\r
         );\r
-\r
-  cts_addon_triggers_in(12 downto 4) <= HDR_IO(23 downto 16);\r
+  \r
+  cts_addon_triggers_in(11 downto 4) <= HDR_IO(23 downto 16);\r
   cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i;\r
-\r
+  \r
   buscts_tx.nack <= '0';\r
   buscts_tx.ack  <= '0';\r
 \r
@@ -577,33 +584,33 @@ begin
 ---------------------------------------------------------------------------\r
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
     generic map(\r
-      PORT_NUMBER      => 4,\r
-      PORT_ADDRESSES   => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"a000",  others => x"0000"),\r
-      PORT_ADDR_MASK   => (0 => 12,      1 => 9,       2 => 1,       3 => 12,      4 => 8,       5 => 8,       6 => 11,        others => 0),\r
+      PORT_NUMBER      => 6,\r
+      PORT_ADDRESSES   => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300",   others => x"0000"),\r
+      PORT_ADDR_MASK   => (0 => 12,      1 => 11,      2 => 1,       3 => 12,      4 => 8,       5 => 8,         others => 0),\r
       PORT_MASK_ENABLE => 1\r
       )\r
     port map(\r
       CLK   => clk_sys,\r
       RESET => reset_i,\r
-\r
+  \r
       REGIO_RX => ctrlbus_rx,\r
       REGIO_TX => ctrlbus_tx,\r
-\r
+  \r
       BUS_RX(0) => bustools_rx,         --Flash, SPI, UART, ADC, SED\r
-      BUS_RX(1) => bussci_rx,           --SCI Serdes\r
+      -- BUS_RX(1) => bussci_rx,           --SCI Serdes\r
+      BUS_RX(1) => buscts_rx,\r
       BUS_RX(2) => bustc_rx,            --Clock switch\r
       BUS_RX(3) => busadc_rx,\r
       BUS_RX(4) => busgbeip_rx,\r
       BUS_RX(5) => busgbereg_rx,\r
-      BUS_RX(6) => buscts_rx,\r
-\r
+  \r
       BUS_TX(0) => bustools_tx,\r
-      BUS_TX(1) => bussci_tx,\r
+      -- BUS_TX(1) => bussci_tx,\r
+      BUS_TX(1) => buscts_tx,\r
       BUS_TX(2) => bustc_tx,\r
       BUS_TX(3) => busadc_tx,\r
       BUS_TX(4) => busgbeip_tx,\r
       BUS_TX(5) => busgbereg_tx,\r
-      BUS_TX(6) => buscts_tx,\r
       STAT_DEBUG => open\r
       );\r
 \r
@@ -616,7 +623,9 @@ begin
       ADC_CMD_2        => x"1d5cb",\r
       ADC_CMD_3        => x"1e3cb",\r
       ADC_CMD_4        => x"2f5cb",\r
-      ADC_CMD_T        => x"1F393"\r
+      ADC_CMD_T        => x"1F393",\r
+      NUM_COINCIDENCES => 4,\r
+      NUM_MULTIPLICITIES => 1\r
       )\r
     port map(\r
       CLK   => clk_sys,\r
@@ -683,7 +692,7 @@ begin
 ---------------------------------------------------------------------------\r
   THE_ADDON : entity work.adc_addon\r
     generic map(\r
-      ACTIVE_CHANNELS => ACTIVE_CHANNELS\r
+      ACTIVE_CHANNELS => ADC_ACTIVE_CHANNELS\r
       )\r
     port map(\r
       CLK           => clk_sys,\r
@@ -701,9 +710,9 @@ begin
       CNV_B         => CNV_B,\r
       TESTPAT_B     => TESTPAT_B,\r
 \r
-      TRIGGER_OUT   => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0),\r
-      READOUT_RX    => readout_rx,\r
-      READOUT_TX    => readout_tx,\r
+      TRIGGER_OUT   => adc_trigger_i(ADC_ACTIVE_CHANNELS-1 downto 0),\r
+      READOUT_RX    => cts_rdo_rx,\r
+      READOUT_TX    => cts_rdo_additional(0 to ADC_ACTIVE_CHANNELS-1),\r
 \r
       BUS_RX        => busadc_rx,\r
       BUS_TX        => busadc_tx\r
@@ -714,15 +723,18 @@ begin
 ---------------------------------------------------------------------------\r
 -- LED\r
 ---------------------------------------------------------------------------\r
+  LED_SFP_GREEN  <= not (gbe_status(0) and gbe_status(1) and gbe_status(2)); --'0';\r
+  LED_SFP_YELLOW <= gbe_status(8);\r
+  LED_SFP_RED    <= not (gbe_status(3) or gbe_status(4)); --'0';\r
 \r
-  LED_SFP_GREEN  <= not med2int(0).stat_op(9);\r
-  LED_SFP_RED    <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
-  LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+  -- LED_SFP_GREEN  <= not med2int(0).stat_op(9);\r
+  -- LED_SFP_RED    <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+  -- LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
   LED            <= x"FF";\r
   LED_RJ_GREEN(1)<= not external_clock_lock or led_off;                 --on if external clock used\r
-  LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0';  --on if SFP is used  (next to SFP)\r
+  LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0';                    --on if SFP is used  (next to SFP)\r
   LED_RJ_RED(1)  <= external_clock_lock or led_off;                     --on if internal clock used\r
-  LED_RJ_RED(0)  <= '1' when SERDES_NUM = 1 or led_off = '1' else '0';  --on if backplane is used   (next to SFP)\r
+  LED_RJ_RED(0)  <= '1';                                                --on if backplane is used   (next to SFP)\r
   LED_EXT_CLOCK  <= IN_SELECT_EXT_CLOCK or led_off;                     --on if trigger/clock from RJ45 is used\r
 \r
   TEST(13 downto 1)    <= (others => '0');\r
@@ -733,9 +745,9 @@ begin
 -------------------------------------------------------------------------------\r
 -- No trigger/data endpoint included\r
 -------------------------------------------------------------------------------\r
-readout_tx(0).data_finished <= '1';\r
-readout_tx(0).data_write    <= '0';\r
-readout_tx(0).busy_release  <= '1';\r
+-- cts_rdo_additional(0).data_finished <= '1';\r
+-- cts_rdo_additional(0).data_write    <= '0';\r
+-- cts_rdo_additional(0).busy_release  <= '1';\r
   \r
   \r
 end architecture;\r