*** empty log message ***

diff --git a/syncmode/compile_central_frankfurt.pl b/syncmode/compile_central_frankfurt.pl
index 133bd0c20e99565755eb483aaa0d5202be7c445f..27f8573f1e27fd172ccdd33b5fdeee2c9a3b4eac 100755 (executable)
--- a/syncmode/compile_central_frankfurt.pl
+++ b/syncmode/compile_central_frankfurt.pl
@@ -12,7 +12,7 @@ my $TOPNAME                      = "trb3_central";  #Name of top-level entity
 my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
 #my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
 # my $synplify_path                = '/d/jspc29/lattice/synplify/fpga_e201103/';
-my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 ###################################################################################

diff --git a/syncmode/trb3_central.prj b/syncmode/trb3_central.prj
index 71df6d33e53a97b530ab993657792916c8243d68..622edddf2c23fc9efa318cbec573080ef1b7e149 100644 (file)
--- a/syncmode/trb3_central.prj
+++ b/syncmode/trb3_central.prj
@@ -34,6 +34,12 @@ set_option -write_vhdl 1
 # automatic place and route (vendor) options
 set_option -write_apr_constraint 0
 
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+   
+
 # set result format/file last
 project -result_format "edif"
 project -result_file "workdir/trb3_central.edf"
@@ -218,7 +224,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4
 
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "./trb3_central.vhd"
-
+add_file -fpga_constraint "./project/full/full.fdc"
 
 
 

diff --git a/syncmode/trb3_central.vhd b/syncmode/trb3_central.vhd
index ba354ed7913827fe2bc71182dd03f3fb9f832a15..07d05539e2d0d3dc3ff9cf297ec1946c8eeed84b 100644 (file)
--- a/syncmode/trb3_central.vhd
+++ b/syncmode/trb3_central.vhd
@@ -377,7 +377,6 @@ THE_MEDIA_UPLINK : med_ecp3_sfp_sync
     MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
     MED_DATAREADY_OUT  => med_dataready_in(0),
     MED_READ_IN        => med_read_out(0),
-    REFCLK2CORE_OUT    => open,
     CLK_RX_HALF_OUT    => rx_clock_100,
     CLK_RX_FULL_OUT    => rx_clock_200,
     
@@ -876,7 +875,7 @@ LED_YELLOW <= link_ok; --debug(3);
   TEST_LINE(16)           <= 'Z';
   TEST_LINE(31 downto 17) <= med_stat_debug(31 downto 17);
   
-  CLK_TEST_OUT <= clk_200_i & clk_100_internal & clk_100_i;
+  CLK_TEST_OUT <= clk_100_internal & clk_200_i & clk_100_i;
   
 
 --   FPGA1_CONNECTOR(0) <= '0';
@@ -895,4 +894,4 @@ LED_YELLOW <= link_ok; --debug(3);
     end process;
 
 
-end architecture;
+end architecture;
\ No newline at end of file

diff --git a/wasa/compile_padiwa_frankfurt.pl b/wasa/compile_padiwa_frankfurt.pl
index 6b41d05441c90f65931c896d6073b092721113ed..a417c27e9e9ced218226e67da096ab865994437e 100755 (executable)
--- a/wasa/compile_padiwa_frankfurt.pl
+++ b/wasa/compile_padiwa_frankfurt.pl
@@ -9,8 +9,8 @@ use strict;
 ###################################################################################
 #Settings for this project
 my $TOPNAME                      = "trb3_periph_padiwa";  #Name of top-level entity
-my $lattice_path                 = '/d/jspc29/lattice/diamond/2.0';
-my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
+my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 #my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 my $lm_license_file_for_par      = "1710\@cronos.e12.physik.tu-muenchen.de";
@@ -115,7 +115,8 @@ execute($c);
 system("rm $TOPNAME.ncd");
 
 
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
 # IOR IO Timing Report

diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd
index 6587ec3d203f3ff499cd57297835c76017345847..b87129374444d4f9a6c9ab0653713648c0e70c03 100644 (file)
--- a/wasa/trb3_periph_padiwa.vhd
+++ b/wasa/trb3_periph_padiwa.vhd
@@ -729,7 +729,7 @@ begin
 -------------------------------------------------------------------------------
   THE_TDC : TDC
     generic map (
-      CHANNEL_NUMBER => 5,             -- Number of TDC channels
+      CHANNEL_NUMBER => 33,             -- Number of TDC channels
       STATUS_REG_NR  => REGIO_NUM_STAT_REGS,
       CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
     port map (
@@ -737,7 +737,7 @@ begin
       CLK_TDC               => clk_tdc,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
-      HIT_IN                => hit_in_i(3 downto 0),  -- Channel start signals
+      HIT_IN                => hit_in_i(31 downto 0),  -- Channel start signals
       TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --