\label{RegIO}
-The RegIO component handles all data received on the slow control channel. Its structure
-is depicted in figure~\ref{fig:regio}. It provides status registers that are common for
-all boards, user defineable status and control registers, and stores information about
-the hardware. As already mentioned, these common registers are needed to provide a
+The RegIO component handles all data received on the slow control channel. Its structure
+is depicted in figure~\ref{fig:regio}. It provides status registers that are common for
+all boards, user defineable status and control registers, and stores information about
+the hardware. As already mentioned, these common registers are needed to provide a
universal monitoring tool for all parts of the detector.
Each register has one 16bit address assigned as shown in Table~\ref{regioaddressmap}.
section about addresses} \\
\hline
\end{tabular}
- \caption{[Register read/write protocol]Register read/write protocol. The config word for
-multiple accesses has the highest bit selecting between fixed (0) addresses and ascending
-(1) addresses. The lower 15bit on the read operation select the maximum number of read
-accesses to be made. A multiple write always consists of one starting word containing
+ \caption{[Register read/write protocol]Register read/write protocol. The config word for
+multiple accesses has the highest bit selecting between fixed (0) addresses and ascending
+(1) addresses. The lower 15bit on the read operation select the maximum number of read
+accesses to be made. A multiple write always consists of one starting word containing
address and mode followed by an arbitrary number of data packets.}
\label{RegIO:protocol}
\end{center}
\end{table}
-Internally it also has logic to readout the 1-wire temperature logic and to assign network
-addresses. Other features include a global timer and configurable easy-to-use status and
+Internally it also has logic to readout the 1-wire temperature logic and to assign network
+addresses. Other features include a global timer and configurable easy-to-use status and
control registers. Additional, more complex logic can be connected to the internal data bus.
The ports on the user interface can be divided into several sets:
\paragraph{Registers}
\label{RegIORegisters}
-There are four types of registers provided by RegIO: Common registers that are defined for all
-boards in the same way and user specific resgisters. These two sets are further divided into
-status registers that can be written by the internal logic and control registers that can be
-written over the network. The registers have a size of 32bit each. The number of user registers
+There are four types of registers provided by RegIO: Common registers that are defined for all
+boards in the same way and user specific resgisters. These two sets are further divided into
+status registers that can be written by the internal logic and control registers that can be
+written over the network. The registers have a size of 32bit each. The number of user registers
in each of the four groups can be set using generics (see \ref{regiogenerics}).
-For each register there is a strobe signal that shows read access (in case of status register) or
-write access (in case of control registers) from the network side. The following listing shows
+For each register there is a strobe signal that shows read access (in case of status register) or
+write access (in case of control registers) from the network side. The following listing shows
the name of all ports:
\lstset { caption ={Register Ports on RegIO}}
\paragraph{Onewire}
-The temperature sensor on each board is connected to the following ports. In case no temperature
-sensor is connected directly, the generic setting \genericname{Regio\_\-Use\_\-1wire\_\-Interface}
+The temperature sensor on each board is connected to the following ports. In case no temperature
+sensor is connected directly, the generic setting \genericname{Regio\_\-Use\_\-1wire\_\-Interface}
has to be set accordingly.
\begin{description}
\item[\portname{Regio\_Onewire\_Inout}] Direct connection to a 1-wire temperature sensor
- \item[\portname{Regio\_Onewire\_Monitor\_Out}] Outputs a copy of the signals on the 1-wire bus.
+ \item[\portname{Regio\_Onewire\_Monitor\_Out}] Outputs a copy of the signals on the 1-wire bus.
Used to transport information to another FPGA.
- \item[\portname{Regio\_Onewire\_Monitor\_In}] The corresponding input to monitor traffic on a
+ \item[\portname{Regio\_Onewire\_Monitor\_In}] The corresponding input to monitor traffic on a
1-wire bus if no sensor is connected directly to the fpga.
\end{description}
\paragraph{Timers}
-The timers give a rough information on the current time. The global time can be set using normal
-slow control accesses. That means, it has an inherent ambiguity of about 200ns plus a drift of up
-to 20ppm compared to other boards. The additional timer ticks can be used to simplify other parts
+The timers give a rough information on the current time. The global time can be set using normal
+slow control accesses. That means, it has an inherent ambiguity of about 200ns plus a drift of up
+to 20ppm compared to other boards. The additional timer ticks can be used to simplify other parts
of the logic, e.g. as clock enable signal for slowly running parts of the design.
\begin{description}
- \item[\portname{Global\_Time\_Out}] The global time measured in microseconds. This time will be
-synchronized on all boards from time to time to keep descrepancies between the boards low. E.g.
+ \item[\portname{Global\_Time\_Out}] The global time measured in microseconds. This time will be
+synchronized on all boards from time to time to keep descrepancies between the boards low. E.g.
used for marking debugging and status information.
- \item[\portname{Local\_Time\_Out}] The local time is used to measure in the sub-microsecond range.
+ \item[\portname{Local\_Time\_Out}] The local time is used to measure in the sub-microsecond range.
It counts with the internal clock frequency (standard: 100 MHz) and is reset each microsecond.
- \item[\portname{Time\_Since\_Last\_Trg\_Out}] The time since the last timing trigger has been received,
+ \item[\portname{Time\_Since\_Last\_Trg\_Out}] The time since the last timing trigger has been received,
measured in clock cycles.
- \item[\portname{Timer\_Us\_Tick\_Out}] A tickmark that is set every microsecond for one clock cycle.
+ \item[\portname{Timer\_Us\_Tick\_Out}] A tickmark that is set every microsecond for one clock cycle.
Can be used to clock internal slow running logic.
- \item[\portname{Timer\_Ms\_Tick\_Out}] A tickmark that is set every 1024 us for one clock cycle.
+ \item[\portname{Timer\_Ms\_Tick\_Out}] A tickmark that is set every 1024 us for one clock cycle.
Can be used to clock internal slow running logic.
\end{description}
\paragraph{Internal Data Bus}
-An access cycle on the internal data bus consists of two actions: First, RegIO sends a read or a
-write strobe. At the same time \portname{address} and \portname{data\_out} are valid. Afterwards
-it waits up to 32 clock cycles for a reaction of the connected logic. This can be either of
-\portname{dataready}, \portname{no\_more\_data}, \portname{write\_ack} or \portname{unknown\_addr}
+An access cycle on the internal data bus consists of two actions: First, RegIO sends a read or a
+write strobe. At the same time \portname{address} and \portname{data\_out} are valid. Afterwards
+it waits up to 32 clock cycles for a reaction of the connected logic. This can be either of
+\portname{dataready}, \portname{no\_more\_data}, \portname{write\_ack} or \portname{unknown\_addr}
as described below. If the logic fails to answer, an automatic timeout is generated.
\begin{description}
- \item[\portname{Regio\_Addr\_Out}] (16 bit) address port. Address is valid when either of
+ \item[\portname{Regio\_Addr\_Out}] (16 bit) address port. Address is valid when either of
\portname{read\_enable} and \portname{write\_enable} is high.
\item[\portname{Regio\_Read\_Enable\_Out}] Read enable strobe.
\item[\portname{Regio\_Write\_Enable\_Out}] Write enable strobe.
- \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when
+ \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when
\portname{write\_\-enable} is high.
- \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when
+ \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when
\portname{dataready\_\-in} is high.
- \item[\portname{Regio\_Dataready\_In}] User signal to show that \portname{data\_in} is valid. May
+ \item[\portname{Regio\_Dataready\_In}] User signal to show that \portname{data\_in} is valid. May
only be used after a strobe on \portname{read\_enable}.
- \item[\portname{Regio\_No\_More\_Data\_In}] User signal. After a read strobe: User has no more data
+ \item[\portname{Regio\_No\_More\_Data\_In}] User signal. After a read strobe: User has no more data
to read from this address. After a write strobe: User is not able to handle more data on this address now.
- \item[\portname{Regio\_Write\_Ack\_In}] User signal. Acknowledge after a strobe on \portname{write\_enable}
+ \item[\portname{Regio\_Write\_Ack\_In}] User signal. Acknowledge after a strobe on \portname{write\_enable}
and writing was successful.
- \item[\portname{Regio\_Unknown\_Addr\_In}] User signal. After either read or write strobe: The given
+ \item[\portname{Regio\_Unknown\_Addr\_In}] User signal. After either read or write strobe: The given
address is not in use.
- \item[\portname{Regio\_Timeout\_Out}] About 24 to 32 clock cycles after a read or write strobe RegIO
+ \item[\portname{Regio\_Timeout\_Out}] About 24 to 32 clock cycles after a read or write strobe RegIO
terminates the access assuming the user logic does not react.
\end{description}
\paragraph{Generic Settings}
\label{regiogenerics}
\begin{description}
- \item[\portname{Regio\_Num\_Stat\_Regs}] The number of status registers (addr. 0x80 ff).
+ \item[\portname{Regio\_Num\_Stat\_Regs}] The number of status registers (addr. 0x80 ff).
This value is log2 of the desired number of 32bit registers
- \item[\portname{Regio\_Num\_Ctrl\_Regs}] The number of control registers (addr. 0xc0 ff).
+ \item[\portname{Regio\_Num\_Ctrl\_Regs}] The number of control registers (addr. 0xc0 ff).
This value is log2 of the desired number of 32bit registers
- \item[\portname{Regio\_Init\_Ctrl\_Regs}] The initial value of all control registers.
+ \item[\portname{Regio\_Init\_Ctrl\_Regs}] The initial value of all control registers.
This generic has a fixed size of 8x32 bits
- \item[\portname{Regio\_Use\_Dat\_Port}] Selects to have an internal data port to connect
+ \item[\portname{Regio\_Use\_Dat\_Port}] Selects to have an internal data port to connect
own registers to in the address space above 0x0100
- \item[\portname{Regio\_Use\_1wire\_Interface}] Set to \constname{c\_Yes} means a temperature
-sensor is connected, \constname{c\_\-Mon\-itor} means there is a 1-wire data stream sent by
+ \item[\portname{Regio\_Use\_1wire\_Interface}] Set to \constname{c\_Yes} means a temperature
+sensor is connected, \constname{c\_\-Mon\-itor} means there is a 1-wire data stream sent by
another FPGA, \constname{c\_No} means temperature and unique id are written using some user supplied logic.
- \item[\portname{Use\_Dat\_Port}] The internal data port can be switched off if not in use.
+ \item[\portname{Use\_Dat\_Port}] The internal data port can be switched off if not in use.
Hence, all accesses to addresses above 0x100 will be automatically answered by RegIO.
- \item[\portname{Init\_Address}] The network address the board is given initially. (note:
+ \item[\portname{Init\_Address}] The network address the board is given initially. (note:
may not work using Synplify under Linux, depending on the compiler version)
- \item[\portname{Init\_Endpoint\_Id}] The endpoint ID. On boards with two or more FPGAs
-this is usually the FPGA number according to the boards schematics. Boards with only one FPGA
-use 1 here. Basic Rule: Each FPGA connected to the same temperature sensore has to have a different
+ \item[\portname{Init\_Endpoint\_Id}] The endpoint ID. On boards with two or more FPGAs
+this is usually the FPGA number according to the boards schematics. Boards with only one FPGA
+use 1 here. Basic Rule: Each FPGA connected to the same temperature sensore has to have a different
endpoint ID to be indentifieable.
- \item[\portname{Compile\_Time}] The UNIX timestamp when the design has been compiled. Must be set
+ \item[\portname{Compile\_Time}] The UNIX timestamp when the design has been compiled. Must be set
by hand or using our standard compile script.
\item[\portname{Hardware\_Version}] These 32bit give information about the type of hardware. The
upper 16~bit are defined in table \ref{HardwareInformation}, the lower 16~bits are free to use.
\subsection{RegIo Bus Handler}
-If you want to connect several registers or function blocks to the internal data bus, you can use the
-RegIO Bus Handler. This special entity (\filename{trb\_net16\_regio\_bus\_handler}) simplifies to
-generate several address sub-spaces on the internal data bus. It is configured using three generic
-values as shown in the listing below. These settings introduce two address spaces: One starting at
-0xA000 with a size of 2**8 addresses, i.e. from 0xA000 to 0xA0FF, and one starting at 0x8000 with
+If you want to connect several registers or function blocks to the internal data bus, you can use the
+RegIO Bus Handler. This special entity (\filename{trb\_net16\_regio\_bus\_handler}) simplifies to
+generate several address sub-spaces on the internal data bus. It is configured using three generic
+values as shown in the listing below. These settings introduce two address spaces: One starting at
+0xA000 with a size of 2**8 addresses, i.e. from 0xA000 to 0xA0FF, and one starting at 0x8000 with
2**6 addresses, i.e. from 0x8000 to 0x803F.
-The behaviour on the data busses is identical to the original RegIO interface. Connecting to the
+The behaviour on the data busses is identical to the original RegIO interface. Connecting to the
different address spaces can be done in a convenient form.
\subsection{Register Map}
-Table \ref{regioaddressmap} shows a list of most defined registers within the slow control endpoint.
+Table \ref{regioaddressmap} shows a list of most defined registers within the slow control endpoint.
The common status and control registers are further explained in the next section.
\begin{table}[htbp]
\hline\hline
00 & common status register 0 & CSR0 & Basic Error Flags and Temperature (see below) (r) \\
01 & common status register 1 & CSR1 & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\
+02 & common status register 2 & CSR2 & Status of LVL1 handler \\
+03 & common status register 3 & CSR3 & Trigger input monitor. Bit 15..0: Edge count, Bit 31..16: Length of last pulse \\
20 & common control register 0 & CCR0 & Strobes for board resets and test triggers (see below) (w)\\
21 & common control register 1 & CCR1 & Sets LVL1 trigger number (Bits 15..0) (r/w)\\
22 & common control register 2 & CCR2 & frontend enable, trigger enable, debug enable (r/w)\\
\paragraph{Common Control and Status Registers (0x00 - 0x01, 0x20 - 0x22)}
-The first common status register (0x00) is described in table \ref{CommonStatReg0}. It is used for error flags
-and readback of the boards temperature. The second status register (0x01) is used to read the LVL1 trigger number
-of the last timing trigger (Bits 15 -- 0) and the number of the event last read on the IPU channel
+The first common status register (0x00) is described in table \ref{CommonStatReg0}. It is used for error flags
+and readback of the boards temperature. The second status register (0x01) is used to read the LVL1 trigger number
+of the last timing trigger (Bits 15 -- 0) and the number of the event last read on the IPU channel
(Bits 31 -- 16).
-\noindent The first common control register (0x20) consists of strobe signals for dummy timing triggers and reset
-signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a
-delay of about 3~us has to be included to allow the endpoint to send back a correct answer.
+\noindent The first common control register (0x20) consists of strobe signals for dummy timing triggers and reset
+signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a
+delay of about 3~us has to be included to allow the endpoint to send back a correct answer.
-\noindent The second common control register (0x21) is used to set the current LVL1 trigger number (Bits 15 -- 0)
-and the number of received timing triggers (Bits 31-16).
+\noindent The second common control register (0x21) is used to set the current LVL1 trigger number (Bits 15 -- 0)
+and the number of received timing triggers (Bits 31-16).
-\noindent The third control register (0x22) includes frontend enable bits (Bits 15 -- 0), as well as a trigger
-enable bit (Bit 31), a debug enable bit (Bit 30), and three data format bits for general usage (Bits 23 -- 20).
+\noindent The third control register (0x22) includes frontend enable bits (Bits 15 -- 0), as well as a trigger
+enable bit (Bit 31), a debug enable bit (Bit 30), and three data format bits for general usage (Bits 23 -- 20).
A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
\begin{table}
\textbf{Bits} & \textbf{Description} \\
\hline\hline
31 -- 20 & temperature \\
-19 -- 13 & reserved \\
+19 -- 14 & reserved \\
+13 & Timing Trigger Input \\
12 & Last event sent on IPU is broken\\
11 & Severe problem in event data buffer / IPU request handler\\
10 & IPU requested event partially not found / data missing\\
\end{center}
\end{table}
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 27 & reserved \\
+26 -- 16 & delay between timing trigger and LVL1 trigger \\
+15 & found timing trigger \\
+14 & LVL1 data valid \\
+13 & multiple timing triggers found \\
+12 & trigger number match \\
+11 & timeout found \\
+10 -- 4 & reserved \\
+3 -- 0 & Status of LVL1 handler state machine. 0: idle, 1: timing trigger found, 3: LVL1 trigger received, 5: bad combination of timing trigger and LVL1 trigger, 7: done.\\
+\hline
+\end{tabularx}
+\caption{Common Status Register 2}
+\label{CommonStatReg2}
+\end{center}
+\end{table}
+
+
+
+
+
+
+
+
+
+
\begin{table}
\begin{center}
\hline\hline
31 & enable trigger \\
30 & enable debug \\
-29 -- 24 & reserved \\
+29 & invert timing trigger \\
+28 -- 24 & reserved \\
23 -- 20 & data format \\
19 -- 16 & reserved \\
15 -- 0 & enable frontends \\
\paragraph{Hardware Information (0x42)}
-This register holds information about the type of hardware. The upper 16 bit define the hardware type,
-the lower 16 bit are kept free to mark minor differences in the hardware setup such as optional patch
-wires used in the design. Design variants can also be marked using these bits. Their definition is
-given in the section dealing with detector specific features. The upper 16 bit are defined in
+This register holds information about the type of hardware. The upper 16 bit define the hardware type,
+the lower 16 bit are kept free to mark minor differences in the hardware setup such as optional patch
+wires used in the design. Design variants can also be marked using these bits. Their definition is
+given in the section dealing with detector specific features. The upper 16 bit are defined in
table~\ref{HardwareInformation}
\begin{table}[htbp]
8800 & Other TRB \\
\hline
\end{tabularx}
-\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value
-can be set by a generic value (\genericname{Regio\_Hardware\_Version}) of the TrbNet endpoint. The
+\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value
+can be set by a generic value (\genericname{Regio\_Hardware\_Version}) of the TrbNet endpoint. The
lower 16bit are not globally defined.}
\label{HardwareInformation}
\end{center}
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