docu for generic flash ctrl, IF

diff --git a/trb3/AdditionalModules.tex b/trb3/AdditionalModules.tex
index d35cf43b7bf0b7e621ccbc17e7495d67676eebee..62cac39b1fbf3f06a27bba1d7fa5900618298766 100644 (file)
--- a/trb3/AdditionalModules.tex
+++ b/trb3/AdditionalModules.tex
@@ -8,4 +8,92 @@
     \item[UART] A generic UART master implemented in FPGA  (resources: 300 slices in FPGA)
     \item[LCD] Any numeric values can be shown on a graphic LCD  (resources: 800 slices in FPGA)
     \item[Debug] For debugging, a UART can be used to access the internal data bus  (resources: 300 slices in FPGA)
-  \end{description}
\ No newline at end of file
+  \end{description}
+
+
+\subsection{Flash programming}
+
+Flash programming of the MACHX03 FPGAs (like the DiRich threshold FPGAs or the Logicbox) is done via a generic
+flash controller which sits in the middle between the serial interface (SPI or UART) and
+the local logic (where the local registers are placed). Both, SPI and UART, have 16-bit adresses and a 16/32-bit
+data bus. The flash controller uses the adresses 0x40 - 0x5F and shades the local user logic for this address space.
+
+The way flash programming is done in the same way as described in the Padiwa documentation, in order to stay consistent.
+
+
+
+
+\begin{longtable}
+{ p{3cm} l c c p{6cm} }
+\toprule
+  \textbf{Register} & \textbf{Addr} & \textbf{Bits} & \textbf{Content} & \textbf{Description} \\
+\midrule
+\midrule
+\endfirsthead\multicolumn{4}{c}{\tablename\ \thetable\ -- \textit{Continued from previous page}} \\\toprule
+  \textbf{Register} & \textbf{Addr} & \textbf{Bits} & \textbf{Content} & \textbf{Description} \\
+\midrule
+\midrule
+\endhead\multicolumn{4}{r}{\textit{Continued on next page}} \\
+  \endfoot 
+  \endlastfoot  \textbf{FlashRAM}\hfill(rw) & 0x4X &   &  & Mapped flash page (16 bytes in total)\\
+
+\rowcolor{light-gray}
+   \textbf{FlashAccess}\hfill(w) & 0x50 &   &  & \\
+\rowcolor{light-gray}
+   \quad  Flash command\hfill &  & 15-13  &  & \\
+\rowcolor{light-gray} 
+    &  & & 0x0 & Read a page from flash and store it in RAM\\
+\rowcolor{light-gray}
+    &  & & 0x4 & Write a page from RAM to flash\\
+\rowcolor{light-gray}
+    &  & & 0x8 & Enable flash (no address required) \\
+\rowcolor{light-gray}
+    &  & & 0xA & Disable flash (no address required) \\
+\rowcolor{light-gray}
+    &  & & 0xE & Erase user of config flash, depending on address \\
+\rowcolor{light-gray}
+   \quad  Flash address\hfill &  & 12-0  &  & \\
+
+
+\textbf{FlashCtrl}  & 0x5C &   &  & \\
+\quad  EnableCfg \hfill{rw} &  & 0  &  & Enable config flash \\
+\quad  FlashErr \hfill{r} &  & 1  &  & Flash error \\
+\quad  FlashBusy \hfill{r} &  & 2  &  & Flash busy (e.g. after erase) \\
+\quad  MasterStart \hfill{w} &  & 3  &  & Starts the flash master by hand, which unpacks the user flash and writes the local registers \\
+\quad  MasterRun  \hfill{r} &  & 4 &  & is =1 while the master is running \\
+
+\rowcolor{light-gray}
+\textbf{FlashPageBurst}  & 0x5D &   &  & Can be used to perform multiple reads on the flash page (0x4X) \\
+\rowcolor{light-gray}
+   \quad  MemWidth \hfill{w} &  & 1-0  &  & Can be used to pack multiple flash bytes into one data word on SPI/UART (requires sufficient buswidth)\\
+\rowcolor{light-gray}
+    &  & & 00 & 8 bit\\
+\rowcolor{light-gray}
+    &  & & 01 & 16 bit\\
+\rowcolor{light-gray}
+    &  & & 10 & 32 bit\\
+\rowcolor{light-gray}
+   \quad  Endian \hfill{w} &  & 4  &  & \quad \\
+\rowcolor{light-gray}
+    &  & & 0 & Little endian\\
+\rowcolor{light-gray}
+    &  & & 1 & Big endian\\
+\rowcolor{light-gray}
+   \quad  NumWords \hfill{w} &  & 11-8  &  & Number of data words (values 1 \dots 3), determines how many data words written to SPI/UART with one single read command. 0: burst disabled.\\
+
+\textbf{Debug}  & 0x5D-0x5F &   &  & Reserved for debugging\\
+\bottomrule
+\caption{Status and Control registers of the flash controller}\label{tab:AdditionalModulesFlash}\end{longtable}
+
+
+
+The flash controller adds in addition a master function which reads the user flash space, and writes the local registers
+after power up (or upon request). This allows to store default values for local registers (like thresholds) in a common way. The
+data which is unpacked starts at the first user page (usually 0x0C00), and contains a version byte, an address byte, and 2-4 data bytes
+(depending on the data width). The data width is selected with the version byte (0x1: 16 bit, 0x2: 32 bit), and any other version byte
+means ``end of file''. In 32 bit mode, 2 more padding bytes are added in order to align the data content with the flash page. This means in
+16 bit mode 4 data words can be stored, and in 32 bit mode 2 data words. The data words are always stored in big-endian.
+
+
+
+