--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_components.all;
+ use work.trb_net_std.all;
+ use work.trb3_components.all;
+ use work.config.all;
+
+entity clock_reset_handler is
+ port (
+ CLOCK_IN : in std_logic; -- oscillator
+ GLOBAL_RESET_IN : in std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ RESET_OUT : out std_logic;
+ CLEAR_OUT : out std_logic;
+ GSR_OUT : out std_logic;
+
+ RAW_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric
+ SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric
+ REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture clock_reset_handler_arch of clock_reset_handler is
+
+attribute syn_keep : boolean;
+attribute syn_preserve : boolean;
+
+signal clock_100 : std_logic;
+signal clock_120 : std_logic;
+signal clock_200 : std_logic;
+signal clock_240 : std_logic;
+signal clock_200_raw : std_logic;
+signal sys_clk_i : std_logic;
+signal timer : unsigned(24 downto 0) := (others => '0');
+signal clear_n_i : std_logic := '0';
+signal reset_i : std_logic;
+signal reset_rising : std_logic;
+signal last_reset_i : std_logic;
+signal debug_reset_handler : std_logic_vector(15 downto 0);
+signal pll_lock : std_logic;
+
+attribute syn_keep of clear_n_i : signal is true;
+attribute syn_preserve of clear_n_i : signal is true;
+
+begin
+
+SYS_CLK_OUT <= sys_clk_i;
+GSR_OUT <= not pll_lock or clear_n_i;
+
+THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input!
+ port map(
+ CLKI => CLOCK_IN,
+ CLKOP => clock_200_raw,
+ CLKOS => clock_100,
+ CLKOS2 => clock_200, --clock_240,
+ CLKOS3 => clock_120,
+ LOCK => pll_lock
+ );
+
+gen_slow_clock : if USE_120_MHZ = 0 generate
+ RAW_CLK_OUT <= clock_200_raw;
+ sys_clk_i <= clock_100;
+ REF_CLK_OUT <= clock_200_raw;
+end generate;
+gen_fast_clock : if USE_120_MHZ = 1 generate
+ RAW_CLK_OUT <= clock_240;
+ sys_clk_i <= clock_120;
+ REF_CLK_OUT <= clock_240;
+end generate;
+
+clear_n_i <= timer(22) when rising_edge(clock_200_raw);
+
+process begin
+ wait until rising_edge(sys_clk_i);
+
+ if timer(22) = '1' then
+ timer <= timer;
+ elsif reset_rising = '1' then
+ timer <= (others => '0');
+ elsif pll_lock = '1' then
+ timer <= timer + 1;
+ end if;
+end process;
+
+
+---------------------------------------------------------------------------
+-- Reset generation
+---------------------------------------------------------------------------
+THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => GLOBAL_RESET_IN, -- reset input (high active, async)
+ CLEAR_N_IN => clear_n_i, -- reset input (low active, async)
+ CLK_IN => clock_200_raw, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => '0', -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => debug_reset_handler
+ );
+
+RESET_OUT <= reset_i;
+
+last_reset_i <= reset_i when rising_edge(clock_200_raw);
+reset_rising <= reset_i and not last_reset_i;
+
+---------------------------------------------------------------------------
+-- Slow clock for DCDC converters
+---------------------------------------------------------------------------
+DEBUG_OUT(0) <= pll_lock;
+DEBUG_OUT(1) <= clear_n_i;
+DEBUG_OUT(15 downto 2) <= debug_reset_handler(15 downto 2);
+DEBUG_OUT(31 downto 16) <= (others => '0');
+
+BUS_TX.data <= (others => '0');
+BUS_TX.unknown <= '1';
+BUS_TX.ack <= '0';
+BUS_TX.nack <= '0';
+
+end architecture;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
- signal testctr : unsigned(31 downto 0);
-
signal link_clock : std_logic;
signal init_quad : std_logic;
signal master_clk_i : std_logic;
signal tx_pcs_rst_i : std_logic;
signal link_tx_ready_i : std_logic;
+ signal rx_dlm_word : std_logic_vector(7 downto 0);
+ signal rx_dlm : std_logic;
+
+ signal global_reset_i : std_logic;
+
+ signal debug_i : std_logic_vector(31 downto 0);
+
signal led_i : std_logic_vector(3 downto 0);
+ signal additional_reg : std_logic_vector(31 downto 0);
+
+ signal flash_ncs_i : std_logic;
+ signal flash_sclk_i : std_logic;
+ signal flash_miso_i : std_logic;
+ signal flash_mosi_i : std_logic;
+
+ signal ep_debug : std_logic_vector(15 downto 0);
+
begin
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
- CLOCK_IN => CLK_200,
- RESET_FROM_NET => med2int(0).stat_op(13),
- SEND_RESET_IN => med2int(0).stat_op(15),
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
- RESET_OUT => reset_i,
- CLEAR_OUT => clear_i,
- GSR_OUT => GSR_N,
- REF_CLK_OUT => clk_full,
- SYS_CLK_OUT => clk_sys,
- RAW_CLK_OUT => clk_full_osc,
- DEBUG_OUT => debug_clock_reset
+ CLOCK_IN => CLK_200,
+ GLOBAL_RESET_IN => global_reset_i,
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+ REF_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ RAW_CLK_OUT => clk_full_osc,
+ DEBUG_OUT => debug_clock_reset
);
init_quad <= not GSR_N;
MEDIA_MED2INT => med2int(0),
MEDIA_INT2MED => int2med(0),
-- komma operation
- RX_DLM_OUT => open,
- RX_DLM_WORD_OUT => open,
- TX_DLM_IN => '0',
- TX_DLM_WORD_IN => x"00",
+ RX_DLM_OUT => rx_dlm,
+ RX_DLM_WORD_OUT => rx_dlm_word,
+ TX_DLM_IN => rx_dlm, --'0',
+ TX_DLM_WORD_IN => rx_dlm_word, --x"00",
RX_RST_OUT => open,
RX_RST_WORD_OUT => open,
TX_RST_IN => '0',
WORD_SYNC_OUT => word_sync_i,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => master_clk_i,
- LINK_TX_NULL_IN => '0',
- LINK_RX_NULL_OUT => open,
+ LINK_TX_NULL_IN => global_reset_i, --'0',
+ LINK_RX_NULL_OUT => global_reset_i, --open,
TX_PLL_LOL_OUT => tx_pll_lol_dual_a,
TX_CLK_AVAIL_OUT => tx_clk_avail_i,
TX_PCS_RST_IN => tx_pcs_rst_i,
-- Status and control port
STAT_DEBUG => med_stat_debug(63 downto 0),
CTRL_DEBUG => open,
- DEBUG_OUT => open
+ DEBUG_OUT => debug_i --open
);
THE_MAIN_TX_RST: main_tx_reset_RS
LINK_TX_READY_OUT => link_tx_ready_i,
STATE_OUT => open
);
-
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-THE_TESTCTR_PROC: process( clk_sys )
-begin
- if( rising_edge(clk_sys) ) then
- testctr <= testctr + 1;
- end if;
-end process THE_TESTCTR_PROC;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger"
-- at least 100ns!
-INTCOM(9 downto 1) <= (others => '0'); --std_logic_vector(testctr(8 downto 0));
+INTCOM(9 downto 1) <= (others => '0');
-TIMING_TEST <= '0'; --std_logic(testctr(31));
+TIMING_TEST <= rx_dlm;
-------------------------------------------------------------------------------
-- Endpoint
I2C_SCL => I2C_SCL, --open,
I2C_SDA => I2C_SDA, --open,
--Timing registers
- TIMERS_OUT => timer
+ TIMERS_OUT => timer,
+ DEBUG_LVL1_HANDLER_OUT => ep_debug
);
-------------------------------------------------------------------------------
CLK => clk_sys,
RESET => reset_i,
--Flash & Reload
- FLASH_CS => FLASH_NCS,
- FLASH_CLK => FLASH_SCLK,
- FLASH_IN => FLASH_MISO,
- FLASH_OUT => FLASH_MOSI,
+ FLASH_CS => flash_ncs_i,
+ FLASH_CLK => flash_sclk_i,
+ FLASH_IN => flash_miso_i,
+ FLASH_OUT => flash_mosi_i,
PROGRAMN => PROGRAMN,
REBOOT_IN => common_ctrl_reg(15),
-- I2C
SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
-- Additional register
- ADDITIONAL_REG(31) => led_off,
- ADDITIONAL_REG(0) => led_i(0),
- ADDITIONAL_REG(1) => led_i(1),
- ADDITIONAL_REG(2) => led_i(2),
- ADDITIONAL_REG(3) => led_i(3),
+ ADDITIONAL_REG => additional_reg,
--Slowcontrol
BUS_RX => bustools_rx,
BUS_TX => bustools_tx,
DEBUG_OUT => debug_tools
);
+ led_off <= additional_reg(0);
+
+ -- FlashROM external connections
+ FLASH_OVERRIDE <= not additional_reg(1);
FLASH_HOLD <= '1';
FLASH_WP <= '1';
- FLASH_OVERRIDE <= '1'; -- do nothing
+ FLASH_NCS <= flash_ncs_i;
+ FLASH_SCLK <= flash_sclk_i;
+ FLASH_MOSI <= flash_mosi_i;
+ flash_miso_i <= FLASH_MISO;
+
+ -- Jan's proposal
+ -- led_off <= additional_reg(0);
+ -- FLASH_OVERRIDE <= not additional_reg(1);
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
- GPIO <= (others => '0'); --std_logic_vector(testctr(15 downto 0));
-
+-- GPIO <= (others => '0');
+ GPIO(15) <= ep_debug(3); --'0'; -- reg.nack
+ GPIO(14) <= ctrlbus_tx.nack; --'0';
+ GPIO(13) <= ctrlbus_tx.ack; --'0';
+ GPIO(12) <= ctrlbus_rx.write; --'0';
+ GPIO(11) <= ctrlbus_rx.read; --'0';
+ GPIO(10) <= bustools_rx.addr(0); --'0';
+ GPIO(9) <= bustools_tx.ack; --'0';
+ GPIO(8) <= bustools_rx.write; --'0';
+ GPIO(7) <= bustools_rx.read; --'0';
+ GPIO(6) <= debug_tools(8); --'0'; -- spi.busy
+ GPIO(5) <= debug_tools(6); --'0'; -- mem.ack
+ GPIO(4) <= debug_tools(5); --'0'; -- mem.write
+ GPIO(3) <= debug_tools(4); --'0'; -- mem.read
+ GPIO(2) <= ep_debug(2); --'0'; -- reg.ack
+ GPIO(1) <= ep_debug(1); --'0'; -- reg.write
+ GPIO(0) <= ep_debug(0); --'0'; -- reg.read
+
-------------------------------------------------------------------------------
-- LED
-------------------------------------------------------------------------------
LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off;
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
- LED(3) <= not led_i(3) or led_off; --std_logic(testctr(27));
- LED(2) <= not led_i(2) or led_off; --std_logic(testctr(26));
- LED(1) <= not led_i(1) or led_off; --std_logic(testctr(25));
- LED(0) <= not led_i(0) or led_off; --std_logic(testctr(24));
-
+ LED(3) <= not rx_dlm_word(7); --led_i(3) or led_off;
+ LED(2) <= not debug_i(2) or led_off; --led_i(2) or led_off;
+ LED(1) <= not debug_i(1) or led_off; --led_i(1) or led_off;
+ LED(0) <= not debug_i(0) or led_off; --led_i(0) or led_off;
+
+ -- 0 red
+ -- 1 orange
+ -- 2 green
+ -- 3 green
-------------------------------------------------------------------------------
-- No trigger/data endpoint included
-------------------------------------------------------------------------------
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