signal trg_win_end_rdo : std_logic;
-- from channel
- signal ch_data : std_logic_vector(35 downto 0);
- signal ch_data_valid : std_logic;
+ signal ch_data : std_logic_vector(35 downto 0);
+ signal ch_data_valid : std_logic;
-- from buffer
- signal buf_data : std_logic_vector(35 downto 0);
- signal buf_data_valid : std_logic;
- signal buf_empty : std_logic;
- signal buf_empty_reg : std_logic;
- signal buf_full : std_logic;
+ signal buf_data : std_logic_vector(35 downto 0);
+ signal buf_data_valid : std_logic;
+ signal buf_empty : std_logic;
+ signal buf_empty_reg : std_logic;
+ signal buf_full : std_logic;
-- fron readout
signal rd_en_reg : std_logic;
-------------------------------------------------------------------------------
- attribute syn_keep : boolean;
- attribute syn_keep of trg_win_end_rdo : signal is true;
- attribute syn_preserve : boolean;
- attribute nomerge : string;
- attribute nomerge of trg_win_end_rdo : signal is "true";
+ attribute syn_keep : boolean;
+ attribute syn_keep of trg_win_end_rdo : signal is true;
+ attribute syn_preserve : boolean;
+ attribute nomerge : string;
+ attribute nomerge of trg_win_end_rdo : signal is "true";
-------------------------------------------------------------------------------
-- DEBUG Counters
-------------------------------------------------------------------------------
HIT_DETECT_NUMBER <= (others => '0'); -- Moved to TDC.vhd
-
+
gen_DEBUG : if DEBUG = c_YES generate
--purpose: Counts the detected but unwritten hits
Lost_Hit_Counter : process (CLK_100)
-- File : Channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-08-28
--- Last update: 2015-10-16
+-- Last update: 2015-12-10
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
signal encoder_data_out : std_logic_vector(9 downto 0);
signal encoder_debug : std_logic_vector(31 downto 0);
signal thermocode : std_logic_vector(287 downto 0);
-
+
-- epoch counter
signal epoch_cntr : std_logic_vector(27 downto 0) := (others => '0');
signal epoch_cntr_r : std_logic_vector(27 downto 0) := (others => '0');
begin -- Channel_200
- GEN_TrgWinEndTdcDist: if SIMULATION = 0 generate
+ GEN_TrgWinEndTdcDist : if SIMULATION = 0 generate
TrgWinEndTdcDist : FD1P3IX
port map (D => '1',
SP => TRG_WIN_END_TDC_IN, --CLKen
CK => CLK_200,
- CD => trg_win_end_tdc, --reset
+ CD => trg_win_end_tdc, --reset
Q => trg_win_end_tdc);
end generate GEN_TrgWinEndTdcDist;
- GEN_TrgWinEndTdcDist_Sim: if SIMULATION = 1 generate
+ GEN_TrgWinEndTdcDist_Sim : if SIMULATION = 1 generate
trg_win_end_tdc <= TRG_WIN_END_TDC_IN when rising_edge(CLK_200);
end generate GEN_TrgWinEndTdcDist_Sim;
-
+
--TrgWinEndTdcDist: process (CLK_200) is
--begin
-- if rising_edge(CLK_200) then -- rising clock edge
thermocode <= result(287 downto 0) when rising_edge(CLK_200);
encoder_start <= hit_detect when rising_edge(CLK_200);
-------------------------------------------------------------------------------
-
+
isReferenceEdge : if REFERENCE = c_YES or DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 2 generate
edge_type <= '1';
end generate isReferenceEdge;
if RESET_100 = '1' then
FSM_RD_STATE <= IDLE;
else
-
+
case FSM_RD_STATE is
when IDLE =>
-- if the data readout is triggered by the end of the trigger window
--end process CheckEpochCounter;
end generate gen_SIMULATION;
-
+
end Channel_200;
-- File : Readout_record.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2015-12-08
+-- Last update: 2015-12-10
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
entity Readout_record is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
- STATUS_REG_NR : integer range 0 to 31);
+ STATUS_REG_NR : integer range 0 to 31);
port (
RESET_100 : in std_logic;
RESET_200 : in std_logic;
-- miscellaneous
LIGHT_MODE_IN : in std_logic;
DEBUG_MODE_EN_IN : in std_logic;
+ INFO_IN : in TIMERS;
STATISTICS_OUT : out std_logic_vector_array_24(0 to 15);
READOUT_DEBUG : out std_logic_vector(31 downto 0)
);
-- readout fsm
type FSM_READ is (IDLE, WAIT_FOR_TRG_WIND_END, RD_CH, WAIT_FOR_DATA_FINISHED, WAIT_FOR_LVL1_TRG_A,
WAIT_FOR_LVL1_TRG_B, WAIT_FOR_LVL1_TRG_C, SEND_STATUS, SEND_TRG_RELEASE_A,
- SEND_TRG_RELEASE_B, SEND_TRG_RELEASE_C, WAIT_FOR_BUFFER_TRANSFER);
+ SEND_TRG_RELEASE_B, SEND_TRG_RELEASE_C, SEND_TRG_RELEASE_D, WAIT_FOR_BUFFER_TRANSFER);
signal RD_CURRENT : FSM_READ := IDLE;
signal RD_NEXT : FSM_READ;
type FSM_WRITE is (IDLE, WR_CH, WAIT_A, WAIT_B, WAIT_C, WAIT_D);
signal wr_status_fsm : std_logic;
signal missing_ref_time_fsm : std_logic;
signal missing_ref_time : std_logic;
- signal wrong_readout_fsm : std_logic;
- signal wrong_readout : std_logic;
signal invalid_trg_fsm : std_logic;
signal invalid_trg : std_logic;
+ signal unknown_trg_fsm : std_logic;
+ signal unknown_trg : std_logic;
signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0;
signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0;
signal buf_delay_fsm : integer range 0 to 63 := 0;
signal wr_fsm_debug_r : std_logic_vector(3 downto 0);
signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0');
signal any_hit : std_logic := '0';
-
+
begin -- behavioral
trg_win_pre <= unsigned(TRG_WIN_PRE_IN);
if RESET_100 = '1' then
RD_CURRENT <= IDLE;
missing_ref_time <= '0';
- wrong_readout <= '0';
invalid_trg <= '0';
+ unknown_trg <= '0';
fifo_nr_rd <= 0;
else
RD_CURRENT <= RD_NEXT;
trg_release <= trg_release_fsm;
missing_ref_time <= missing_ref_time_fsm;
buf_delay <= buf_delay_fsm;
- wrong_readout <= wrong_readout_fsm;
invalid_trg <= invalid_trg_fsm;
+ unknown_trg <= unknown_trg_fsm;
idle_time_up <= idle_fsm;
readout_time_up <= readout_fsm;
wait_time_up <= wait_fsm;
end process RD_FSM_CLK;
READ_EN_OUT <= rd_en;
- RD_FSM_PROC : process (RD_CURRENT, READOUT_RX, stop_status,
- DEBUG_MODE_EN_IN, fifo_nr_rd, TRG_WIN_END_RDO_IN, buf_delay, CH_EMPTY_IN,
- buffer_transfer_done_2r, MISSING_REF_TIME_IN, wrong_readout, isNoHit_r)
+ RD_FSM_PROC : process (RD_CURRENT, READOUT_RX, stop_status, DEBUG_MODE_EN_IN, fifo_nr_rd,
+ TRG_WIN_END_RDO_IN, buf_delay, CH_EMPTY_IN, buffer_transfer_done_2r,
+ MISSING_REF_TIME_IN, isNoHit_r, missing_ref_time, invalid_trg, unknown_trg)
+
begin
RD_NEXT <= RD_CURRENT;
data_finished_fsm <= '0';
trg_release_fsm <= '0';
missing_ref_time_fsm <= missing_ref_time;
- wrong_readout_fsm <= wrong_readout;
invalid_trg_fsm <= invalid_trg;
+ unknown_trg_fsm <= unknown_trg;
idle_fsm <= '0';
readout_fsm <= '0';
wait_fsm <= '0';
case (RD_CURRENT) is
when IDLE =>
if READOUT_RX.valid_timing_trg = '1' then -- physical trigger
- if READOUT_RX.trg_type = x"1" then -- status trigger
- RD_NEXT <= WAIT_FOR_TRG_WIND_END;
- else -- the other triggers
- RD_NEXT <= SEND_TRG_RELEASE_A;
- data_finished_fsm <= '1';
- end if;
- readout_fsm <= '1';
+ RD_NEXT <= WAIT_FOR_TRG_WIND_END;
elsif READOUT_RX.valid_notiming_trg = '1' then
if READOUT_RX.trg_type = x"E" then -- status trigger
wr_header_fsm <= '1';
RD_NEXT <= SEND_STATUS;
elsif READOUT_RX.trg_type = x"D" then -- tdc calibration trigger
- RD_NEXT <= WAIT_FOR_TRG_WIND_END;
- --wr_header_fsm <= '1';
- readout_fsm <= '1';
+ RD_NEXT <= WAIT_FOR_TRG_WIND_END;
else -- the other triggers
- RD_NEXT <= SEND_TRG_RELEASE_A;
- data_finished_fsm <= '1';
+ RD_NEXT <= SEND_TRG_RELEASE_A;
end if;
elsif READOUT_RX.invalid_trg = '1' then -- invalid trigger
RD_NEXT <= SEND_TRG_RELEASE_A;
end if;
idle_fsm <= '1';
rd_fsm_debug_fsm <= x"1";
-
+
when WAIT_FOR_TRG_WIND_END =>
if TRG_WIN_END_RDO_IN = '1' then
RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER;
else
buf_delay_fsm <= buf_delay+ 1;
end if;
+ wait_fsm <= '1';
rd_fsm_debug_fsm <= x"3";
when RD_CH =>
rd_fsm_debug_fsm <= x"4";
when WAIT_FOR_LVL1_TRG_A => -- wait for trigger data valid
- if READOUT_RX.data_valid = '1' then
- RD_NEXT <= WAIT_FOR_LVL1_TRG_B;
- elsif READOUT_RX.trg_timeout = '1' then
- RD_NEXT <= SEND_TRG_RELEASE_A;
+ if READOUT_RX.data_valid = '1' or READOUT_RX.trg_timeout = '1' then
+ if READOUT_RX.trg_type /= x"1" and READOUT_RX.trg_type /= x"D" then
+ unknown_trg_fsm <= '1';
+ end if;
+ RD_NEXT <= SEND_TRG_RELEASE_A;
end if;
wait_fsm <= '1';
rd_fsm_debug_fsm <= x"6";
- when WAIT_FOR_LVL1_TRG_B =>
- RD_NEXT <= WAIT_FOR_LVL1_TRG_C;
- wait_fsm <= '1';
- rd_fsm_debug_fsm <= x"7";
+ --when WAIT_FOR_LVL1_TRG_B =>
+ -- RD_NEXT <= WAIT_FOR_LVL1_TRG_C;
+ -- wait_fsm <= '1';
+ -- rd_fsm_debug_fsm <= x"7";
- when WAIT_FOR_LVL1_TRG_C =>
- if READOUT_RX.trg_spurious = '1' then
- wrong_readout_fsm <= '1';
- end if;
- RD_NEXT <= SEND_TRG_RELEASE_A;
- wait_fsm <= '1';
- rd_fsm_debug_fsm <= x"8";
+ --when WAIT_FOR_LVL1_TRG_C =>
+ -- if READOUT_RX.trg_spurious = '1' then
+ -- wrong_readout_fsm <= '1';
+ -- end if;
+ -- RD_NEXT <= SEND_TRG_RELEASE_A;
+ -- wait_fsm <= '1';
+ -- rd_fsm_debug_fsm <= x"8";
when SEND_STATUS =>
if stop_status = '1' then
if DEBUG_MODE_EN_IN = '1' then
RD_NEXT <= WAIT_FOR_LVL1_TRG_A;
else
- RD_NEXT <= SEND_TRG_RELEASE_A;
+ RD_NEXT <= SEND_TRG_RELEASE_A;
end if;
else
wr_status_fsm <= '1';
rd_fsm_debug_fsm <= x"A";
when SEND_TRG_RELEASE_B =>
- RD_NEXT <= SEND_TRG_RELEASE_C;
+ RD_NEXT <= SEND_TRG_RELEASE_C;
+ readout_fsm <= '1';
+ rd_fsm_debug_fsm <= x"A";
+
+ when SEND_TRG_RELEASE_C =>
+ RD_NEXT <= SEND_TRG_RELEASE_D;
data_finished_fsm <= '1';
readout_fsm <= '1';
rd_fsm_debug_fsm <= x"B";
- when SEND_TRG_RELEASE_C =>
+ when SEND_TRG_RELEASE_D =>
RD_NEXT <= IDLE;
trg_release_fsm <= '1';
missing_ref_time_fsm <= '0';
- wrong_readout_fsm <= '0';
invalid_trg_fsm <= '0';
+ unknown_trg_fsm <= '0';
readout_fsm <= '1';
rd_fsm_debug_fsm <= x"C";
when 10 => data_out_r <= "010" & "01010" & std_logic_vector(wait_time);
when 11 => data_out_r <= "010" & "01011" & std_logic_vector(total_empty_channel);
when 12 => data_out_r <= "010" & "01100" & std_logic_vector(readout_time);
- stop_status <= '1';
when 13 => data_out_r <= "010" & "01101" & std_logic_vector(timeout_number);
+ stop_status <= '1';
+ when 14 => data_out_r <= "010" & "01110" & x"000" & INFO_IN.temperature;
i := -1;
when others => null;
end case;
READOUT_TX.data_finished <= data_finished when rising_edge(CLK_100);
READOUT_TX.busy_release <= trg_release when rising_edge(CLK_100);
READOUT_TX.statusbits <= trg_statusbit when rising_edge(CLK_100);
- trg_statusbit(23) <= wrong_readout when rising_edge(CLK_100);
+ trg_statusbit(23) <= READOUT_RX.trg_spurious when rising_edge(CLK_100);
READOUT_DEBUG(3 downto 0) <= rd_fsm_debug;
READOUT_DEBUG(7 downto 4) <= wr_fsm_debug;
READOUT_DEBUG(10) <= trg_release;
READOUT_DEBUG(16 downto 11) <= data_out_r(27 downto 22);
READOUT_DEBUG(31 downto 17) <= (others => '0');
-
+
-- Error, warning bits set in the header
header_error_bits(0) <= or_all(CH_ALMOST_FULL_IN);
-- Error, warning bits set in the trailer
trailer_error_bits(0) <= missing_ref_time; -- info from the triggerhandler
- trailer_error_bits(1) <= wrong_readout; -- if there is a wrong readout because of a spurious timing trigger
+ trailer_error_bits(1) <= READOUT_RX.trg_spurious; -- if there is a wrong readout because of a spurious timing trigger
trailer_error_bits(2) <= invalid_trg; -- if there is an invalid trigger
trailer_error_bits(3) <= READOUT_RX.trg_missing; -- if the trigger handler detects no reference time signal
trailer_error_bits(4) <= READOUT_RX.trg_multiple; -- if there is multiple triggers
trailer_error_bits(5) <= READOUT_RX.trg_spike; -- if there is spikes
trailer_error_bits(6) <= READOUT_RX.trg_timeout; -- if there is a timeout signal from the endpoint
- trailer_error_bits(15 downto 7) <= (others => '0');
+ trailer_error_bits(7) <= unknown_trg; -- if there is an unknown timing trigger
+ trailer_error_bits(15 downto 8) <= (others => '0');
- TrailerTriggerInfo: process (CLK_100) is
+ TrailerTriggerInfo : process (CLK_100) is
begin
- if rising_edge(CLK_100) then -- rising clock edge
+ if rising_edge(CLK_100) then -- rising clock edge
if READOUT_RX.data_valid = '1' or READOUT_RX.trg_timeout = '1' then
trailer_trg_type <= READOUT_RX.trg_type;
trailer_trg_code <= READOUT_RX.trg_code;
wrongReadoutUp : entity work.risingEdgeDetect
port map (
CLK => CLK_100,
- SIGNAL_IN => wrong_readout,
+ SIGNAL_IN => READOUT_RX.trg_spurious,
PULSE_OUT => wrong_readout_up);
-- Number of wrong readout becasue of spurious trigger
Statistics_Wrong_Readout_Number : process (CLK_100)
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX;
--Debug
+ INFO_IN : in TIMERS;
LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0)
);
end TDC_record;
signal busreadout_rx : READOUT_RX;
signal busreadout_tx : READOUT_TX;
-
- attribute syn_keep : boolean;
- attribute syn_keep of reset_tdc : signal is true;
- attribute syn_keep of coarse_cntr : signal is true;
- attribute syn_keep of hit_in_i : signal is true;
- attribute syn_preserve : boolean;
- attribute syn_preserve of coarse_cntr : signal is true;
- attribute syn_preserve of hit_in_i : signal is true;
- attribute nomerge : string;
- attribute nomerge of hit_in_i : signal is "true";
-
+
+ attribute syn_keep : boolean;
+ attribute syn_keep of reset_tdc : signal is true;
+ attribute syn_keep of coarse_cntr : signal is true;
+ attribute syn_keep of hit_in_i : signal is true;
+ attribute syn_preserve : boolean;
+ attribute syn_preserve of coarse_cntr : signal is true;
+ attribute syn_preserve of hit_in_i : signal is true;
+ attribute nomerge : string;
+ attribute nomerge of hit_in_i : signal is "true";
+
begin
generic map(
PORT_NUMBER => 4,
PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", 3 => x"0800", others => x"0000"),
- PORT_ADDR_MASK => (0 => 7, 1 => 5, 2 => 7, 3 => 3, others => 0),
+ PORT_ADDR_MASK => (0 => 7, 1 => 5, 2 => 7, 3 => 3, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
CLK => CLK_READOUT,
RESET => RESET,
- REGIO_RX => BUS_RX,
- REGIO_TX => BUS_TX,
-
+ REGIO_RX => BUS_RX,
+ REGIO_TX => BUS_TX,
+
BUS_RX(0) => bushit_rx, -- hit counter bus
BUS_RX(1) => busstat_rx, -- status reg bus
BUS_RX(2) => buschdebug_rx, -- channel debug bus
BUS_TX(1) => busstat_tx,
BUS_TX(2) => buschdebug_tx,
BUS_TX(3) => busctrl_tx,
-
+
STAT_DEBUG => open
);
-- Slow Control
-------------------------------------------------------------------------------
- TheSlowcontrolBus: entity work.BusHandler_record
+ TheSlowcontrolBus : entity work.BusHandler_record
generic map (
BUS_LENGTH => 8)
port map (
DATA_IN => ctrl_reg,
DATA_OUT => ctrl_reg);
-
+
-- Slow control signals
logic_anal_control <= ctrl_reg(0)(3 downto 0);
debug_mode_en <= ctrl_reg(0)(4);
edge_falling_d_r(i) <= edge_falling_d(i) when rising_edge(CLK_TDC);
edge_falling_d_2r(i) <= edge_falling_d_r(i) when rising_edge(CLK_TDC);
- edge_falling_d_3r(i) <= edge_falling_d_2r(i) when rising_edge(CLK_TDC); --edge_falling_d_r(i) and not edge_falling_d_2r(i) when rising_edge(CLK_TDC);
+ edge_falling_d_3r(i) <= edge_falling_d_2r(i) when rising_edge(CLK_TDC); --edge_falling_d_r(i) and not edge_falling_d_2r(i) when rising_edge(CLK_TDC);
hit_edge(i) <= '0' when edge_falling_d(i) = '1' or RESET = '1' else
'1' when rising_edge(edge_rising(i));
-- miscellaneous
LIGHT_MODE_IN => light_mode_en,
DEBUG_MODE_EN_IN => debug_mode_en,
+ INFO_IN => INFO_IN,
STATISTICS_OUT => readout_statistics,
READOUT_DEBUG => readout_debug
);
-- Slow Control Data Busses
-------------------------------------------------------------------------------
-- Hit counter
- TheHitCounterBus: entity work.BusHandler_record
+ TheHitCounterBus : entity work.BusHandler_record
generic map (
BUS_LENGTH => CHANNEL_NUMBER-1)
port map (
end generate GenHitDetectNumber;
-- Status register
- TheStatusRegisterBus: entity work.BusHandler_record
+ TheStatusRegisterBus : entity work.BusHandler_record
generic map (
BUS_LENGTH => STATUS_REG_NR-1)
port map (
status_registers_bus(0)(3 downto 0) <= readout_debug(3 downto 0); -- rd_fsm
status_registers_bus(0)(7 downto 4) <= readout_debug(7 downto 4); -- wr_fsm
status_registers_bus(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8));
- status_registers_bus(0)(16) <= REFERENCE_TIME when rising_edge(CLK_READOUT);
+ status_registers_bus(0)(16) <= REFERENCE_TIME when rising_edge(CLK_READOUT);
status_registers_bus(0)(27 downto 17) <= TDC_VERSION(10 downto 0);
status_registers_bus(0)(31 downto 28) <= busreadout_rx.trg_type when rising_edge(CLK_READOUT);
-- Channel debug
- TheChannelDebugBus: entity work.BusHandler_record
+ TheChannelDebugBus : entity work.BusHandler_record
generic map (
BUS_LENGTH => CHANNEL_NUMBER-1)
port map (
buschdebug_data_in(i) <= ch_200_debug(i)(31 downto 2) & edge_rising_2r(i) & ch_200_debug(i)(0);
end generate GEN_BUSCHDEBUG;
-
+
-------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------
--LOGIC_ANALYSER_OUT(14) <= hit_in_i(1);
--LOGIC_ANALYSER_OUT(15) <= hit_in_i(1);
-
+
end TDC_record;
-- File : TriggerHandler.vhd
-- Author : Cahit Ugur c.ugur@gsi.de
-- Created : 2013-03-13
--- Last update: 2015-09-15
+-- Last update: 2015-12-10
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
architecture behavioral of TriggerHandler is
-- Placer Directives
- attribute HGROUP : string;
+ attribute HGROUP : string;
-- for whole architecture
- attribute HGROUP of Behavioral : architecture is "TriggerHandler_group";
+ attribute HGROUP of Behavioral : architecture is "TriggerHandler_group";
-- trigger signals
signal trg_in_r : std_logic_vector(TRIGGER_NUM-1 downto 0);
signal missing_ref_time_rdo : std_logic;
signal trg_time : std_logic_vector(38 downto 0) := (others => '0');
signal trg_win_state_debug_f : std_logic_vector(3 downto 0);
-
+
begin -- architecture behavioral
else
trg_pulse_tdc(i) <= '0';
end if;
-
+
end if;
end process Validation;
end generate GEN_TRIGGER;
if TRG_TYPE_IN = x"D" then
STATE_TW_NEXT <= COUNT_CALIBRATION;
else
- STATE_TW_NEXT <= WIN_END;
+ STATE_TW_NEXT <= WAIT_NEXT_TRIGGER;
end if;
elsif valid_timing_200 = '1' then
STATE_TW_NEXT <= MISSING_REFERENCE_TIME;
end if;
trg_win_cnt_f <= trg_win_cnt + to_unsigned(1, 12);
trg_win_state_debug_f <= x"3";
-
+
when COUNT_CALIBRATION =>
if trg_win_cnt(6) = '1' then
STATE_TW_NEXT <= WIN_END;
end if;
trg_win_cnt_f <= trg_win_cnt + to_unsigned(1, 12);
trg_win_state_debug_f <= x"4";
-
+
when VALIDATE_TRIGGER =>
if valid_trigger_flag = '1' then
STATE_TW_NEXT <= WIN_END;
end if;
trg_win_end_f <= '0';
trg_win_state_debug_f <= x"5";
-
+
when WIN_END =>
STATE_TW_NEXT <= WAIT_NEXT_TRIGGER;
trg_win_end_f <= '1';
trg_win_state_debug_f <= x"6";
-
+
when MISSING_REFERENCE_TIME =>
STATE_TW_NEXT <= WAIT_NEXT_TRIGGER;
trg_win_end_f <= '1';
missing_ref_time_f <= '1';
trg_win_state_debug_f <= x"7";
-
+
when WAIT_NEXT_TRIGGER =>
if trg_release_200 = '1' then
STATE_TW_NEXT <= IDLE;
trg_win_state_debug_f <= x"8";
when others =>
- STATE_TW_NEXT <= IDLE;
+ STATE_TW_NEXT <= IDLE;
trg_win_state_debug_f <= x"0";
end case;
end process FSM_TRIGGER_WINDOW_COMBINATIONAL;
use ieee.numeric_std.all;
library work;
use work.trb_net_std.all;
+use work.config.all;
package tdc_components is
-
+
+ --type CH_RX is record
+ -- data : std_logic_vector_array_36(0 to NUM_TDC_CHANNELS);
+ -- data_valid : std_logic_vector(NUM_TDC_CHANNELS-1 downto 0);
+ -- almost_full : std_logic_vector(NUM_TDC_CHANNELS-1 downto 0);
+ -- empty : std_logic_vector(NUM_TDC_CHANNELS-1 downto 0);
+ --end record;
+
+ --type CH_TX is record
+ -- read_en : std_logic_vector(NUM_TDC_CHANNELS-1 downto 0);
+ --end record;
+
component TDC_record is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
HIT_CAL_IN : in std_logic;
BUSRDO_RX : in READOUT_RX;
BUSRDO_TX : out READOUT_TX;
- LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
BUS_RX : in CTRLBUS_RX;
- BUS_TX : in CTRLBUS_TX);
+ BUS_TX : in CTRLBUS_TX;
+ INFO_IN : in TIMERS;
+ LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0));
end component TDC_record;
-
+
component TDC is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
ENCODER_START_OUT : out std_logic;
ENCODER_FINISHED_OUT : out std_logic;
FIFO_WRITE_OUT : out std_logic;
- CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0));
+ CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0));
end component Channel_200;
component Readout_Header is
MISSING_REF_TIME_IN : in std_logic;
LIGHT_MODE_IN : in std_logic;
DEBUG_MODE_EN_IN : in std_logic;
+ INFO_IN : in TIMERS;
STATISTICS_OUT : out std_logic_vector_array_24(0 to 15);
READOUT_DEBUG : out std_logic_vector(31 downto 0));
end component Readout_record;
-
+
component Readout is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
LIGHT_MODE_IN : in std_logic;
DEBUG_MODE_EN_IN : in std_logic;
STATISTICS_OUT : out std_logic_vector_array_24(0 to 15);
- READOUT_DEBUG : out std_logic_vector(31 downto 0));
+ READOUT_DEBUG : out std_logic_vector(31 downto 0));
end component Readout;
component TriggerHandler is
DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH);
DATA_OUT : out std_logic_vector_array_32(0 to BUS_LENGTH));
end component BusHandler_record;
-
+
component BusHandler
generic (
BUS_LENGTH : integer range 0 to 64 := 2);
component up_counter
generic (
- NUMBER_OF_BITS : positive);
+ NUMBER_OF_BITS : positive);
port (
CLK : in std_logic;
RESET : in std_logic;
COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
+ UP_IN : in std_logic);
end component;
component Adder_304
Q : out std_logic_vector(35 downto 0);
Empty : out std_logic;
Full : out std_logic;
- AlmostFull : out std_logic);
+ AlmostFull : out std_logic);
end component FIFO_DC_36x64_DynThr_OutReg;
component FIFO_DC_36x64_OutReg is
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