signal set_output_coin, set_output_simplecoin : std_logic_vector(7 downto 0);
signal edge_enable : std_logic_vector(7 downto 0) := (others => '0');
-type coincidence_arr is array(0 to 16) of integer range 0 to 63;
+type coincidence_arr is array(0 to 23) of integer range 0 to 63;
signal coincidence_config_1, coincidence_config_2 : coincidence_arr;
-signal coincidence_enable : std_logic_vector(15 downto 0);
+signal coincidence_enable : std_logic_vector(23 downto 0);
begin
when others => null;
end case;
end if;
- elsif BUS_RX.addr(6 downto 4) = "100" then
- coincidence_config_1(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= to_integer(unsigned(BUS_RX.data(13 downto 8)));
- coincidence_config_2(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= to_integer(unsigned(BUS_RX.data(5 downto 0)));
- coincidence_enable(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= BUS_RX.data(31);
+ elsif BUS_RX.addr(6 downto 5) = "10" then
+ coincidence_config_1(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= to_integer(unsigned(BUS_RX.data(13 downto 8)));
+ coincidence_config_2(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= to_integer(unsigned(BUS_RX.data(5 downto 0)));
+ coincidence_enable(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= BUS_RX.data(31);
elsif BUS_RX.addr(6 downto 0) = "0110010" then
set_multiplicity(0) <= unsigned(BUS_RX.data(23 downto 16));
set_multiplicity(1) <= unsigned(BUS_RX.data(15 downto 8));
BUS_TX.ack <= '0';
BUS_TX.unknown <= '1';
end if;
- elsif BUS_RX.addr(6 downto 4) = "100" then
- BUS_TX.data(13 downto 8) <= std_logic_vector(to_unsigned(coincidence_config_1(to_integer(unsigned(BUS_RX.addr(3 downto 0)))),6));
- BUS_TX.data( 5 downto 0) <= std_logic_vector(to_unsigned(coincidence_config_2(to_integer(unsigned(BUS_RX.addr(3 downto 0)))),6));
- BUS_TX.data(31) <= coincidence_enable(to_integer(unsigned(BUS_RX.addr(3 downto 0))));
+ elsif BUS_RX.addr(6 downto 5) = "10" then
+ BUS_TX.data(13 downto 8) <= std_logic_vector(to_unsigned(coincidence_config_1(to_integer(unsigned(BUS_RX.addr(4 downto 0)))),6));
+ BUS_TX.data( 5 downto 0) <= std_logic_vector(to_unsigned(coincidence_config_2(to_integer(unsigned(BUS_RX.addr(4 downto 0)))),6));
+ BUS_TX.data(31) <= coincidence_enable(to_integer(unsigned(BUS_RX.addr(4 downto 0))));
elsif BUS_RX.addr(6 downto 0) = "0110000" then
BUS_TX.data(OUTPUTS-1 downto 0) <= out_reg;
BUS_TX.data(31 downto OUTPUTS) <= (others => '0');
variable t : std_logic;
begin
t := '0';
- for i in 0 to 15 loop
+ for i in 0 to 23 loop
t := t or (coincidence_enable(i) and inp_verylong(coincidence_config_1(i)) and inp_verylong(coincidence_config_2(i)));
end loop;
got_coincidence <= t;