fix names of SPI ports

fix mapping of PWM outputs on DAC FPGAs

diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf
index a7862641adeeb57b5476facdba821f4813be9f18..57bf40a55d7fb2442ca9d89e9ff704fceb1d7afb 100644 (file)
--- a/pinout/dirich.lpf
+++ b/pinout/dirich.lpf
@@ -156,19 +156,19 @@ DEFINE PORT GROUP "TEST_group" "TEST*" ;
 IOBUF GROUP  "TEST_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
 
 
-LOCATE COMP "MISO_IN_1"          SITE "E7";    #DAC1_CTRL0
-LOCATE COMP "MISO_IN_2"          SITE "A17";   #DAC2_CTRL0
-LOCATE COMP "MOSI_OUT_1"         SITE "D7";    #DAC1_CTRL1
-LOCATE COMP "MOSI_OUT_2"         SITE "A18";   #DAC2_CTRL1
-LOCATE COMP "SCLK_OUT_1"         SITE "E6";    #DAC1_CTRL2
-LOCATE COMP "SCLK_OUT_2"         SITE "B19";   #DAC2_CTRL2
-LOCATE COMP "CS_OUT_1"           SITE "D6";    #DAC1_CTRL3
-LOCATE COMP "CS_OUT_2"           SITE "B18";   #DAC2_CTRL3
-IOBUF PORT "MISO_IN_1  " IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "MOSI_OUT_1"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "SCLK_OUT_1"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "CS_OUT_1"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "MISO_IN_2  " IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "MOSI_OUT_2"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "SCLK_OUT_2"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "CS_OUT_2"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+LOCATE COMP "MISO_IN[1]"          SITE "E7";    #DAC1_CTRL0
+LOCATE COMP "MISO_IN[2]"          SITE "A17";   #DAC2_CTRL0
+LOCATE COMP "MOSI_OUT[1]"         SITE "D7";    #DAC1_CTRL1
+LOCATE COMP "MOSI_OUT[2]"         SITE "A18";   #DAC2_CTRL1
+LOCATE COMP "SCLK_OUT[1]"         SITE "E6";    #DAC1_CTRL2
+LOCATE COMP "SCLK_OUT[2]"         SITE "B19";   #DAC2_CTRL2
+LOCATE COMP "CS_OUT[1]"           SITE "D6";    #DAC1_CTRL3
+LOCATE COMP "CS_OUT[2]"           SITE "B18";   #DAC2_CTRL3
+IOBUF PORT "MISO_IN[1]" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "MOSI_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "SCLK_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "CS_OUT[1]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "MISO_IN[2]" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "MOSI_OUT[2]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "SCLK_OUT[2]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "CS_OUT[2]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index 2a00fa1052ff987f4bfafd3e22db2f2bce8f57ab..58499c1f7b39b489e61b9adcd1243776c6190d04 100644 (file)
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -10,8 +10,8 @@ use work.trb_net_std.all;
 \r
 entity thresholds is\r
   port(\r
-    ID     : in  std_logic;\r
-    OUTPUT : out std_logic_vector(15 downto 0);\r
+    DAC_FLAG     : in  std_logic;\r
+    OUTPUT   : out std_logic_vector(15 downto 0);\r
     MISO_OUT : out std_logic;\r
     MOSI_IN  : in  std_logic;\r
     SCLK_IN  : in  std_logic;\r
@@ -190,8 +190,30 @@ THE_PWM_GEN : entity work.pwm_generator
     );    \r
 \r
 --TODO connect to output according to ID\r
-OUTPUT <= pwm_i;\r
-\r
+process(pwm_i,DAC_FLAG)\r
+  begin\r
+    if DAC_FLAG = '1' then\r
+      OUTPUT <= pwm_i;\r
+    else\r
+      OUTPUT(1)  <= pwm_i(15);\r
+      OUTPUT(2)  <= pwm_i(13);\r
+      OUTPUT(3)  <= pwm_i(8);\r
+      OUTPUT(4)  <= pwm_i(5);\r
+      OUTPUT(5)  <= pwm_i(16);\r
+      OUTPUT(6)  <= pwm_i(4);\r
+      OUTPUT(7)  <= pwm_i(3);\r
+      OUTPUT(8)  <= pwm_i(6);\r
+      OUTPUT(9)  <= pwm_i(2);\r
+      OUTPUT(10) <= pwm_i(1);\r
+      OUTPUT(11) <= pwm_i(7);\r
+      OUTPUT(12) <= pwm_i(9);\r
+      OUTPUT(13) <= pwm_i(14);\r
+      OUTPUT(14) <= pwm_i(12);\r
+      OUTPUT(15) <= pwm_i(10);\r
+      OUTPUT(16) <= pwm_i(11);      \r
+    end if;\r
+  end process;  \r
+    \r
     \r
     \r
 ---------------------------------------------------------------------------\r