DDMTD continued

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index d663c5a0b507b9f040cbc903f1adca9c60a45b48..e2c16dafcf487eb7e5cee552d734d29237f6ea3e 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -264,7 +264,7 @@ architecture trb3sc_arch of trb3sc_cts is
   signal init_quad                   : std_logic;
   signal link_clock                  : std_logic;
   
---  signal phaser_data                 : std_logic_vector(31 downto 0);
+  signal phaser_data                 : std_logic_vector(31 downto 0);
   signal ping_i                      : std_logic;
   signal ping_q                      : std_logic;
   signal pong_i                      : std_logic;
@@ -284,9 +284,9 @@ architecture trb3sc_arch of trb3sc_cts is
   signal start_pong_q                : std_logic;
   signal toggle_i                    : std_logic;
   signal toggle_q                    : std_logic;
-  signal beat_i                      : std_logic;
-  signal beat_q                      : std_logic;
   signal tristate_pings_i            : std_logic;
+  signal cal_pulse_i                 : std_logic;
+  signal cal_pulse_q                 : std_logic_vector(1 downto 0);
   
 begin
 
@@ -567,9 +567,21 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     PONG_OUT        => pong_stretched_i,
     START_PING_OUT  => start_ping_i,
     START_PONG_OUT  => start_pong_i,
-    TOGGLE_OUT      => toggle_i,
-    BEAT_OUT        => beat_i
+    DELAY_VALUE_OUT => phaser_data(15 downto 0),
+    DELAY_VALID_OUT => open,
+    TOGGLE_OUT      => toggle_i
   );
+
+  phaser_data(31 downto 16) <= (others => '0');
+  
+  THE_CAL_CLOCK_PROC: process( master_clk_i, reset_i ) 
+  begin
+    if   ( reset_i = '1' ) then
+      cal_pulse_i <= '0';
+    elsif( rising_edge(master_clk_i) ) then
+      cal_pulse_i <= not cal_pulse_i;
+    end if;
+  end process THE_CAL_CLOCK_PROC;
   
   -- Output registers
   THE_PING_OR: OFS1P3DX
@@ -625,14 +637,23 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     D     => start_pong_i,
     Q     => start_pong_q
   );
-  
-  THE_BEAT_OR: OFS1P3DX
+
+  THE_REF_CLK_1_OR: OFS1P3DX
   port map(
     SP    => '1',
     CD    => '0',
-    SCLK  => clk_sample,
-    D     => beat_i,
-    Q     => beat_q
+    SCLK  => master_clk_i,
+    D     => cal_pulse_i,
+    Q     => cal_pulse_q(1)
+  );
+
+  THE_REF_CLK_0_OR: OFS1P3DX
+  port map(
+    SP    => '1',
+    CD    => '0',
+    SCLK  => master_clk_i,
+    D     => cal_pulse_i,
+    Q     => cal_pulse_q(0)
   );
 
   THE_TOGGLE_OR: OFS1P3DX
@@ -648,10 +669,10 @@ HDR_IO(1)  <= ping_q when (tristate_pings_i = '0') else 'Z';
 HDR_IO(3)  <= pong_q when (tristate_pings_i = '0') else 'Z';
 HDR_IO(5)  <= ping_stretched_q;
 HDR_IO(7)  <= pong_stretched_q;
-HDR_IO(9)  <= beat_q;
+HDR_IO(9)  <= '0';
 
-HDR_IO(2)  <= '0'; -- reserved for testing calibration
-HDR_IO(4)  <= '0'; -- reserved for testing calibration
+HDR_IO(2)  <= cal_pulse_q(0) when (tristate_pings_i = '1') else 'Z';
+HDR_IO(4)  <= cal_pulse_q(1) when (tristate_pings_i = '1') else 'Z';
 HDR_IO(6)  <= start_ping_q;
 HDR_IO(8)  <= start_pong_q;
 HDR_IO(10) <= toggle_q;
@@ -663,16 +684,16 @@ end generate;
 ---------------------------------------------------------------------------
 -- PCSC: not used
 ---------------------------------------------------------------------------    
-  bussci3_tx.data    <= (others => '0');
-  bussci3_tx.ack     <= '0';
-  bussci3_tx.nack    <= '0';
-  bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+--  bussci3_tx.data    <= (others => '0');
+--  bussci3_tx.ack     <= '0';
+--  bussci3_tx.nack    <= '0';
+--  bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
 
 -- can be used for simple readback on debugging
-  --bussci3_tx.data    <= phaser_data;
-  --bussci3_tx.ack     <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
-  --bussci3_tx.nack    <= '0';
-  --bussci3_tx.unknown <= '0';
+  bussci3_tx.data    <= phaser_data;
+  bussci3_tx.ack     <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+  bussci3_tx.nack    <= '0';
+  bussci3_tx.unknown <= '0';
 
 ---------------------------------------------------------------------------
 -- PCSD: GbE