###################################################################################
#Settings for this project
my $TOPNAME = "trb3_periph_32PinAddOn"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $lattice_path = '/d/jspc29/lattice/diamond/3.6_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/J-2014.09-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
###################################################################################
system("env| grep LM_");
my $r = "";
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+# my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+my $c="/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options -batch $TOPNAME.prj";
$r=execute($c, "do_not_exit" );
$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
execute($c);
my $tpmap = $TOPNAME . "_map" ;
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
execute($c);
system("rm $TOPNAME.ncd");
#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
execute($c);
# IOR IO Timing Report
# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
# execute($c);
# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
---Include SPI on AddOn connector
- constant INCLUDE_SPI : integer := c_YES;
-
---Add logic to generate configurable trigger signal from input signals.
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
- constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs
- constant PHYSICAL_INPUTS : integer := 32; --number of inputs connected
- constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
---Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 16;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 24;
+ constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics
+
+ --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
constant USE_125_MHZ : integer := c_NO; --not implemented yet!
constant USE_RXCLOCK : integer := c_NO; --not implemented yet!
constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet!
------------------------------------------------------------------------------
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ others => x"00");
+
------------------------------------------------------------------------------
--Select settings by configuration
-../../tdc/releases/tdc_v2.1.5
\ No newline at end of file
+../../tdc/releases/tdc_v2.3/
\ No newline at end of file
add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/trb3_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
add_file -vhdl -lib work "../base/code/input_statistics.vhd"
add_file -vhdl -lib work "../base/code/sedcheck.vhd"
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "tdc_release/Channel.vhd"
add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib work "tdc_release/Readout.vhd"
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
add_file -vhdl -lib work "tdc_release/TDC.vhd"
+add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
add_file -vhdl -lib work "tdc_release/up_counter.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+++ /dev/null
-tdc_release/trb3_periph_32PinAddOn.vhd
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.tdc_components.all;
+use work.config.all;
+use work.tdc_version.all;
+use work.version.all;
+
+
+entity trb3_periph_32PinAddOn is
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --Connection to ADA AddOn
+ SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only
+ INP : in std_logic_vector(63 downto 0);
+ --DAC
+ DAC_IN_SDI : in std_logic;
+ DAC_OUT_SDO : out std_logic;
+ DAC_OUT_SCK : out std_logic;
+ DAC_OUT_CS : out std_logic;
+ DAC_OUT_CLR : out std_logic;
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+ --Test Connectors
+ TEST_LINE : inout std_logic_vector(15 downto 0)
+ );
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ --important signals
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+ attribute syn_useioff of INP : signal is false;
+ attribute syn_useioff of SPARE_LINE : signal is true;
+ attribute syn_useioff of DAC_IN_SDI : signal is true;
+ attribute syn_useioff of DAC_OUT_SDO : signal is true;
+ attribute syn_useioff of DAC_OUT_SCK : signal is true;
+ attribute syn_useioff of DAC_OUT_CS : signal is true;
+ attribute syn_useioff of DAC_OUT_CLR : signal is true;
+
+
+end entity;
+
+
+architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+
+ signal timing_trg_received_i : std_logic;
+
+ --READOUT
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 0);
+
+ --Slow Control channel
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
+ signal bus_master_active : std_logic;
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+ signal lcd_out : std_logic_vector(4 downto 0);
+ signal feature_outputs_i : std_logic_vector(15 downto 0);
+ signal spi_cs, spi_mosi, spi_miso, spi_clk, spi_clr : std_logic_vector(15 downto 0);
+ signal uart_rx, uart_tx, debug_rx, debug_tx : std_logic;
+ signal trig_gen_out_i : std_logic_vector(3 downto 0);
+ signal sed_error_i : std_logic;
+ --TDC
+ signal hit_in_i : std_logic_vector(64 downto 1);
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med2int(0).stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ RESET => '0',
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+ pll_calibration: entity work.pll_in125_out33
+ port map (
+ CLK => CLK_GPLL_LEFT,
+ CLKOP => osc_int,
+ LOCK => open);
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_125_MHZ => c_NO,
+ USE_CTC => c_NO
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => int2med(0).data,
+ MED_PACKET_NUM_IN => int2med(0).packet_num,
+ MED_DATAREADY_IN => int2med(0).dataready,
+ MED_READ_OUT => med2int(0).tx_read,
+ MED_DATA_OUT => med2int(0).data,
+ MED_PACKET_NUM_OUT => med2int(0).packet_num,
+ MED_DATAREADY_OUT => med2int(0).dataready,
+ MED_READ_IN => '1',
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med2int(0).stat_op,
+ CTRL_OP => int2med(0).ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
+ generic map (
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ TIMING_TRIGGER_RAW => c_YES,
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+
+ port map(
+ -- Misc
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
+
+ --Slow Control Port
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+ ONEWIRE_INOUT => TEMPSENS,
+ --Timing registers
+ TIMERS_OUT => timer
+ );
+
+
+ timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustdc_rx, --TDC config
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustdc_tx,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS : entity work.trb3_tools
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_DOUT,
+ FLASH_OUT => FLASH_DIN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ SPI_CLR_OUT => spi_clr,
+ --LCD
+ LCD_DATA_IN => lcd_data,
+ UART_RX_IN => uart_rx,
+ UART_TX_OUT => uart_tx,
+ DEBUG_RX_IN => debug_rx,
+ DEBUG_TX_OUT => debug_tx,
+
+ --Trigger & Monitor
+ MONITOR_INPUTS(19 downto 0) => INP(19 downto 0),
+ MONITOR_INPUTS(23 downto 20) => trig_gen_out_i,
+ TRIG_GEN_INPUTS => INP(15 downto 0),
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ LCD_OUT => lcd_out,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Feature I/O
+---------------------------------------------------------------------------
+ gen_SPI : if INCLUDE_SPI = 1 generate
+ DAC_OUT_CS <= spi_cs(0);
+ DAC_OUT_SDO <= spi_mosi(0);
+ DAC_OUT_SCK <= spi_clk(0);
+ DAC_OUT_CLR <= spi_clr(0);
+ spi_miso(0) <= DAC_IN_SDI;
+ end generate;
+ gen_NO_SPI : if INCLUDE_SPI = 0 generate
+ DAC_OUT_SDO <= trig_gen_out_i(0);
+ DAC_OUT_SCK <= trig_gen_out_i(1);
+ DAC_OUT_CS <= trig_gen_out_i(2);
+ DAC_OUT_CLR <= trig_gen_out_i(3);
+ end generate;
+
+
+ FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
+ FPGA5_COMM(6 downto 3) <= (others => 'Z');
+ FPGA5_COMM(1) <= 'Z';
+
+ feature_outputs_i(0) <= uart_rx;
+ feature_outputs_i(1) <= uart_tx;
+ feature_outputs_i(2) <= spi_cs(1);
+ feature_outputs_i(3) <= spi_mosi(1);
+ feature_outputs_i(4) <= spi_clk(1);
+ spi_miso(1) <= TEST_LINE(5);
+ feature_outputs_i(7) <= lcd_out(4); --lcd_cs
+ feature_outputs_i(8) <= lcd_out(0); --lcd_rst
+ feature_outputs_i(9) <= lcd_out(3); --lcd_dc
+ feature_outputs_i(10) <= lcd_out(2); --lcd_mosi
+ feature_outputs_i(11) <= lcd_out(1); --lcd_sck
+ --12 is LCD MISO, but not used
+ feature_outputs_i(14) <= debug_rx;
+ feature_outputs_i(15) <= debug_tx;
+
+---------------------------------------------------------------------------
+-- LCD Data to display
+---------------------------------------------------------------------------
+ lcd_data(15 downto 0) <= timer.network_address;
+ lcd_data(47 downto 16) <= timer.microsecond;
+ lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32));
+ lcd_data(511 downto 80) <= (others => '0');
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med2int(0).stat_op(9);
+ LED_ORANGE <= not med2int(0).stat_op(10);
+ LED_RED <= '1';
+ LED_YELLOW <= not med2int(0).stat_op(11);
+
+---------------------------------------------------------------------------
+-- Test Connector - Additional Features
+---------------------------------------------------------------------------
+-- TEST_LINE <= feature_outputs_i;
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+ THE_TDC : entity work.TDC_record
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+ STATUS_REG_NR => 21, -- Number of status regs
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => CLK_PCLK_LEFT,
+ CLK_READOUT => clk_100_i, -- Clock for the readout
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC
+ -- Trigger signals from handler
+ BUSRDO_RX => readout_rx,
+ BUSRDO_TX => readout_tx(0),
+ --
+ INFO_IN => timer,
+ LOGIC_ANALYSER_OUT => TEST_LINE,
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx
+ );
+
+ -- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ hit_in_i <= INP;
+ end generate;
+
+ -- For ToT Measurements
+ gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+ Gen_Hit_In_Signals : for i in 1 to 32 generate
+ hit_in_i(i*2-1) <= INP(i-1);
+ hit_in_i(i*2) <= not INP(i-1);
+ end generate Gen_Hit_In_Signals;
+ end generate;
+
+end architecture;
--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_components.all;
+ use work.trb_net_std.all;
+ use work.trb3_components.all;
+ use work.config.all;
+
+entity trb3_tools is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ --Flash & Reload
+ FLASH_CS : out std_logic;
+ FLASH_CLK : out std_logic;
+ FLASH_IN : in std_logic;
+ FLASH_OUT : out std_logic;
+ PROGRAMN : out std_logic;
+ REBOOT_IN : in std_logic;
+
+ --SPI
+ SPI_CS_OUT : out std_logic_vector(15 downto 0);
+ SPI_MOSI_OUT: out std_logic_vector(15 downto 0);
+ SPI_MISO_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ SPI_CLK_OUT : out std_logic_vector(15 downto 0);
+ SPI_CLR_OUT : out std_logic_vector(15 downto 0);
+
+ --LCD
+ LCD_DATA_IN : in std_logic_vector(511 downto 0) := (others => '0');
+
+ --Feature I/O
+ UART_RX_IN : in std_logic := '0';
+ UART_TX_OUT : out std_logic;
+ DEBUG_RX_IN : in std_logic := '0';
+ DEBUG_TX_OUT: out std_logic;
+ LCD_OUT : out std_logic_vector(4 downto 0); -- lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst
+
+ --Trigger & Monitor
+ MONITOR_INPUTS : in std_logic_vector(MONITOR_INPUT_NUM-1 downto 0) := (others => '0');
+ TRIG_GEN_INPUTS : in std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0) := (others => '0');
+ TRIG_GEN_OUTPUTS : out std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);
+ --SED
+ SED_ERROR_OUT : out std_logic;
+
+ --Slowcontrol
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ --Control master for default settings
+ BUS_MASTER_IN : in CTRLBUS_TX := (data => (others => '0'), unknown => '1', others => '0');
+ BUS_MASTER_OUT : out CTRLBUS_RX;
+ BUS_MASTER_ACTIVE : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+
+
+architecture trb3_tools_arch of trb3_tools is
+
+signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, bussed_rx, busuart_rx, busflashset_rx, busmon_rx, bustrig_rx : CTRLBUS_RX;
+signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, bussed_tx, busuart_tx, busflashset_tx, busmon_tx, bustrig_tx : CTRLBUS_TX;
+
+signal spi_sdi, spi_sdo, spi_sck : std_logic;
+signal spi_cs, spi_clr : std_logic_vector(15 downto 0);
+signal uart_rx, uart_tx : std_logic;
+
+signal flashset_active, debug_active : std_logic;
+signal flash_cs_i, flash_clk_i, flash_out_i : std_logic;
+signal flash_cs_s, flash_clk_s, flash_out_s : std_logic;
+
+signal debug_rx, debug_tx : std_logic;
+signal debug_status : std_logic_vector(31 downto 0);
+
+begin
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 7,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 3 => x"0500", 4 => x"0600", 5 => x"0180", 6 => x"0f00", 7 => x"0f80", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 5, 3 => 1, 4 => 2, 5 => 4, 6 => 7, 7 => 7, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ REGIO_RX => BUS_RX,
+ REGIO_TX => BUS_TX,
+
+ BUS_RX(0) => busflash_rx,
+ BUS_RX(1) => busspi_rx,
+ BUS_RX(2) => bussed_rx,
+ BUS_RX(3) => busuart_rx,
+ BUS_RX(4) => busflashset_rx,
+ BUS_RX(5) => bustrig_rx,
+ BUS_RX(6) => busmon_rx,
+ BUS_TX(0) => busflash_tx,
+ BUS_TX(1) => busspi_tx,
+ BUS_TX(2) => bussed_tx,
+ BUS_TX(3) => busuart_tx,
+ BUS_TX(4) => busflashset_tx,
+ BUS_TX(5) => bustrig_tx,
+ BUS_TX(6) => busmon_tx,
+
+ STAT_DEBUG => open
+ );
+
+
+
+---------------------------------------------------------------------------
+-- Flash & Reboot
+---------------------------------------------------------------------------
+ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload_record
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ BUS_RX => busflash_rx,
+ BUS_TX => busflash_tx,
+
+ DO_REBOOT_IN => REBOOT_IN,
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => flash_cs_i,
+ SPI_SCK_OUT => flash_clk_i,
+ SPI_SDO_OUT => flash_out_i,
+ SPI_SDI_IN => FLASH_IN
+ );
+
+
+---------------------------------------------------------------------------
+-- Load Settings from Flash
+---------------------------------------------------------------------------
+THE_FLASH_REGS : entity work.load_settings
+ port map(
+ CLK => CLK,
+ RST => RESET,
+
+ -- the bus handler signals
+ BUS_RX => busflashset_rx,
+ BUS_TX => busflashset_tx,
+
+ IS_ACTIVE => flashset_active,
+
+ BUS_MASTER_TX => bus_flash_rx_out,
+ BUS_MASTER_RX => bus_flash_tx_in,
+
+ SPI_MOSI => flash_out_s,
+ SPI_MISO => FLASH_IN,
+ SPI_SCK => flash_clk_s,
+ SPI_NCS => flash_cs_s
+
+ );
+
+ BUS_MASTER_ACTIVE <= flashset_active or debug_active;
+ FLASH_CS <= flash_cs_i when flashset_active = '0' else flash_cs_s;
+ FLASH_CLK <= flash_clk_i when flashset_active = '0' else flash_clk_s;
+ FLASH_OUT <= flash_out_i when flashset_active = '0' else flash_out_s;
+
+ bus_flash_tx_in <= BUS_MASTER_IN;
+ bus_debug_tx_in <= BUS_MASTER_IN;
+
+ BUS_MASTER_OUT <= bus_debug_rx_out when debug_active = '1' else
+ bus_flash_rx_out;
+
+
+---------------------------------------------------------------------------
+-- SED Detection
+---------------------------------------------------------------------------
+ THE_SED : entity work.sedcheck
+ port map(
+ CLK => CLK,
+ ERROR_OUT => SED_ERROR_OUT,
+ BUS_RX => bussed_rx,
+ BUS_TX => bussed_tx,
+ DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- LCD
+---------------------------------------------------------------------------
+gen_lcd : if INCLUDE_LCD = 1 generate
+ THE_LCD : entity work.lcd
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ MOSI => LCD_OUT(2),
+ SCK => LCD_OUT(1),
+ DC => LCD_OUT(3),
+ CS => LCD_OUT(4),
+ RST => LCD_OUT(0),
+
+ INPUT => LCD_DATA_IN,
+ DEBUG => open
+ );
+end generate;
+
+---------------------------------------------------------------------------
+-- SPI
+---------------------------------------------------------------------------
+ gen_SPI : if INCLUDE_SPI = 1 generate
+ THE_SPI : spi_ltc2600
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+ -- Slave bus
+ BUS_ADDR_IN => busspi_rx.addr(4 downto 0),
+ BUS_READ_IN => busspi_rx.read,
+ BUS_WRITE_IN => busspi_rx.write,
+ BUS_ACK_OUT => busspi_tx.ack,
+ BUS_BUSY_OUT => busspi_tx.nack,
+ BUS_DATA_IN => busspi_rx.data,
+ BUS_DATA_OUT => busspi_tx.data,
+ -- SPI connections
+ SPI_CS_OUT(15 downto 0) => spi_cs,
+ SPI_SDI_IN => spi_sdi,
+ SPI_SDO_OUT => spi_sdo,
+ SPI_SCK_OUT => spi_sck,
+ SPI_CLR_OUT => spi_clr
+ );
+ SPI_CS_OUT <= spi_cs;
+ SPI_CLK_OUT <= (others => spi_sck);
+ SPI_MOSI_OUT <= (others => spi_sdo);
+ SPI_CLR_OUT <= spi_clr;
+ spi_sdi <= or_all(SPI_MISO_IN and not spi_cs);
+
+ end generate;
+ busspi_tx.unknown <= '0';
+
+---------------------------------------------------------------------------
+-- UART
+---------------------------------------------------------------------------
+ gen_uart : if INCLUDE_UART = 1 generate
+ THE_UART : entity work.uart
+ generic map(
+ OUTPUTS => 1
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ UART_RX(0) => uart_rx,
+ UART_TX(0) => uart_tx,
+ BUS_RX => busuart_rx,
+ BUS_TX => busuart_tx
+ );
+ end generate;
+
+---------------------------------------------------------------------------
+-- Debug Connection
+---------------------------------------------------------------------------
+gen_debug : if INCLUDE_DEBUG_INTERFACE = 1 generate
+ THE_DEBUG : entity work.debuguart
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ RX_IN => DEBUG_RX_IN,
+ TX_OUT => DEBUG_TX_OUT,
+
+ DEBUG_ACTIVE => debug_active,
+
+ BUS_DEBUG_TX => bus_debug_tx_in,
+ BUS_DEBUG_RX => bus_debug_rx_out,
+
+ STATUS => debug_status
+
+ );
+end generate;
+gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate
+ bus_debug_rx_out.write <= '0';
+ bus_debug_rx_out.read <= '0';
+ bus_debug_rx_out.timeout <= '0';
+ bus_debug_rx_out.addr <= (others => '0');
+ bus_debug_rx_out.data <= (others => '0');
+ debug_tx <= 'Z';
+end generate;
+
+---------------------------------------------------------------------------
+-- Trigger logic
+---------------------------------------------------------------------------
+gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
+ THE_TRIG_LOGIC : input_to_trigger_logic
+ generic map(
+ INPUTS => TRIG_GEN_INPUT_NUM,
+ OUTPUTS => TRIG_GEN_OUTPUT_NUM
+ )
+ port map(
+ CLK => CLK,
+
+ INPUT => TRIG_GEN_INPUTS,
+ OUTPUT => TRIG_GEN_OUTPUTS,
+
+ DATA_IN => bustrig_rx.data,
+ DATA_OUT => bustrig_tx.data,
+ WRITE_IN => bustrig_rx.write,
+ READ_IN => bustrig_rx.read,
+ ACK_OUT => bustrig_tx.ack,
+ NACK_OUT => bustrig_tx.nack,
+ ADDR_IN => bustrig_rx.addr
+ );
+
+end generate;
+
+gen_noTRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
+ bustrig_tx.unknown <= bustrig_rx.read or bustrig_rx.write;
+end generate;
+
+---------------------------------------------------------------------------
+-- Input Statistics
+---------------------------------------------------------------------------
+gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
+
+ THE_STAT_LOGIC : entity work.input_statistics
+ generic map(
+ INPUTS => MONITOR_INPUT_NUM,
+ SINGLE_FIFO_ONLY => USE_SINGLE_FIFO
+ )
+ port map(
+ CLK => CLK,
+
+ INPUT => MONITOR_INPUTS,
+
+ DATA_IN => busmon_rx.data,
+ DATA_OUT => busmon_tx.data,
+ WRITE_IN => busmon_rx.write,
+ READ_IN => busmon_rx.read,
+ ACK_OUT => busmon_tx.ack,
+ NACK_OUT => busmon_tx.nack,
+ ADDR_IN => busmon_rx.addr
+ );
+end generate;
+
+gen_noSTATISTICS : if INCLUDE_STATISTICS = 0 generate
+ busmon_tx.unknown <= busmon_rx.read or busmon_rx.write;
+end generate;
+
+DEBUG_OUT <= debug_status;
+
+
+end architecture;
\ No newline at end of file
jspc29 / trb3.git / commitdiff