port(
CLK : in std_logic;
TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
RESET : in std_logic;
GSR_N : in std_logic;
-- Debug
+component trb_net16_gbe_buf is
+generic(
+ DO_SIMULATION : integer range 0 to 1 := 1;
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
+);
+port(
+ CLK : in std_logic;
+ TEST_CLK : in std_logic; -- only for simulation!
+ CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ -- Debug
+ STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
+ STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
+ -- configuration interface
+ IP_CFG_START_IN : in std_logic;
+ IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
+ IP_CFG_DONE_OUT : out std_logic;
+ IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
+ IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
+ IP_CFG_MEM_CLK_OUT : out std_logic;
+ MR_RESET_IN : in std_logic;
+ MR_MODE_IN : in std_logic;
+ MR_RESTART_IN : in std_logic;
+ -- gk 29.03.10
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- gk 22.04.10
+ -- registers setup interface
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
+ BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
+ BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
+ BUS_ACK_OUT : out std_logic; -- gk 26.04.10
+ -- gk 23.04.10
+ LED_PACKET_SENT_OUT : out std_logic;
+ LED_AN_DONE_N_OUT : out std_logic;
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
+ CTS_CODE_IN : in std_logic_vector (7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector (31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector (15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ --SFP Connection
+ SFP_RXD_P_IN : in std_logic;
+ SFP_RXD_N_IN : in std_logic;
+ SFP_TXD_P_OUT : out std_logic;
+ SFP_TXD_N_OUT : out std_logic;
+ SFP_REFCLK_P_IN : in std_logic;
+ SFP_REFCLK_N_IN : in std_logic;
+ SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SFP_TXDIS_OUT : out std_logic; -- SFP disable
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- PacketConstructor interface
+ IG_CTS_CTR_TST : out std_logic_vector(2 downto 0);
+ IG_REM_CTR_TST : out std_logic_vector(3 downto 0);
+ IG_BSM_LOAD_TST : out std_logic_vector(3 downto 0);
+ IG_BSM_SAVE_TST : out std_logic_vector(3 downto 0);
+ IG_DATA_TST : out std_logic_vector(15 downto 0);
+ IG_WCNT_TST : out std_logic_vector(15 downto 0);
+ IG_RCNT_TST : out std_logic_vector(16 downto 0);
+ IG_RD_EN_TST : out std_logic;
+ IG_WR_EN_TST : out std_logic;
+ IG_EMPTY_TST : out std_logic;
+ IG_AEMPTY_TST : out std_logic;
+ IG_FULL_TST : out std_logic;
+ IG_AFULL_TST : out std_logic;
+ PC_WR_EN_TST : out std_logic;
+ PC_DATA_TST : out std_logic_vector (7 downto 0);
+ PC_READY_TST : out std_logic;
+ PC_START_OF_SUB_TST : out std_logic;
+ PC_END_OF_DATA_TST : out std_logic;
+ PC_SUB_SIZE_TST : out std_logic_vector(31 downto 0);
+ PC_TRIG_NR_TST : out std_logic_vector(31 downto 0);
+ PC_PADDING_TST : out std_logic;
+ PC_DECODING_TST : out std_logic_vector(31 downto 0);
+ PC_EVENT_ID_TST : out std_logic_vector(31 downto 0);
+ PC_QUEUE_DEC_TST : out std_logic_vector(31 downto 0);
+ PC_BSM_CONSTR_TST : out std_logic_vector(3 downto 0);
+ PC_BSM_LOAD_TST : out std_logic_vector(3 downto 0);
+ PC_BSM_SAVE_TST : out std_logic_vector(3 downto 0);
+ PC_SHF_EMPTY_TST : out std_logic;
+ PC_SHF_FULL_TST : out std_logic;
+ PC_SHF_WR_EN_TST : out std_logic;
+ PC_SHF_RD_EN_TST : out std_logic;
+ PC_SHF_Q_TST : out std_logic_vector(7 downto 0);
+ PC_DF_EMPTY_TST : out std_logic;
+ PC_DF_FULL_TST : out std_logic;
+ PC_DF_WR_EN_TST : out std_logic;
+ PC_DF_RD_EN_TST : out std_logic;
+ PC_DF_Q_TST : out std_logic_vector(7 downto 0);
+ PC_ALL_CTR_TST : out std_logic_vector(4 downto 0);
+ PC_SUB_CTR_TST : out std_logic_vector(4 downto 0);
+ PC_BYTES_LOADED_TST : out std_logic_vector(15 downto 0);
+ PC_SIZE_LEFT_TST : out std_logic_vector(31 downto 0);
+ PC_SUB_SIZE_TO_SAVE_TST : out std_logic_vector(31 downto 0);
+ PC_SUB_SIZE_LOADED_TST : out std_logic_vector(31 downto 0);
+ PC_SUB_BYTES_LOADED_TST : out std_logic_vector(31 downto 0);
+ PC_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0);
+ PC_ACT_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0);
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- FrameConstructor interface
+ FC_WR_EN_TST : out std_logic;
+ FC_DATA_TST : out std_logic_vector(7 downto 0);
+ FC_H_READY_TST : out std_logic;
+ FC_READY_TST : out std_logic;
+ FC_IP_SIZE_TST : out std_logic_vector(15 downto 0);
+ FC_UDP_SIZE_TST : out std_logic_vector(15 downto 0);
+ FC_IDENT_TST : out std_logic_vector(15 downto 0);
+ FC_FLAGS_OFFSET_TST : out std_logic_vector(15 downto 0);
+ FC_SOD_TST : out std_logic;
+ FC_EOD_TST : out std_logic;
+ FC_BSM_CONSTR_TST : out std_logic_vector(7 downto 0);
+ FC_BSM_TRANS_TST : out std_logic_vector(3 downto 0);
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- FrameTransmitter interface
+ FT_DATA_TST : out std_logic_vector(8 downto 0);
+ FT_TX_EMPTY_TST : out std_logic;
+ FT_START_OF_PACKET_TST : out std_logic;
+ FT_BSM_INIT_TST : out std_logic_vector(3 downto 0);
+ FT_BSM_MAC_TST : out std_logic_vector(3 downto 0);
+ FT_BSM_TRANS_TST : out std_logic_vector(3 downto 0);
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- MAC interface
+ MAC_HADDR_TST : out std_logic_vector(7 downto 0);
+ MAC_HDATA_TST : out std_logic_vector(7 downto 0);
+ MAC_HCS_TST : out std_logic;
+ MAC_HWRITE_TST : out std_logic;
+ MAC_HREAD_TST : out std_logic;
+ MAC_HREADY_TST : out std_logic;
+ MAC_HDATA_EN_TST : out std_logic;
+ MAC_FIFOAVAIL_TST : out std_logic;
+ MAC_FIFOEOF_TST : out std_logic;
+ MAC_FIFOEMPTY_TST : out std_logic;
+ MAC_TX_READ_TST : out std_logic;
+ MAC_TX_DONE_TST : out std_logic;
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- pcs and serdes
+ PCS_AN_LP_ABILITY_TST : out std_logic_vector(15 downto 0);
+ PCS_AN_COMPLETE_TST : out std_logic;
+ PCS_AN_PAGE_RX_TST : out std_logic;
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- debug ports
+ ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
+);
+end component;
+
+component trb_net16_gbe_packet_constr is
+port(
+ RESET : in std_logic;
+ CLK : in std_logic;
+ -- ports for user logic
+ PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
+ PC_DATA_IN : in std_logic_vector(7 downto 0);
+ PC_READY_OUT : out std_logic;
+ PC_START_OF_SUB_IN : in std_logic;
+ PC_END_OF_DATA_IN : in std_logic;
+ -- queue and subevent layer headers
+ PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
+ PC_PADDING_IN : in std_logic; -- gk 29.03.10
+ PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
+ PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
+ PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
+ PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
+ PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
+ PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
+ -- FrameConstructor ports
+ FC_WR_EN_OUT : out std_logic;
+ FC_DATA_OUT : out std_logic_vector(7 downto 0);
+ FC_H_READY_IN : in std_logic;
+ FC_READY_IN : in std_logic;
+ FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ FC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ FC_SOD_OUT : out std_logic;
+ FC_EOD_OUT : out std_logic;
+ -- debug ports
+ BSM_CONSTR_OUT : out std_logic_vector(3 downto 0);
+ BSM_LOAD_OUT : out std_logic_vector(3 downto 0);
+ BSM_SAVE_OUT : out std_logic_vector(3 downto 0);
+ DBG_SHF_EMPTY : out std_logic;
+ DBG_SHF_FULL : out std_logic;
+ DBG_SHF_WR_EN : out std_logic;
+ DBG_SHF_RD_EN : out std_logic;
+ DBG_SHF_Q : out std_logic_vector(7 downto 0);
+ DBG_DF_EMPTY : out std_logic;
+ DBG_DF_FULL : out std_logic;
+ DBG_DF_WR_EN : out std_logic;
+ DBG_DF_RD_EN : out std_logic;
+ DBG_DF_Q : out std_logic_vector(7 downto 0);
+ DBG_ALL_CTR : out std_logic_vector(4 downto 0);
+ DBG_SUB_CTR : out std_logic_vector(4 downto 0);
+ DBG_MY_CTR : out std_logic_vector(1 downto 0);
+ DBG_BYTES_LOADED : out std_logic_vector(15 downto 0);
+ DBG_SIZE_LEFT : out std_logic_vector(31 downto 0);
+ DBG_SUB_SIZE_TO_SAVE : out std_logic_vector(31 downto 0);
+ DBG_SUB_SIZE_LOADED : out std_logic_vector(31 downto 0);
+ DBG_SUB_BYTES_LOADED : out std_logic_vector(31 downto 0);
+ DBG_QUEUE_SIZE : out std_logic_vector(31 downto 0);
+ DBG_ACT_QUEUE_SIZE : out std_logic_vector(31 downto 0);
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+);
+end component;
+
+component trb_net16_gbe_frame_constr is
+port(
+ -- ports for user logic
+ RESET : in std_logic;
+ CLK : in std_logic;
+ --
+ WR_EN_IN : in std_logic;
+ DATA_IN : in std_logic_vector(7 downto 0);
+ START_OF_DATA_IN : in std_logic;
+ END_OF_DATA_IN : in std_logic;
+ IP_F_SIZE_IN : in std_logic_vector(15 downto 0);
+ UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation
+ HEADERS_READY_OUT : out std_logic;
+ READY_OUT : out std_logic;
+ DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
+ IHL_VERSION_IN : in std_logic_vector(7 downto 0);
+ TOS_IN : in std_logic_vector(7 downto 0);
+ IDENTIFICATION_IN : in std_logic_vector(15 downto 0);
+ FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
+ TTL_IN : in std_logic_vector(7 downto 0);
+ PROTOCOL_IN : in std_logic_vector(7 downto 0);
+ -- ports for packetTransmitter
+ RD_CLK : in std_logic; -- 125MHz clock!!!
+ FT_DATA_OUT : out std_logic_vector(8 downto 0);
+ FT_TX_EMPTY_OUT : out std_logic;
+ FT_TX_RD_EN_IN : in std_logic;
+ FT_START_OF_PACKET_OUT : out std_logic;
+ FT_TX_DONE_IN : in std_logic;
+ -- debug ports
+ BSM_CONSTR_OUT : out std_logic_vector(7 downto 0);
+ BSM_TRANS_OUT : out std_logic_vector(3 downto 0);
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+);
+end component;
+
+component trb_net16_gbe_frame_trans is
+port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ TX_MAC_CLK : in std_logic;
+ TX_EMPTY_IN : in std_logic;
+ START_OF_PACKET_IN : in std_logic;
+ DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC
+ -- NEW PORTS
+ HADDR_OUT : out std_logic_vector(7 downto 0);
+ HDATA_OUT : out std_logic_vector(7 downto 0);
+ HCS_OUT : out std_logic;
+ HWRITE_OUT : out std_logic;
+ HREAD_OUT : out std_logic;
+ HREADY_IN : in std_logic;
+ HDATA_EN_IN : in std_logic;
+ TX_FIFOAVAIL_OUT : out std_logic;
+ TX_FIFOEOF_OUT : out std_logic;
+ TX_FIFOEMPTY_OUT : out std_logic;
+ TX_DONE_IN : in std_logic;
+ -- Debug
+ BSM_INIT_OUT : out std_logic_vector(3 downto 0);
+ BSM_MAC_OUT : out std_logic_vector(3 downto 0);
+ BSM_TRANS_OUT : out std_logic_vector(3 downto 0);
+ DBG_RD_DONE_OUT : out std_logic;
+ DBG_INIT_DONE_OUT : out std_logic;
+ DBG_ENABLED_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+);
+end component;
+
+component trb_net16_med_ecp_sfp_gbe_8b is
+-- gk 28.04.10
+generic (
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
+);
+port(
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ CLK_125_OUT : out std_logic;
+ CLK_RX_OUT : out std_logic;
+ CLK_TX_OUT : out std_logic;
+ CLK_125_TX_IN : in std_logic; -- gk 28.04.10 used when intclk
+ CLK_125_RX_IN : in std_logic; -- gk 28.04.10 used when intclk
+ --SGMII connection to frame transmitter (tsmac)
+ FT_TX_CLK_EN_OUT : out std_logic;
+ FT_RX_CLK_EN_OUT : out std_logic;
+ FT_COL_OUT : out std_logic;
+ FT_CRS_OUT : out std_logic;
+ FT_TXD_IN : in std_logic_vector(7 downto 0);
+ FT_TX_EN_IN : in std_logic;
+ FT_TX_ER_IN : in std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic;
+ SD_REFCLK_N_IN : in std_logic;
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic; -- SFP disable
+ -- Autonegotiation stuff
+ MR_RESET_IN : in std_logic;
+ MR_MODE_IN : in std_logic;
+ MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0);
+ MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0);
+ MR_AN_PAGE_RX_OUT : out std_logic;
+ MR_AN_COMPLETE_OUT : out std_logic;
+ MR_AN_ENABLE_IN : in std_logic;
+ MR_RESTART_AN_IN : in std_logic;
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+);
+end component;
+
+component gbe_setup is
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ -- interface to regio bus
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
+ BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
+ BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
+ BUS_ACK_OUT : out std_logic; -- gk 26.04.10
+
+ GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0);
+
+ -- output to gbe_buf
+ GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0);
+ GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0);
+ GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0);
+ GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0);
+ GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0);
+ GBE_USE_GBE_OUT : out std_logic;
+ GBE_USE_TRBNET_OUT : out std_logic;
+ GBE_USE_MULTIEVENTS_OUT : out std_logic;
+ GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10
+ GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
+ GBE_DELAY_OUT : out std_logic_vector(31 downto 0);
+ -- gk 01.06.10
+ DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0);
+ DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0);
+ DBG_PC1_IN : in std_logic_vector(31 downto 0);
+ DBG_PC2_IN : in std_logic_vector(31 downto 0);
+ DBG_FC1_IN : in std_logic_vector(31 downto 0);
+ DBG_FC2_IN : in std_logic_vector(31 downto 0);
+ DBG_FT1_IN : in std_logic_vector(31 downto 0);
+ DBG_FT2_IN : in std_logic_vector(31 downto 0);
+ DBG_FIFO_RD_EN_OUT : out std_logic;
+ DBG_FIFO_Q_IN : in std_logic_vector(8 downto 0)
+);
+end component;
+
+
+component ip_configurator is
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ -- configuration interface
+ START_CONFIG_IN : in std_logic; -- start configuration run
+ BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank
+ CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used
+ MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for
+ MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory
+ MEM_CLK_OUT : out std_logic; -- clock for BlockRAM
+ -- information for IP cores
+ DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address
+ DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address
+ DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port
+ SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address
+ SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address
+ SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port
+ MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size)
+ -- Debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+);
+end component;
+
+
component ipu_dummy is
port( CLK_IN : in std_logic; -- 100MHz local clock
jspc29 / trbnet.git / commitdiff