Xilinx FIFO 19x16 obuf by Boris

diff --git a/xilinx/virtex4/fifo_19x16_obuf.vhd b/xilinx/virtex4/fifo_19x16_obuf.vhd
index 254e1efadb6948173fa6911830bcabd7a0e36740..1230adf3ccc4ce1383f57140f6680edf43e4d483 100644 (file)
--- a/xilinx/virtex4/fifo_19x16_obuf.vhd
+++ b/xilinx/virtex4/fifo_19x16_obuf.vhd
@@ -34,7 +34,7 @@ port (
        rd_en: IN std_logic;
        rst: IN std_logic;
        wr_en: IN std_logic;
-       data_count: OUT std_logic_VECTOR(4 downto 0);
+       data_count: OUT std_logic_VECTOR(3 downto 0);
        dout: OUT std_logic_VECTOR(18 downto 0);
        empty: OUT std_logic;
        full: OUT std_logic;
@@ -46,6 +46,7 @@ end component;
 
 begin
 
+WCNT(4) <= '0';
 
 the_xilinx_fifo_19x16_obuf: xilinx_fifo_19x16_obuf
 port map(
@@ -55,7 +56,7 @@ port map(
        rd_en            => RdEn,
        rst              => Reset,
        wr_en            => WrEn,
-       data_count       => WCNT,
+       data_count       => WCNT(3 downto 0),
        dout             => Q,
        empty            => Empty,
        full             => Full,