]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
intermediate commit
authorCahit <c.ugur@gsi.de>
Tue, 11 Feb 2014 13:36:46 +0000 (14:36 +0100)
committerCahit <c.ugur@gsi.de>
Tue, 11 Feb 2014 13:36:46 +0000 (14:36 +0100)
32PinAddOn/trb3_periph_32PinAddOn.vhd
base/trb3_components.vhd
tdc_releases/tdc_v1.6/Channel.vhd
tdc_releases/tdc_v1.6/Channel_200.vhd
tdc_releases/tdc_v1.6/Readout.vhd
tdc_releases/tdc_v1.6/TDC.vhd

index 0a2eb9bad518bc7090d4d17125828aa54686869b..6f064e48c5646c7c6fcf78efc65118d41c90f2f9 100644 (file)
@@ -686,7 +686,7 @@ begin
   DAC_SPI : spi_ltc2600
     generic map (
       BITS       => 14,
-      WAITCYCLES => 15)
+      WAITCYCLES => 100)
     port map (
       CLK_IN         => clk_100_i,
       RESET_IN       => reset_i,
@@ -815,14 +815,14 @@ begin
       CONTROL_REG_IN        => tdc_ctrl_reg);
 
   -- For single edge measurements
-  --hit_in_i <= INP;    
+  hit_in_i <= INP;    
   --hit_in_i <= (others => timing_trg_received_i);
 
-  -- For ToT Measurements
-  Gen_Hit_In_Signals : for i in 1 to 32 generate
-    hit_in_i(i*2-1) <= INP(i-1);
-    hit_in_i(i*2)   <= not INP(i-1);
-  end generate Gen_Hit_In_Signals;
+  ---- For ToT Measurements
+  --Gen_Hit_In_Signals : for i in 1 to 32 generate
+  --  hit_in_i(i*2-1) <= INP(i-1);
+  --  hit_in_i(i*2)   <= not INP(i-1);
+  --end generate Gen_Hit_In_Signals;
 
   -- Trigger on a TDC Channel
   FPGA5_COMM(10) <= hit_in_i(to_integer(unsigned(tdc_ctrl_reg(5*32+7 downto 5*32))));
index 52656d9d64939533e1cd8ffc1c75e2f1d37c81f5..649cdcd39a05a51b9c4483d054e2138fb05074f7 100644 (file)
@@ -211,6 +211,7 @@ package trb3_components is
   component Channel_200
     generic (
       CHANNEL_ID : integer range 0 to 64;
+      DEBUG      : integer range 0 to 1;
       SIMULATION : integer range 0 to 1;
       REFERENCE  : integer range 0 to 1);
     port (
@@ -218,6 +219,7 @@ package trb3_components is
       RESET_200            : in  std_logic;
       CLK_100              : in  std_logic;
       RESET_100            : in  std_logic;
+      RESET_COUNTERS       : in  std_logic;
       HIT_IN               : in  std_logic;
       TRIGGER_WIN_END_TDC  : in  std_logic;
       TRIGGER_WIN_END_RDO  : in  std_logic;
index 6665397f392efd4f824c91314301da3a6ffbefd5..236da4c026deb79d3ef4efd78d4656ca55a287cb 100644 (file)
@@ -87,21 +87,24 @@ architecture Channel of Channel is
   signal rd_en_reg : std_logic;
 
   -- debug
-  signal sync_q                : std_logic_vector(2 downto 0);
-  signal hit_pulse             : std_logic;
-  signal hit_pulse_100         : std_logic;
-  signal encoder_finished_i    : std_logic;
-  signal encoder_finished_100  : std_logic;
-  signal encoder_start_i       : std_logic;
-  signal encoder_start_100     : std_logic;
-  signal fifo_write_i          : std_logic;
-  signal fifo_write_100        : std_logic;
-  signal lost_hit_cntr         : unsigned(23 downto 0);
-  signal hit_detect_cntr       : unsigned(23 downto 0);
-  signal encoder_start_cntr    : unsigned(23 downto 0);
-  signal encoder_finished_cntr : unsigned(23 downto 0);
-  signal fifo_write_cntr       : unsigned(23 downto 0);
-  signal channel_200_debug_i   : std_logic_vector(31 downto 0);
+  signal sync_q                  : std_logic_vector(2 downto 0);
+  signal hit_pulse               : std_logic;
+  signal hit_pulse_100           : std_logic;
+  signal encoder_finished_i      : std_logic;
+  signal encoder_finished_100    : std_logic;
+  signal encoder_start_i         : std_logic;
+  signal encoder_start_100       : std_logic;
+  signal fifo_write_i            : std_logic;
+  signal fifo_write_100          : std_logic;
+  signal lost_hit_cntr           : unsigned(23 downto 0);
+  signal hit_detect_cntr         : unsigned(23 downto 0);
+  signal encoder_start_cntr      : unsigned(23 downto 0);
+  signal encoder_finished_cntr   : unsigned(23 downto 0);
+  signal fifo_write_cntr         : unsigned(23 downto 0);
+  signal channel_200_debug_i     : std_logic_vector(31 downto 0);
+  signal ch_buffer_counter       : unsigned(15 downto 0) := (others => '0');
+  signal ch_buffer_out_counter   : unsigned(15 downto 0) := (others => '0');
+  signal ch_buffer_valid_counter : unsigned(15 downto 0) := (others => '0');
 
   -- other
 
@@ -133,6 +136,7 @@ begin
   Channel200 : Channel_200
     generic map (
       CHANNEL_ID => CHANNEL_ID,
+      DEBUG      => DEBUG,
       SIMULATION => SIMULATION,
       REFERENCE  => REFERENCE)
     port map (
@@ -140,6 +144,7 @@ begin
       RESET_200            => RESET_200,
       CLK_100              => CLK_100,
       RESET_100            => RESET_100,
+      RESET_COUNTERS       => RESET_COUNTERS,
       HIT_IN               => hit_buf,
       TRIGGER_WIN_END_TDC  => trig_win_end_tdc_i,
       TRIGGER_WIN_END_RDO  => trig_win_end_rdo_i,
@@ -280,42 +285,52 @@ begin
     begin
       if rising_edge(CLK_100) then
         if RESET_COUNTERS = '1' then
-          encoder_start_cntr <= (others => '0');
-        elsif encoder_start_100 = '1' then
-          encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1);
+          ch_buffer_counter <= (others => '0');
+        elsif ch_data_valid_i = '1' then
+          if ch_data_i(35 downto 31) = "00011" then  -- it is a data word
+            ch_buffer_counter <= ch_buffer_counter + to_unsigned(1, 16);
+          end if;
         end if;
+        --elsif encoder_start_100 = '1' then
+        --  encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1);
+        --end if;
       end if;
     end process Encoder_Start_Counter;
 
-    ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100);
+    --ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100);
+    ENCODER_START_NUMBER(15 downto 0) <= std_logic_vector(ch_buffer_counter) when rising_edge(CLK_100);
 
     --purpose: Counts the encoder finished signals
     ENCODER_FINISHED_Counter : process (CLK_100)
     begin
       if rising_edge(CLK_100) then
         if RESET_COUNTERS = '1' then
-          encoder_finished_cntr <= (others => '0');
-        elsif encoder_finished_100 = '1' then
-          encoder_finished_cntr <= encoder_finished_cntr + to_unsigned(1, 1);
+          ch_buffer_out_counter <= (others => '0');
+        elsif buf_data_i(35 downto 31) = "00011" then
+          ch_buffer_out_counter <= ch_buffer_out_counter + to_unsigned(1, 16);
         end if;
       end if;
     end process ENCODER_FINISHED_Counter;
 
-    ENCODER_FINISHED_NUMBER <= std_logic_vector(encoder_finished_cntr) when rising_edge(CLK_100);
+    --ENCODER_FINISHED_NUMBER <= std_logic_vector(encoder_finished_cntr) when rising_edge(CLK_100);
+    ENCODER_FINISHED_NUMBER(15 downto 0) <= std_logic_vector(ch_buffer_out_counter) when rising_edge(CLK_100);
 
     --purpose: Counts the written hits
     FIFO_WRITE_Counter : process (CLK_100)
     begin
       if rising_edge(CLK_100) then
         if RESET_COUNTERS = '1' then
-          fifo_write_cntr <= (others => '0');
-        elsif fifo_write_100 = '1' then
-          fifo_write_cntr <= fifo_write_cntr + to_unsigned(1, 1);
+          ch_buffer_valid_counter <= (others => '0');
+        elsif buf_data_valid_i = '1' then
+          if buf_data_i(35 downto 31) = "00011" then
+            ch_buffer_valid_counter <= ch_buffer_valid_counter + to_unsigned(1, 16);
+          end if;          
         end if;
       end if;
     end process FIFO_WRITE_Counter;
 
-    FIFO_WRITE_NUMBER <= std_logic_vector(fifo_write_cntr) when rising_edge(CLK_100);
+    --FIFO_WRITE_NUMBER <= std_logic_vector(fifo_write_cntr) when rising_edge(CLK_100);
+    FIFO_WRITE_NUMBER(15 downto 0) <= std_logic_vector(ch_buffer_valid_counter) when rising_edge(CLK_100);
   end generate gen_DEBUG;
 
 -------------------------------------------------------------------------------
index 6fd730c0438c8a10f4e3121d4cc17535df585a77..d66775a993b22f834504d01459b4fe9b92fc212c 100644 (file)
@@ -5,7 +5,7 @@
 -- File       : Channel_200.vhd
 -- Author     : c.ugur@gsi.de
 -- Created    : 2012-08-28
--- Last update: 2014-01-22
+-- Last update: 2014-01-28
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -23,6 +23,7 @@ entity Channel_200 is
 
   generic (
     CHANNEL_ID : integer range 0 to 64;
+    DEBUG      : integer range 0 to 1;
     SIMULATION : integer range 0 to 1;
     REFERENCE  : integer range 0 to 1);
   port (
@@ -30,6 +31,7 @@ entity Channel_200 is
     RESET_200            : in  std_logic;  -- reset sync with 200Mhz clk
     CLK_100              : in  std_logic;  -- 100 MHz clk
     RESET_100            : in  std_logic;  -- reset sync with 100Mhz clk
+    RESET_COUNTERS       : in  std_logic;  -- reset for counters
 --
     HIT_IN               : in  std_logic;  -- hit in
     TRIGGER_WIN_END_TDC  : in  std_logic;  -- trigger window end strobe
@@ -130,10 +132,12 @@ architecture Channel_200 of Channel_200 is
 
   -----------------------------------------------------------------------------
   -- debug
-  signal data_cnt_total  : integer range 0 to 2147483647 := 0;
-  signal data_cnt_event  : integer range 0 to 255        := 0;
-  signal epoch_cnt_total : integer range 0 to 65535      := 0;
-  signal epoch_cnt_event : integer range 0 to 127        := 0;
+  signal data_cnt_total      : integer range 0 to 2147483647 := 0;
+  signal data_cnt_event      : integer range 0 to 255        := 0;
+  signal epoch_cnt_total     : integer range 0 to 65535      := 0;
+  signal epoch_cnt_event     : integer range 0 to 127        := 0;
+  signal ch_fifo_counter     : unsigned(15 downto 0)         := (others => '0');
+  signal ch_fifo_counter_100 : unsigned(15 downto 0)         := (others => '0');
   -----------------------------------------------------------------------------
 
   attribute syn_keep                  : boolean;
@@ -205,7 +209,7 @@ begin  -- Channel_200
     end process EpochCounterCapture;
   end generate isChannelEpoch;
 
-  isReferenceEpoch: if REFERENCE = c_YES generate
+  isReferenceEpoch : if REFERENCE = c_YES generate
     EpochCounterCapture : process (CLK_200)
     begin
       if rising_edge(CLK_200) then
@@ -221,7 +225,7 @@ begin  -- Channel_200
       end if;
     end process EpochCounterCapture;
   end generate isReferenceEpoch;
-  
+
   --purpose: Encoder
   Encoder : Encoder_304_Bit
     port map (
@@ -345,8 +349,8 @@ begin  -- Channel_200
           elsif epoch_cntr_updated = '0' and encoder_finished_i = '1' then
             FSM_WR_NEXT <= WRITE_DATA;
           elsif epoch_cntr_updated = '1' and encoder_finished_i = '1' then
-            write_epoch_fsm <= '1';
-            FSM_WR_NEXT     <= WRITE_DATA;
+            --write_epoch_fsm <= '1';
+            FSM_WR_NEXT <= WRITE_DATA;
           elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then
             FSM_WR_NEXT <= WRITE_STOP_A;
           else
@@ -472,8 +476,8 @@ begin  -- Channel_200
           elsif epoch_cntr_updated = '0' and encoder_finished_i = '1' then
             FSM_WR_NEXT <= WRITE_DATA;
           elsif epoch_cntr_updated = '1' and encoder_finished_i = '1' then
-            write_epoch_fsm <= '1';
-            FSM_WR_NEXT     <= WRITE_DATA;
+            --write_epoch_fsm <= '1';
+            FSM_WR_NEXT <= WRITE_DATA;
           elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then
             FSM_WR_NEXT <= WRITE_STOP_A;
           else
@@ -725,14 +729,32 @@ begin  -- Channel_200
 -------------------------------------------------------------------------------
 -- DEBUG
 -------------------------------------------------------------------------------
-  CHANNEL_200_DEBUG(7 downto 0)   <= fifo_data_in_i(35 downto 28);
-  CHANNEL_200_DEBUG(15 downto 8)  <= fifo_data_i(35 downto 28);
-  CHANNEL_200_DEBUG(16)           <= fifo_wr_en_i;
-  CHANNEL_200_DEBUG(17)           <= fifo_data_valid_i;
-  CHANNEL_200_DEBUG(18)           <= fifo_rd_en_i;
-  CHANNEL_200_DEBUG(23 downto 19) <= (others => '0');
-  CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i;
-  CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i;
+  --CHANNEL_200_DEBUG(7 downto 0)   <= fifo_data_in_i(35 downto 28);
+  --CHANNEL_200_DEBUG(15 downto 8)  <= fifo_data_i(35 downto 28);
+  --CHANNEL_200_DEBUG(16)           <= fifo_wr_en_i;
+  --CHANNEL_200_DEBUG(17)           <= fifo_data_valid_i;
+  --CHANNEL_200_DEBUG(18)           <= fifo_rd_en_i;
+  --CHANNEL_200_DEBUG(23 downto 19) <= (others => '0');
+  --CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i;
+  --CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i;
+
+  ch_fifo_counter_100            <= ch_fifo_counter when rising_edge(CLK_100);
+  CHANNEL_200_DEBUG(15 downto 0) <= std_logic_vector(ch_fifo_counter_100);
+
+  gen_DEBUG : if DEBUG = c_YES generate
+    debugChannelDataCount : process (CLK_200)
+    begin
+      if rising_edge(CLK_200) then
+        if RESET_COUNTERS = '1' then
+          ch_fifo_counter <= (others => '0');
+        elsif fifo_wr_en_i = '1' then
+          if fifo_data_in_i(35 downto 31) = "00011" then  -- it is a data word
+            ch_fifo_counter <= ch_fifo_counter + to_unsigned(1, 16);
+          end if;
+        end if;
+      end if;
+    end process debugChannelDataCount;
+  end generate gen_DEBUG;
 
   gen_SIMULATION : if SIMULATION = c_YES generate
     -- count data written
index da6d8d7f950505049a20a4ef29c3e472038eb65a..4d3da45a98e1827204f8bf91c53ff9f779c3f1d9 100644 (file)
@@ -5,7 +5,7 @@
 -- File       : Readout.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-10-25
--- Last update: 2014-01-23
+-- Last update: 2014-01-29
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -178,8 +178,8 @@ architecture behavioral of Readout is
   signal wr_number               : unsigned(7 downto 0);
   signal fifo_nr_rd_fsm          : integer range 0 to CHANNEL_NUMBER := 0;
   signal fifo_nr_wr_fsm          : integer range 0 to CHANNEL_NUMBER := 0;
-  signal buf_delay_fsm           : integer range 0 to 15             := 0;
-  signal buf_delay_i             : integer range 0 to 15             := 0;
+  signal buf_delay_fsm           : integer range 0 to 31             := 0;
+  signal buf_delay_i             : integer range 0 to 31             := 0;
   signal start_ch_fsm            : integer range 0 to CHANNEL_NUMBER := 0;
 --  signal wr_trailer_fsm          : std_logic;
   signal idle_fsm                : std_logic;
@@ -435,7 +435,7 @@ begin  -- behavioral
         rd_fsm_debug_fsm <= x"2";
 
       when WAIT_FOR_BUFFER_TRANSFER =>  -- the data from channel fifo is written to the buffer
-        if buf_delay_i = 15 then
+        if buf_delay_i = 31 then
           RD_NEXT       <= RD_CH;
           buf_delay_fsm <= 0;
         else
@@ -471,8 +471,8 @@ begin  -- behavioral
       when WAIT_FOR_LVL1_TRIG_A =>      -- wait for trigger data valid
         if TRG_DATA_VALID_IN = '1' then
           RD_NEXT <= WAIT_FOR_LVL1_TRIG_B;
-        elsif TMGTRG_TIMEOUT_IN = '1' then
-          RD_NEXT <= IDLE;
+        --elsif TMGTRG_TIMEOUT_IN = '1' then
+        --  RD_NEXT <= IDLE;
         end if;
         wait_fsm         <= '1';
         rd_fsm_debug_fsm <= x"6";
@@ -700,8 +700,9 @@ begin  -- behavioral
 
   DATA_OUT                    <= data_out_reg;
   DATA_WRITE_OUT              <= data_wr_reg;
-  finished_i                  <= (data_finished or wr_finished_2reg) when rising_edge(CLK_100);
-  DATA_FINISHED_OUT           <= data_finished; --finished_i;
+--  finished_i                  <= (data_finished or wr_finished_2reg) when rising_edge(CLK_100);
+  finished_i                  <= data_finished when rising_edge(CLK_100);
+  DATA_FINISHED_OUT           <= finished_i;
   TRG_RELEASE_OUT             <= trig_release_reg;
   TRG_STATUSBIT_OUT           <= (others => '0');
   READOUT_DEBUG(3 downto 0)   <= rd_fsm_debug;
index c376f3e8f60cfe584b104bced9886deb08f016f6..ed0a5c3d93654e1a1dd6f5578adb31f03e0a6be7 100644 (file)
@@ -224,7 +224,7 @@ begin
   end generate GEN_Channel_Enable;
 
   -- purpose: Calibration trigger for the reference channel
-  process (calibration_on, HIT_CALIBRATION) is
+  process (calibration_on, HIT_CALIBRATION, REFERENCE_TIME) is
   begin  -- process
     if calibration_on = '1' then
           hit_in_i(0) <= HIT_CALIBRATION;
@@ -371,7 +371,8 @@ begin
       TRIGGER_WIN_POST_IN     => unsigned(TRG_WIN_POST),
       TRIGGER_WIN_END_RDO_OUT => trig_win_end_rdo,
       TRIGGER_WIN_END_TDC_OUT => trig_win_end_tdc);
-  trig_in_i <= REFERENCE_TIME or VALID_NOTIMING_TRG_IN;
+--  trig_in_i <= REFERENCE_TIME or VALID_NOTIMING_TRG_IN;
+  trig_in_i <= VALID_TIMING_TRG_IN or VALID_NOTIMING_TRG_IN;
   
   -- Readout
   TheReadout : Readout
@@ -532,23 +533,23 @@ begin
 
 --  status_registers_bus_i(21) <= ch_200_debug_i(0);
   
-  --TheLostHitBus : BusHandler
-  --  generic map (
-  --    BUS_LENGTH => CHANNEL_NUMBER-1)
-  --  port map (
-  --    RESET            => reset_rdo,
-  --    CLK              => CLK_READOUT,
-  --    DATA_IN          => ch_lost_hit_bus_i,
-  --    READ_EN_IN       => LHB_READ_EN_IN,
-  --    WRITE_EN_IN      => LHB_WRITE_EN_IN,
-  --    ADDR_IN          => LHB_ADDR_IN,
-  --    DATA_OUT         => LHB_DATA_OUT,
-  --    DATAREADY_OUT    => LHB_DATAREADY_OUT,
-  --    UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT);
-
-  --GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate
-  --  ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT);
-  --end generate GenLostHitNumber;
+  TheLostHitBus : BusHandler
+    generic map (
+      BUS_LENGTH => CHANNEL_NUMBER-1)
+    port map (
+      RESET            => reset_rdo,
+      CLK              => CLK_READOUT,
+      DATA_IN          => ch_lost_hit_bus_i,
+      READ_EN_IN       => LHB_READ_EN_IN,
+      WRITE_EN_IN      => LHB_WRITE_EN_IN,
+      ADDR_IN          => LHB_ADDR_IN,
+      DATA_OUT         => LHB_DATA_OUT,
+      DATAREADY_OUT    => LHB_DATAREADY_OUT,
+      UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT);
+
+  GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate
+    ch_lost_hit_bus_i(i) <= ch_encoder_start_number_i(i)(15 downto 0) & ch_200_debug_i(i)(15 downto 0) when rising_edge(CLK_READOUT);
+  end generate GenLostHitNumber;
 
   --TheEncoderStartBus : BusHandler
   --  generic map (
@@ -572,27 +573,28 @@ begin
   ESB_DATAREADY_OUT    <= '0';
   ESB_UNKNOWN_ADDR_OUT <= '0';
 
-  --TheEncoderFinishedBus : BusHandler
-  --  generic map (
-  --    BUS_LENGTH => CHANNEL_NUMBER-1)
-  --  port map (
-  --    RESET            => reset_rdo,
-  --    CLK              => CLK_READOUT,
-  --    DATA_IN          => ch_encoder_finished_bus_i,
-  --    READ_EN_IN       => EFB_READ_EN_IN,
-  --    WRITE_EN_IN      => EFB_WRITE_EN_IN,
-  --    ADDR_IN          => EFB_ADDR_IN,
-  --    DATA_OUT         => EFB_DATA_OUT,
-  --    DATAREADY_OUT    => EFB_DATAREADY_OUT,
-  --    UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT);
-
-  --GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate
-  --  ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT);
-  --end generate GenFifoWriteNumber;
-
-  EFB_DATA_OUT         <= (others => '0');
-  EFB_DATAREADY_OUT    <= '0';
-  EFB_UNKNOWN_ADDR_OUT <= '0';
+  TheEncoderFinishedBus : BusHandler
+    generic map (
+      BUS_LENGTH => CHANNEL_NUMBER-1)
+    port map (
+      RESET            => reset_rdo,
+      CLK              => CLK_READOUT,
+      DATA_IN          => ch_encoder_finished_bus_i,
+      READ_EN_IN       => EFB_READ_EN_IN,
+      WRITE_EN_IN      => EFB_WRITE_EN_IN,
+      ADDR_IN          => EFB_ADDR_IN,
+      DATA_OUT         => EFB_DATA_OUT,
+      DATAREADY_OUT    => EFB_DATAREADY_OUT,
+      UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT);
+
+  GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate
+    --ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT);
+    ch_encoder_finished_bus_i(i) <= ch_fifo_write_number_i(i)(15 downto 0)& ch_encoder_finished_number_i(i)(15 downto 0) when rising_edge(CLK_READOUT);
+  end generate GenFifoWriteNumber;
+
+  --EFB_DATA_OUT         <= (others => '0');
+  --EFB_DATAREADY_OUT    <= '0';
+  --EFB_UNKNOWN_ADDR_OUT <= '0';
 
 -- Logic Analyser
   TheLogicAnalyser : LogicAnalyser