update ECP5 media interface

diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx b/media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx
new file mode 100644 (file)
index 0000000..4dfcdb9
--- /dev/null
+++ b/media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 11 25 09:50:53.703" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+               <File name="serdes_sync_0.lpc" type="lpc" modified="2020 08 10 15:47:35.000"/>
+               <File name="serdes_sync_0.vhd" type="top_level_vhdl" modified="2020 08 10 15:47:35.000"/>
+  </Package>
+</DiamondModule>

diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd
index cdd207d45aec811292691081fc0e62a6fb589603..5a8cdca3474162bfc30fe726f8f42cbd22116fc8 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync.vhd
@@ -127,7 +127,7 @@ SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0';   --slave only swi
 -------------------------------------------------      
 -- Serdes
 -------------------------------------------------      
-gen_pcs0 : if SERDES_NUM = SERDES_NUM generate -- same entity in any case
+gen_pcs0 : if SERDES_NUM = 0 or SERDES_NUM = 1 generate -- same entity in any case
   THE_SERDES : entity work.pcs 
     port map(
       serdes_sync_0_hdinp            => hdinp,
@@ -184,7 +184,120 @@ gen_pcs0 : if SERDES_NUM = SERDES_NUM generate -- same entity in any case
       serdes_sync_0_rsl_tx_rdy           => tx_ready
       );
 end generate;
+-- gen_pcs1 : if SERDES_NUM = 1 generate
+--   THE_SERDES : entity work.pcs1
+--     port map(
+--       serdes_sync_0_hdinp            => hdinp,
+--       serdes_sync_0_hdinn            => hdinn,
+--       serdes_sync_0_hdoutp           => hdoutp,
+--       serdes_sync_0_hdoutn           => hdoutn,
+--       serdes_sync_0_rxrefclk         => CLK_INTERNAL_FULL,
+--       serdes_sync_0_rx_pclk          => clk_rx_full,
+--       serdes_sync_0_tx_pclk          => clk_tx_full,
+--       
+--       serdes_sync_0_txdata           => tx_data,
+--       serdes_sync_0_tx_k(0)          => tx_k,
+--       serdes_sync_0_tx_force_disp(0) => '0',
+--       serdes_sync_0_tx_disp_sel(0)   => '0',
+--       serdes_sync_0_rxdata           => rx_data,
+--       serdes_sync_0_rx_k(0)          => rx_k,
+--       serdes_sync_0_rx_disp_err(0)   => open,
+--       serdes_sync_0_rx_cv_err(0)     => rx_error,
+--       
+--       serdes_sync_0_tx_idle_c        => '0',
+--       serdes_sync_0_signal_detect_c  => '0', 
+--       serdes_sync_0_rx_los_low_s     => rx_los_low,
+--       serdes_sync_0_lsm_status_s     => lsm_status,
+--       serdes_sync_0_rx_cdr_lol_s     => rx_cdr_lol,
+--       serdes_sync_0_rx_pcs_rst_c     => rx_pcs_rst,
+--       serdes_sync_0_tx_pcs_rst_c     => tx_pcs_rst,
+--       serdes_sync_0_rx_serdes_rst_c  => rx_serdes_rst,
+-- 
+-- 
+--       serdes_sync_0_sci_wrdata           => sci_data_in_i,
+--       serdes_sync_0_sci_rddata           => sci_data_out_i,
+--       serdes_sync_0_sci_addr             => sci_addr_i,
+--       serdes_sync_0_sci_en_dual          => reset_n,
+--       serdes_sync_0_sci_sel_dual         => sci_ch_i(4),
+--       serdes_sync_0_sci_en               => reset_n,
+--       serdes_sync_0_sci_sel              => sci_ch_i(0),
+--       serdes_sync_0_sci_rd               => sci_read_i,
+--       serdes_sync_0_sci_wrn              => sci_write_i,
+--       serdes_sync_0_sci_int              => open,
+--       
+--       serdes_sync_0_cyawstn              => '0', --?
+--       serdes_sync_0_rst_dual_c           => rst_qd,
+--       serdes_sync_0_serdes_rst_dual_c    => '0',
+--       serdes_sync_0_tx_pwrup_c           => '1',
+--       serdes_sync_0_rx_pwrup_c           => '1',      
+--       serdes_sync_0_serdes_pdb           => '1', 
+--       serdes_sync_0_tx_serdes_rst_c      => tx_serdes_rst,
+-- 
+--       serdes_sync_0_pll_refclki          => CLK_REF_FULL,
+--       serdes_sync_0_pll_lol              => tx_pll_lol,
+--       serdes_sync_0_rsl_disable          => '1',
+--       serdes_sync_0_rsl_rst              => '0',
+--       serdes_sync_0_rsl_rx_rdy           => rx_ready,
+--       serdes_sync_0_rsl_tx_rdy           => tx_ready
+--       );
+-- end generate;
+gen_pcs2 : if SERDES_NUM = 2 generate
+  THE_SERDES : entity work.pcs2
+    port map(
+      serdes_sync_0_hdinp            => hdinp,
+      serdes_sync_0_hdinn            => hdinn,
+      serdes_sync_0_hdoutp           => hdoutp,
+      serdes_sync_0_hdoutn           => hdoutn,
+      serdes_sync_0_rxrefclk         => CLK_INTERNAL_FULL,
+      serdes_sync_0_rx_pclk          => clk_rx_full,
+      serdes_sync_0_tx_pclk          => clk_tx_full,
+      
+      serdes_sync_0_txdata           => tx_data,
+      serdes_sync_0_tx_k(0)          => tx_k,
+      serdes_sync_0_tx_force_disp(0) => '0',
+      serdes_sync_0_tx_disp_sel(0)   => '0',
+      serdes_sync_0_rxdata           => rx_data,
+      serdes_sync_0_rx_k(0)          => rx_k,
+      serdes_sync_0_rx_disp_err(0)   => open,
+      serdes_sync_0_rx_cv_err(0)     => rx_error,
+      
+      serdes_sync_0_tx_idle_c        => '0',
+      serdes_sync_0_signal_detect_c  => '0', 
+      serdes_sync_0_rx_los_low_s     => rx_los_low,
+      serdes_sync_0_lsm_status_s     => lsm_status,
+      serdes_sync_0_rx_cdr_lol_s     => rx_cdr_lol,
+      serdes_sync_0_rx_pcs_rst_c     => rx_pcs_rst,
+      serdes_sync_0_tx_pcs_rst_c     => tx_pcs_rst,
+      serdes_sync_0_rx_serdes_rst_c  => rx_serdes_rst,
+
 
+      serdes_sync_0_sci_wrdata           => sci_data_in_i,
+      serdes_sync_0_sci_rddata           => sci_data_out_i,
+      serdes_sync_0_sci_addr             => sci_addr_i,
+      serdes_sync_0_sci_en_dual          => reset_n,
+      serdes_sync_0_sci_sel_dual         => sci_ch_i(4),
+      serdes_sync_0_sci_en               => reset_n,
+      serdes_sync_0_sci_sel              => sci_ch_i(0),
+      serdes_sync_0_sci_rd               => sci_read_i,
+      serdes_sync_0_sci_wrn              => sci_write_i,
+      serdes_sync_0_sci_int              => open,
+      
+      serdes_sync_0_cyawstn              => '0', --?
+      serdes_sync_0_rst_dual_c           => rst_qd,
+      serdes_sync_0_serdes_rst_dual_c    => '0',
+      serdes_sync_0_tx_pwrup_c           => '1',
+      serdes_sync_0_rx_pwrup_c           => '1',      
+      serdes_sync_0_serdes_pdb           => '1', 
+      serdes_sync_0_tx_serdes_rst_c      => tx_serdes_rst,
+
+      serdes_sync_0_pll_refclki          => CLK_REF_FULL,
+      serdes_sync_0_pll_lol              => tx_pll_lol,
+      serdes_sync_0_rsl_disable          => '1',
+      serdes_sync_0_rsl_rst              => '0',
+      serdes_sync_0_rsl_rx_rdy           => rx_ready,
+      serdes_sync_0_rsl_tx_rdy           => tx_ready
+      );
+end generate;
     tx_serdes_rst <= '0';
     serdes_rst_qd <= '0';
 --    wa_position_sel <= x"0";