architecture trb_net_onewire_arch of trb_net_onewire is
constant MAX_COUNTER : integer := 2**17-1;
- type state_t is (IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_READ_ROM, READ_WAIT,
+ type state_t is (IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT,
WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
- READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, SEND_SKIP_ROM);
+ READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP);
signal state, next_state : state_t;
signal timecounter : integer range 0 to MAX_COUNTER;
signal bitcounter : integer range 0 to 127;
signal conv_temp, next_conv_temp : std_logic;
signal reading_temp, next_reading_temp : std_logic;
signal skip_rom, next_skip_rom : std_logic;
- signal buf_TEMP_OUT, temp_shift : std_logic_vector(11 downto 0);
+ signal buf_TEMP_OUT : std_logic_vector(11 downto 0);
begin
when WAIT_AFTER_RESET =>
if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then --1200
reset_timecounter <= '1';
- if send_rom = '1' then
- next_state <= SEND_READ_ROM;
- else
- next_skip_rom <= '1';
- next_state <= SEND_SKIP_ROM;
- end if;
+ next_state <= SEND_ROM_COMMAND;
end if;
--presence is not checked
--sending rom commands
- when SEND_READ_ROM =>
- next_send_bit <= not bitcounter_vector(1); --this is x33, lsb first
+ when SEND_ROM_COMMAND =>
+ next_skip_rom <= not send_rom and not bitcounter_vector(3);
inc_bitcounter <= '1';
- if bitcounter_vector(3) = '1' then --send 8 bit
- next_state <= READ_READ_ROM;
- reset_bitcounter <= '1';
+ next_state <= WRITE_START;
+
+ if send_rom = '1' then
+ next_send_bit <= not bitcounter_vector(1); --this is x33, lsb first
else
- next_state <= WRITE_START;
- end if;
+ next_send_bit <= bitcounter_vector(1); --this is xCC, lsb first
+ end if;
- when SEND_SKIP_ROM =>
- next_send_bit <= bitcounter_vector(1); --this is xCC, lsb first
- inc_bitcounter <= '1';
if bitcounter_vector(3) = '1' then --send 8 bit
- next_skip_rom <= '0';
- if conv_temp = '1' then
+ if send_rom = '1' then
+ next_state <= READ_READ_ROM;
+ elsif conv_temp = '1' then
next_state <= SEND_CONV_TEMP;
else
next_state <= SEND_READ_TEMP;
end if;
reset_bitcounter <= '1';
- else
- next_state <= WRITE_START;
end if;
+
--sending sensor commands
when SEND_CONV_TEMP =>
next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0);
end if;
when SEND_READ_TEMP =>
- next_send_bit <= (or_all(bitcounter_vector(2 downto 0)))
- and not((bitcounter_vector(2) and bitcounter_vector(1) and not bitcounter_vector(0)));
- --this is xBE, lsb first
+ if bitcounter_vector(2 downto 0) = "000" or bitcounter_vector(2 downto 0) = "110" then
+ next_send_bit <= '0'; --this is xBE, lsb first
+ else
+ next_send_bit <= '1';
+ end if;
inc_bitcounter <= '1';
if bitcounter_vector(3) = '1' then --send 8 bit
next_state <= READ_READ_TEMP;
next_state <= READ_BIT;
end if;
- when READ_READ_TEMP => --waiting for end of conversion
+ when READ_READ_TEMP =>
inc_bitcounter <= '1';
if bitcounter_vector(3 downto 2) = "11" then --read 12 bit
next_state <= IDLE;
when WRITE_WAIT =>
if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then
reset_timecounter <= '1';
- if send_rom = '1' then
- next_state <= SEND_READ_ROM;
- elsif skip_rom = '1' then
- next_state <= SEND_SKIP_ROM;
+ if send_rom = '1' or skip_rom = '1' then
+ next_state <= SEND_ROM_COMMAND;
+-- elsif skip_rom = '1' then
+-- next_state <= SEND_SKIP_ROM;
elsif conv_temp = '1' then
next_state <= SEND_CONV_TEMP;
elsif reading_temp = '1' then
end generate;
---saving received id data
+--saving received data
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- ram_wr <= '0';
- else
- ram_wr <= '0';
- if recv_bit_ready = '1' and send_rom = '1' then
- ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4));
- ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4));
- word(15 downto 1) <= word(14 downto 0);
- word(0) <= recv_bit;
- if bitcounter_vector(3 downto 0) = "0000" then
- ram_wr <= '1';
- end if;
+ ram_wr <= '0';
+ if recv_bit_ready = '1' and (send_rom = '1' or reading_temp = '1') then
+ ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4));
+ ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4));
+ word(14 downto 0) <= word(15 downto 1);
+ word(15) <= recv_bit;
+ if bitcounter_vector(3 downto 0) = "0000" and send_rom = '1' then
+ ram_wr <= '1';
+ end if;
+ if bitcounter_vector(3 downto 0) = "1100" and reading_temp = '1' then
+ buf_TEMP_OUT <= recv_bit & word(14 downto 4);
end if;
end if;
end if;
end process;
--saving temperature
- process(CLK)
- begin
- if rising_edge(CLK) then
- if recv_bit_ready = '1' and reading_temp = '1' then
- temp_shift(10 downto 0) <= temp_shift(11 downto 1);
- temp_shift(11) <= recv_bit;
- if bitcounter_vector(3 downto 0) = "1100" then
- buf_TEMP_OUT <= temp_shift;
- end if;
- end if;
- end if;
- end process;
+ -- process(CLK)
+ -- begin
+ -- if rising_edge(CLK) then
+ -- if recv_bit_ready = '1' and reading_temp = '1' then
+ -- temp_shift(10 downto 0) <= temp_shift(11 downto 1);
+ -- temp_shift(11) <= recv_bit;
+ -- if bitcounter_vector(3 downto 0) = "1100" then
+ -- buf_TEMP_OUT <= temp_shift;
+ -- end if;
+ -- end if;
+ -- end if;
+ -- end process;
ADDR_OUT <= ram_addr;
DATA_OUT <= word;
TEMP_OUT <= buf_TEMP_OUT;
+ STAT(0) <= '0';
STAT(1) <= input;
STAT(2) <= output;
STAT(3) <= send_rom;
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