coarse delay measurement added

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 323b46abe99432fb593c5038004dac63b6de92fd..c28c8aae67103d45baa6ab1e35dd5403ae58b49c 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -224,7 +224,9 @@ architecture trb3sc_arch of trb3sc_cts is
   attribute syn_preserve of bustc_rx    : signal is true;   
   
   signal tx_dlm_i                    : std_logic;
+  signal tx_dlm_q                    : std_logic;
   signal rx_dlm_i                    : std_logic;
+  signal rx_dlm_q                    : std_logic;
   
   signal destroy_link_i              : std_logic;
   signal enable_dlm_i                : std_logic;
@@ -284,11 +286,6 @@ architecture trb3sc_arch of trb3sc_cts is
   signal start_ping_q                : std_logic;
   signal start_pong_i                : std_logic;
   signal start_pong_q                : std_logic;
-  signal toggle_i                    : std_logic;
-  signal toggle_q                    : std_logic;
-  signal tristate_pings_i            : std_logic;
-  signal cal_pulse_i                 : std_logic;
-  signal cal_pulse_q                 : std_logic_vector(1 downto 0);
   signal fsm_active_int              : std_logic;
   signal fsm_ce_int                  : std_logic;
   signal fsm_rst_int                 : std_logic;
@@ -299,6 +296,10 @@ architecture trb3sc_arch of trb3sc_cts is
   signal ack_delay_x                 : std_logic;
   signal phaser_start                : std_logic;
 
+  signal coarse_delay_data           : std_logic_vector(31 downto 0);
+
+  signal cal_phase_q                 : std_logic;
+  
 begin
 
   THE_TIME_COUNTER_PROC: process( clk_full_osc )
@@ -483,7 +484,6 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
   send_dlm_word_i  <= std_logic_vector(dlm_tag_ctr);
   enable_dlm_i     <= test_reg(31); -- ONLY FOR TESTING
   send_rst_i       <= test_reg(30); -- ONLY FOR TESTING
-  tristate_pings_i <= test_reg(25); -- ONLY FOR TESTING
   destroy_link_i   <= test_reg(24); -- ONLY FOR TESTING
   phaser_start     <= test_reg(16); -- ONLY FOR TESTING
   send_rst_word_i  <= test_reg(15 downto 8); -- ONLY FOR TESTING
@@ -573,13 +573,13 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
   port map(
     AUXCLK           => clk_sample,
     RESET            => reset_i,
-    PING_IN          => ping_i, --HDR_IO(1),
-    PONG_IN          => pong_i, --HDR_IO(3),
+    PING_IN          => ping_i,
+    PONG_IN          => pong_i,
     PING_OUT         => ping_stretched_i,
     PONG_OUT         => pong_stretched_i,
     START_PING_OUT   => start_ping_i,
     START_PONG_OUT   => start_pong_i,
-    TOGGLE_OUT       => toggle_i,
+    TOGGLE_OUT       => open,
     DELAY_VALUE_OUT  => delay_value_int,
     DELAY_VALID_OUT  => delay_valid_int,
     FSM_ACTIVE_IN    => fsm_active_int,
@@ -588,10 +588,16 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     FSM_CLR_DONE_OUT => fsm_clr_done_int
   );
 
+  cal_phase_q <= (ping_i xor pong_i) when rising_edge(master_clk_i);
+  
   THE_STATISTICS: entity statistics 
   port map( 
     AUXCLK           => clk_sample,
     RESET            => reset_i,
+    DELAY_CLK        => master_clk_i,
+    DELAY_START_IN   => tx_dlm_i,
+    DELAY_STOP_IN    => rx_dlm_i,
+    DELAY_COARSE_OUT => coarse_delay_data, -- BUG
     DELAY_VALUE_IN   => delay_value_int,
     DELAY_VALID_IN   => delay_valid_int,
     FSM_START_IN     => phaser_start,
@@ -622,16 +628,25 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
   busddmtd_tx.nack    <= '0';
   busddmtd_tx.unknown <= '0';
 
-  THE_CAL_CLOCK_PROC: process( master_clk_i, reset_i ) 
-  begin
-    if   ( reset_i = '1' ) then
-      cal_pulse_i <= '0';
-    elsif( rising_edge(master_clk_i) ) then
-      cal_pulse_i <= not cal_pulse_i;
-    end if;
-  end process THE_CAL_CLOCK_PROC;
-  
   -- Output registers
+  THE_TX_DLM_OR: OFS1P3DX
+  port map(
+    SP    => '1',
+    CD    => '0',
+    SCLK  => master_clk_i,
+    D     => tx_dlm_i,
+    Q     => tx_dlm_q
+  );
+
+  THE_RX_DLM_OR: OFS1P3DX
+  port map(
+    SP    => '1',
+    CD    => '0',
+    SCLK  => pong_clk_i,
+    D     => rx_dlm_i,
+    Q     => rx_dlm_q
+  );
+
   THE_PING_OR: OFS1P3DX
   port map(
     SP    => '1',
@@ -686,44 +701,17 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     Q     => start_pong_q
   );
 
-  THE_REF_CLK_1_OR: OFS1P3DX
-  port map(
-    SP    => '1',
-    CD    => '0',
-    SCLK  => master_clk_i,
-    D     => cal_pulse_i,
-    Q     => cal_pulse_q(1)
-  );
-
-  THE_REF_CLK_0_OR: OFS1P3DX
-  port map(
-    SP    => '1',
-    CD    => '0',
-    SCLK  => master_clk_i,
-    D     => cal_pulse_i,
-    Q     => cal_pulse_q(0)
-  );
-
-  THE_TOGGLE_OR: OFS1P3DX
-  port map(
-    SP    => '1',
-    CD    => '0',
-    SCLK  => clk_sample,
-    D     => toggle_i,
-    Q     => toggle_q
-  );
-
-HDR_IO(1)  <= ping_q when (tristate_pings_i = '0') else 'Z';
-HDR_IO(3)  <= pong_q when (tristate_pings_i = '0') else 'Z';
+HDR_IO(1)  <= ping_q;
+HDR_IO(3)  <= pong_q;
 HDR_IO(5)  <= ping_stretched_q;
 HDR_IO(7)  <= pong_stretched_q;
 HDR_IO(9)  <= '0';
 
-HDR_IO(2)  <= '0'; --cal_pulse_q(0) when (tristate_pings_i = '1') else 'Z';
-HDR_IO(4)  <= '0'; --cal_pulse_q(1) when (tristate_pings_i = '1') else 'Z';
+HDR_IO(2)  <= tx_dlm_q;
+HDR_IO(4)  <= rx_dlm_q;
 HDR_IO(6)  <= start_ping_q;
 HDR_IO(8)  <= start_pong_q;
-HDR_IO(10) <= toggle_q;
+HDR_IO(10) <= '0';
 --------------------------------------------------------------------------------------------------------
 --------------------------------------------------------------------------------------------------------
 
@@ -732,16 +720,16 @@ end generate;
 ---------------------------------------------------------------------------
 -- PCSC: not used
 ---------------------------------------------------------------------------    
-  bussci3_tx.data    <= (others => '0');
-  bussci3_tx.ack     <= '0';
-  bussci3_tx.nack    <= '0';
-  bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+--  bussci3_tx.data    <= (others => '0');
+--  bussci3_tx.ack     <= '0';
+--  bussci3_tx.nack    <= '0';
+--  bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
 
 -- can be used for simple readback on debugging
---  bussci3_tx.data    <= phaser_data;
---  bussci3_tx.ack     <= ack_delay(2); --bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
---  bussci3_tx.nack    <= '0';
---  bussci3_tx.unknown <= '0';
+  bussci3_tx.data    <= cal_phase_q & coarse_delay_data(30 downto 0);
+  bussci3_tx.ack     <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+  bussci3_tx.nack    <= '0';
+  bussci3_tx.unknown <= '0';
 
 ---------------------------------------------------------------------------
 -- PCSD: GbE
@@ -1225,8 +1213,8 @@ end generate;
     REFOUT <= (others => cts_trigger_out);
   end generate;
   
-  RJ_IO(0)                           <= tx_dlm_i; --cts_trigger_out;
-  RJ_IO(1)                           <= rx_dlm_i;
+  RJ_IO(0)                           <= '0'; --tx_dlm_i; --cts_trigger_out;
+  RJ_IO(1)                           <= '0'; --rx_dlm_i;
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------