corrected constraint name

diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf
index 785d3858b1c342de450610c3c306a159a7c61894..0d17389798b1c890e95bfb51a74f7dc4811e6f09 100644 (file)
--- a/pinout/basic_constraints.lpf
+++ b/pinout/basic_constraints.lpf
@@ -23,7 +23,7 @@ FREQUENCY PORT CLK_EXT_PLL_RIGHT    200 MHz;
 
 
 #If these signals do not exist, somebody messed around with the design...
-MULTICYCLE TO CELL   "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns;
+MULTICYCLE TO CELL   "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio[*]" 20 ns;
 MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns;
 MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns;
 MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
@@ -59,4 +59,4 @@ BLOCK PATH FROM PORT "TEMPSENS";
 BLOCK PATH TO   PORT "TESTLINE";
 
 PROHIBIT PRIMARY   NET "ENPIRION_CLOCK_c" ;
-PROHIBIT SECONDARY NET "ENPIRION_CLOCK_c" ;
\ No newline at end of file
+PROHIBIT SECONDARY NET "ENPIRION_CLOCK_c" ;