next_A_AOD <= '0';
next_TDC_SETTING_LOADED_OUT <= '0';
up_counter_i <= '0';
- A_ADD(8 downto 0) <= send_data(8 downto 0);
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+
if time_counter = time_limit then
clear_time_counter <= '1';
next_state <= write_address_strobe;
when idle_state =>
next_debug_register <= x"00";
-- hex 00
- next_GDE <= '0';
- next_MODD <= '0';
- next_RES <= '0';
- next_TOK <= '0';
- next_WRM <= '0';
- next_RDM <= '0';
+ next_GDE <= '0';
+ next_MODD <= '0';
+ next_RES <= '0';
+ next_TOK <= '0';
+ next_WRM <= '0';
+ next_RDM <= '0';
clear_time_counter <= '1';
if MODE_TRIGGER = '1' then
next_state <= reset_mode_state;
A_RDO_OUT : out std_logic; --ready FROM first motherboard
ROC1_WRITTEN_OUT : out std_logic;
- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0);
DIRECTION_DATA_LINE_OUT : out std_logic_vector(3 downto 0);
MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------
D : out std_logic_vector(6 downto 0);
A_RDO_OUT : out std_logic;
ROC1_WRITTEN_OUT : out std_logic;
- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0);
DIRECTION_DATA_LINE_OUT : out std_logic_vector(3 downto 0);
MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0);
ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0);
DATA_VALID_OUT : out std_logic;
FULL_FIFO_IN : in std_logic;
INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0);
- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); --x"0"debug,
+ DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0); --x"0"debug,
--x"1" 2 hit in one word
DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
end component;
PULSE_OUT : out std_logic);
end component;
+component oddParityGen
+ generic (width : integer);
+ port (
+ CLK : in std_logic;
+ ad : in std_logic_vector(7 downto 0);
+ oddParity : out std_logic);
+end component;
+
+-- component xor2test
+-- port (
+-- CLK : in STD_LOGIC;
+-- A_IN : in STD_LOGIC;
+-- B_IN : in STD_LOGIC;
+-- Y_OUT : out STD_LOGIC);
+-- end component;
+component xor2test
+ port (
+ Clock : in std_logic;
+ L, w : in std_logic;
+ Output : out std_logic_vector(3 downto 0);
+ Input : in std_logic_vector( 3 downto 0));
+end component;
+
end package mdc_oepb_pack;
when idle_state =>
next_DEBUG_REGISTER <= "0000";
- --hex 64 + GDE
+ --hex 64 + GDE
next_A_MOD <= '0';
next_A_RES <= '1';
next_A_TOK <= '0';
if TRIGGER_TYPE = x"1" then
next_state <= wait_state;
else
- next_state <= idle_state;
+ next_state <= idle_state;
end if;
when wait_state =>
next_state <= send_token_state;
else
next_state <= wait_state_1;
- end if;
+ end if;
+
-------------------------------------------------------------------------------
-- token width
-------------------------------------------------------------------------------
next_A_WRM <= '1';
next_A_RDM <= '1';
next_A_GDE <= '1';
--- if (A_RDO = '1' and counter_for_token < x"000fffff") then
--- next_state <= token_is_back_state;
--- elsif (A_RDO = '0' and counter_for_token >= x"000fffff") then
--- next_state <= token_not_back_state;
--- else
--- next_state <= wait_token_back_state;
--- end if;
if A_RDO = '1' then
- -- next_TOKEN_BACK_OUT <= '1';
next_state <= token_is_back_state;
- -- next_state <= idle_state;
else
next_state <= wait_token_back_state;
end if;
INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); --from common stop generator
--x"0"debug, x"1" 2 hit in one word, x"2" test data,
- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0);
DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
end tdc_readout;
signal clear_counter_check_hit,up_counter_check_hit : STD_LOGIC;
signal counter_check_hit : std_logic_vector(3 downto 0);
signal reg_data_type_select_in : std_logic_vector(3 downto 0);
-signal reg_test_data_maximun_word_number : std_logic_vector(15 downto 0);
+signal reg_test_data_maximun_word_number : std_logic_vector(11 downto 0);
signal clear_counter_check_hit_calibration,up_counter_check_hit_calibration : STD_LOGIC;
signal counter_check_hit_calibration : std_logic_vector(3 downto 0);
signal clear_saved_data_new_format_hit_0_1_cal : std_logic;
reg_test_data_maximun_word_number <= (others => '0');
else
reg_data_type_select_in <= DATA_TYPE_SELECT_IN(3 downto 0);
- reg_test_data_maximun_word_number <= DATA_TYPE_SELECT_IN(19 downto 4);
+ reg_test_data_maximun_word_number <= DATA_TYPE_SELECT_IN(15 downto 4);
end if;
end if;
end process;
when idle_state_test_data =>
next_debug_register_test_data <= x"0";
- next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
+ next_data_bus_out_test_data(11 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
if (INIT_TDC_READOUT_IN = x"1") then
next_state_test_data <= send_data_with_valid_test_data;
else
next_debug_register_test_data <= x"1";
up_counter_test_data <= '1';
next_data_valid_out_test_data <= '1';
- next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
+ next_data_bus_out_test_data(11 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
next_state_test_data <= send_data_with_valid_next_test_data;
when send_data_with_valid_next_test_data =>
next_debug_register_test_data <= x"2";
next_data_valid_out_test_data <= '0';
- next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
+ next_data_bus_out_test_data(11 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
next_state_test_data <= check_dataword_number_test_data;
when check_dataword_number_test_data =>
next_debug_register_test_data <= x"3";
next_data_valid_out_test_data <= '0';
- next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
+ next_data_bus_out_test_data(11 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
if (conv_integer(counter_test_data) >= reg_test_data_maximun_word_number) then
next_state_test_data <= send_token_state_test_data;
else
next_debug_register_test_data <= x"4";
next_token_tdc_readout_i_test_data <= x"1";
clear_counter_test_data <= '1';
- next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
+ next_data_bus_out_test_data(11 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
next_state_test_data <= idle_state_test_data;
when others =>
-------------------------------------------------------------------------------
-- tdc_readout_and_trb_interface
-------------------------------------------------------------------------------
- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0);
TOKEN_TO_TRB_OUT : out std_logic;
REINIT_ROC1_IN : in std_logic;
REINIT_ROC1_OUT : out std_logic;
signal reg_calibration_trigger, next_calibration_trigger : std_logic;
signal reg_cal1_written, next_cal1_written : std_logic;
signal test_signal_i, reg_test_signal_i : std_logic;
-
+ signal keep_roc1_written_i : std_logic;
+ signal mb_not_initialized : std_logic;
+ signal reset_or_mb_not_initialized : std_logic;
+
--constant declarations
constant width : integer := 5;
constant width_token : integer := 5;
-------------------------------------------------------------------------------
u4 : mode_line_multiplexer
port map (
- --CLK : in std_logic; --for testing
- --mode lines input from trigger_begrun
+ --mode lines input from trigger_begrun
CLK => CLK,
A_MOD_TB => A_MOD_TB_i,
A_RES_TB => A_RES_TB_i,
-- map send_token_to_mb
-------------------------------------------------------------------------------
u5 : send_token_to_mb
- generic map (--width_token => 5,
- width => 5)
+ generic map (width => 5)
port map (
CLK => CLK,
- RESET => reset_i,
+ RESET => reset_or_mb_not_initialized, --reset_i,
TRIGGER_TYPE => trigger_type_send_token,--trigger_type,
A_MOD => A_MOD_ST_i,
A_RES => A_RES_ST_i,
STOP_READOUT_OUT => STOP_READOUT_OUT,
DEBUG_REGISTER => DEBUG_REGISTER(16 downto 13)
);
+
+ reset_or_mb_not_initialized <= reset_i or mb_not_initialized;
+
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if(RESET = '1') then
+ mb_not_initialized <= '0';
+ keep_roc1_written_i <= '0';
+ elsif (roc1_written_i = '1' or keep_roc1_written_i = '1') then
+ mb_not_initialized <= '0';
+ keep_roc1_written_i <= '1';
+ else
+ mb_not_initialized <= '1';
+ end if;
+ end if;
+ end process;
-------------------------------------------------------------------------------
--the state machine check which kind of trigger arrives. Depending on the
--trigger,this activates different states: when the beginrun trigger comes the
jspc29 / mdcoep.git / commitdiff