TDC removed, PAR changed

diff --git a/template/compile.pl b/template/compile.pl
index 933ff60e0f11ce91609a877af1352c5888dd6f93..8a19aa687e9ce69f56c9c1ed9bf6f366dcc1b061 120000 (symlink)
--- a/template/compile.pl
+++ b/template/compile.pl
@@ -1 +1 @@
-../../trb3/scripts/compile.pl
\ No newline at end of file
+../../trb3sc/scripts/compile.pl
\ No newline at end of file

diff --git a/template/par.p2t b/template/par.p2t
index 722b6fea38ac0e2a441952b9516efafd0bf067c5..cfeb9c515cfa03cd529c9974a4980a9a96cd4d1a 100644 (file)
--- a/template/par.p2t
+++ b/template/par.p2t
@@ -1,7 +1,7 @@
 -w
 -l 5
 -s 10
--t 11 # seed setting here!
+-t 13 # seed setting here!
 -c 2
 -e 2
 -i 10

diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd
index 30fd2ab4ee7a1efbf534bb0e26c2d65763958b6d..87a6ed13fb06403cfac2dcf92b103556ffbdae93 100644 (file)
--- a/template/trb5sc_template.vhd
+++ b/template/trb5sc_template.vhd
@@ -28,9 +28,6 @@ entity trb5sc_template is
     SFP_MOD_0  : in  std_logic;
     
     --AddOn
---     FE_GPIO    : inout std_logic_vector(11 downto 0);
---     FE_CLK     : out   std_logic_vector( 2 downto 1);
---     FE_DIFF    : inout std_logic_vector(63 downto 0);
     INP : in std_logic_vector(63 downto 0);
 
     CS    : out std_logic_vector(4 downto 1);
@@ -141,7 +138,9 @@ architecture arch of trb5sc_template is
   signal link_tx_ready_i             : std_logic;
   signal debug_i                     : std_logic_vector(31 downto 0);
   signal tx_fsm_state                : std_logic_vector(3 downto 0);
-  
+  signal rx_dlm_word_i               : std_logic_vector(7 downto 0);
+  signal rx_dlm_i                    : std_logic;
+
 begin
 
 trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);
@@ -198,8 +197,8 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
       MEDIA_MED2INT      => med2int(0),
       MEDIA_INT2MED      => int2med(0),
       -- komma operation
-      RX_DLM_OUT         => open,
-      RX_DLM_WORD_OUT    => open,
+      RX_DLM_OUT         => rx_dlm_i, --open,
+      RX_DLM_WORD_OUT    => rx_dlm_word_i, --open,
       TX_DLM_IN          => '0',
       TX_DLM_WORD_IN     => x"00",
       RX_RST_OUT         => open,
@@ -263,8 +262,10 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
     BACK_GPIO(0) <= sfp_txdis_i;
   end generate;  
 
+  LED_EXT_CLOCK  <= not std_logic(rx_dlm_word_i(7));
+  
   HDR_IO(15 downto 12) <= tx_fsm_state;
-  HDR_IO(11)           <= init_quad;
+  HDR_IO(11)           <= rx_dlm_i;
   HDR_IO(10)           <= clear_i;
   HDR_IO(9)            <= tx_clk_avail_i;
   HDR_IO(8)            <= tx_pll_lol_dual_a;
@@ -443,43 +444,42 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
 --  LED            <= x"F0";
   LED_RJ_GREEN   <= "00";
   LED_RJ_RED     <= "11";
-  LED_EXT_CLOCK  <= IN_SELECT_EXT_CLOCK or led_off;
+--  LED_EXT_CLOCK  <= IN_SELECT_EXT_CLOCK or led_off;
   
 -------------------------------------------------------------------------------
 -- TDC
 -------------------------------------------------------------------------------
-  THE_TDC : entity work.TDC_record
-    generic map (
-      CHANNEL_NUMBER => NUM_TDC_CHANNELS,
-      STATUS_REG_NR  => 21,
-      DEBUG          => c_NO,
-      SIMULATION     => c_NO
-    )
-    port map (
-      RESET              => reset_i,
-      CLK_TDC            => clk_full,
-      CLK_READOUT        => clk_sys,
-      REFERENCE_TIME     => trigger_in_i,
-      HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),
-      HIT_CAL_IN         => clk_cal,
-      -- Trigger signals from handler
-      BUSRDO_RX          => readout_rx,
-      BUSRDO_TX          => readout_tx(0),
-      -- Slow control bus
-      BUS_RX             => bustdc_rx,
-      BUS_TX             => bustdc_tx,
-      -- Dubug signals
-      INFO_IN            => timer,
-      LOGIC_ANALYSER_OUT => open
-    );
-
+--  THE_TDC : entity work.TDC_record
+--    generic map (
+--      CHANNEL_NUMBER => NUM_TDC_CHANNELS,
+--      STATUS_REG_NR  => 21,
+--      DEBUG          => c_NO,
+--      SIMULATION     => c_NO
+--    )
+--    port map (
+--      RESET              => reset_i,
+--      CLK_TDC            => clk_full,
+--      CLK_READOUT        => clk_sys,
+--      REFERENCE_TIME     => trigger_in_i,
+--      HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),
+--      HIT_CAL_IN         => clk_cal,
+--      -- Trigger signals from handler
+--      BUSRDO_RX          => readout_rx,
+--      BUSRDO_TX          => readout_tx(0),
+--      -- Slow control bus
+--      BUS_RX             => bustdc_rx,
+--      BUS_TX             => bustdc_tx,
+--      -- Dubug signals
+--      INFO_IN            => timer,
+--      LOGIC_ANALYSER_OUT => open
+--    );
 
 -------------------------------------------------------------------------------
 -- No trigger/data endpoint included
 -------------------------------------------------------------------------------
---  readout_tx(0).data_finished <= '1';
---  readout_tx(0).data_write    <= '0';
---  readout_tx(0).busy_release  <= '1';    
+  readout_tx(0).data_finished <= '1';
+  readout_tx(0).data_write    <= '0';
+  readout_tx(0).busy_release  <= '1';    
   
 end architecture;