changed delay measurement time

diff --git a/special/phaser.vhd b/special/phaser.vhd
index 936fd2e8e40dfb6f8264f6609d0e37dfc0dcdd06..a1c8ae47cfbf42a4a033c4902ccfc4b1247059e2 100644 (file)
--- a/special/phaser.vhd
+++ b/special/phaser.vhd
@@ -26,14 +26,14 @@ architecture arch of phaser is
 -- state machine signals\r
 \r
 -- Signals\r
-  signal hi_cnt         : unsigned(20 downto 0);\r
-  signal cyc_cnt        : unsigned(20 downto 0);\r
+  signal hi_cnt         : unsigned(19 downto 0);\r
+  signal cyc_cnt        : unsigned(19 downto 0);\r
   signal update         : std_logic;\r
   signal cyc_done_x     : std_logic;\r
   signal cyc_done       : std_logic;\r
   signal phase_x        : std_logic;\r
   signal phase          : std_logic;\r
-  signal hi_cnt_int     : std_logic_vector(20 downto 0);\r
+  signal hi_cnt_int     : std_logic_vector(19 downto 0);\r
 \r
   signal coarse_counter : unsigned(11 downto 0);\r
   signal coarse_delay   : std_logic_vector(11 downto 0);\r
@@ -87,7 +87,7 @@ begin
     end if;\r
   end process THE_CYC_CNT_PROC;\r
 \r
-  cyc_done_x <= '1' when (cyc_cnt = x"fffffc") else '0';\r
+  cyc_done_x <= '1' when (cyc_cnt = x"ffffc") else '0';\r
 \r
   -- high signal count\r
   THE_HI_CNT_PROC: process( SAMPLE_CLK, RESET )\r