);
end generate;
- GEN_DUMMY_FIFO_TO_APL: if FIFO_TO_APL_DEPTH = 0 generate
- FIFO_TO_APL: trb_net16_dummy_fifo
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_apl_data_in,
- PACKET_NUM_IN => fifo_to_apl_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_apl_write,
- DATA_OUT => next_fifo_to_apl_data_out,
- PACKET_NUM_OUT => next_fifo_to_apl_packet_num_out,
- READ_ENABLE_IN => fifo_to_apl_read,
- FULL_OUT => fifo_to_apl_full,
- EMPTY_OUT => next_fifo_to_apl_empty
- );
- end generate;
+-- GEN_DUMMY_FIFO_TO_APL: if FIFO_TO_APL_DEPTH = 0 generate
+-- FIFO_TO_APL: trb_net16_dummy_fifo
+-- port map (
+-- CLK => CLK,
+-- RESET => RESET,
+-- CLK_EN => CLK_EN,
+-- DATA_IN => fifo_to_apl_data_in,
+-- PACKET_NUM_IN => fifo_to_apl_packet_num_in,
+-- WRITE_ENABLE_IN => fifo_to_apl_write,
+-- DATA_OUT => next_fifo_to_apl_data_out,
+-- PACKET_NUM_OUT => next_fifo_to_apl_packet_num_out,
+-- READ_ENABLE_IN => fifo_to_apl_read,
+-- FULL_OUT => fifo_to_apl_full,
+-- EMPTY_OUT => next_fifo_to_apl_empty
+-- );
+-- end generate;
---------------------------------------
-- keep track of fifo to apl read operations
CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high
-- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (31 downto 0); --data from FEE
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0); --data from FEE
FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid
FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready
FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again
USE_VENDOR_CORES => c_YES,
SECURE_MODE_TO_APL => c_YES,
SECURE_MODE_TO_INT => c_YES,
- APL_WRITE_ALL_WORDS=> c_YES,
+ APL_WRITE_ALL_WORDS=> c_NO,
BROADCAST_BITMASK => x"FF"
)
port map (
APL_FEE_SEND_IN <= cts_start_readout_rising;
APL_FEE_READ_IN <= FEE_READ_IN;
+
+ FEE_DATAREADY_OUT <= APL_FEE_DATAREADY_OUT when APL_FEE_TYP_OUT = TYP_DAT else '0';
+ FEE_DATA_OUT <= APL_FEE_DATA_OUT;
FEE_BUSY_OUT <= APL_FEE_RUN_OUT;
APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= buf_CTS_NUMBER_OUT;
end if;
end process;
- PROC_IPU_DATA : process(CLK)
- begin
- if rising_edge(CLK) then
- if FEE_READ_IN = '1' then
- FEE_DATAREADY_OUT <= '0';
- end if;
- if APL_FEE_READ_IN = '1' and APL_FEE_DATAREADY_OUT = '1' and APL_FEE_TYP_OUT = TYPE_DAT then
- if APL_FEE_PACKET_NUM_OUT = c_F0 or APL_FEE_PACKET_NUM_OUT = c_F2 then
- FEE_DATA_OUT(31 downto 16) <= APL_FEE_DATA_OUT;
- elsif APL_FEE_PACKET_NUM_OUT = c_F1 or APL_FEE_PACKET_NUM_OUT = c_F3 then
- FEE_DATA_OUT(15 downto 0) <= APL_FEE_DATA_OUT;
- FEE_DATAREADY_OUT <= '1';
- end if;
- end if;
- end if;
- end process;
+-- PROC_IPU_DATA : process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if FEE_READ_IN = '1' then
+-- FEE_DATAREADY_OUT <= '0';
+-- end if;
+-- if APL_FEE_READ_IN = '1' and APL_FEE_DATAREADY_OUT = '1' and APL_FEE_TYP_OUT = TYPE_DAT then
+-- if APL_FEE_PACKET_NUM_OUT = c_F0 or APL_FEE_PACKET_NUM_OUT = c_F2 then
+-- FEE_DATA_OUT(31 downto 16) <= APL_FEE_DATA_OUT;
+-- elsif APL_FEE_PACKET_NUM_OUT = c_F1 or APL_FEE_PACKET_NUM_OUT = c_F3 then
+-- FEE_DATA_OUT(15 downto 0) <= APL_FEE_DATA_OUT;
+-- FEE_DATAREADY_OUT <= '1';
+-- end if;
+-- end if;
+-- end if;
+-- end process;
STAT_REGS : out std_logic_vector (16*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
-
--Debugging registers
STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal HUB_CTRL_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal HUB_CTRL_media_interfaces_off: std_logic_vector (31 downto 0);
- signal HUB_CTRL_TIMEOUT_TIME : std_logic_vector (15 downto 0);
+ signal HUB_CTRL_TIMEOUT_TIME : std_logic_vector (31 downto 0);
signal HUB_ADDRESS : std_logic_vector (15 downto 0);
signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0);
signal global_time : std_logic_vector(31 downto 0);
signal local_time : std_logic_vector(7 downto 0);
+ signal timer_ms_tick : std_logic;
signal timer_us_tick : std_logic;
signal stat_ipu_fsm : std_logic_vector(15 downto 0);
STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32),
STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32),
CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32),
+ CTRL_OBUF_settings( 3 downto 0) => HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
+ CTRL_OBUF_settings(15 downto 4) => (others => '0'),
+ CTRL_OBUF_settings(19 downto 16) => HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
+ CTRL_OBUF_settings(31 downto 20) => (others => '0'),
STAT_INIT_OBUF_DEBUG => IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32),
- STAT_REPLY_OBUF_DEBUG => IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32)
+ STAT_REPLY_OBUF_DEBUG => IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32),
+ TIMER_TICKS_IN(0) => timer_us_tick,
+ TIMER_TICKS_IN(1) => timer_ms_tick
);
end generate;
gen_trmbuf: if HUB_USED_CHANNELS(k) = 0 generate
STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
- CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
+ CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32),
+ CTRL_TIMER_TICK(0) => timer_us_tick,
+ CTRL_TIMER_TICK(1) => timer_ms_tick
);
end generate;
gen_select_logic2 : if i = c_IPU_CHANNEL generate
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
STAT_FSM => stat_ipu_fsm,
CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
- CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
+ CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32),
+ CTRL_TIMER_TICK(0) => timer_us_tick,
+ CTRL_TIMER_TICK(1) => timer_ms_tick
);
buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
end generate;
GLOBAL_TIME => global_time,
LOCAL_TIME => local_time,
TIME_SINCE_LAST_TRG => open,
+ TIMER_MS_TICK => timer_ms_tick,
TIMER_US_TICK => timer_us_tick,
REGISTERS_IN => HC_STAT_REGS,
REGISTERS_OUT => HC_CTRL_REGS,
if rising_edge(CLK) then
for i in 0 to 2**(c_MUX_WIDTH-1)-1 loop
if HUB_locked(i) = '0' then
- HUB_CTRL_activepoints(i*32+31 downto i*32) <= HC_CTRL_REGS(i*32+31 downto i*32);
+ HUB_CTRL_activepoints(i*32+31 downto i*32) <= HC_CTRL_REGS(i*32+31 downto i*32) and not HC_STAT_ack_waiting(i*32+31 downto i*32);
+ else
+ HUB_CTRL_activepoints(i*32+31 downto i*32) <= HUB_CTRL_activepoints(i*32+31 downto i*32) and not HC_STAT_ack_waiting(i*32+31 downto i*32);
end if;
end loop;
end if;
end process;
gen_ack_waiting : for i in 0 to MII_NUMBER-1 generate
- HC_STAT_ack_waiting(i) <= IOBUF_STAT_INIT_OBUF_DEBUG((2*MII_NUMBER+i)*32+19);
- HC_STAT_ack_waiting(32+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((1*MII_NUMBER+i)*32+19);
- HC_STAT_ack_waiting(64+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((2*MII_NUMBER+i)*32+19);
- HC_STAT_ack_waiting(96+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((3*MII_NUMBER+i)*32+19);
+ HC_STAT_ack_waiting(i) <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+0)*32+20);
+ HC_STAT_ack_waiting(32+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+1)*32+20);
+ HC_STAT_ack_waiting(64+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+2)*32+20);
+ HC_STAT_ack_waiting(96+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+3)*32+20);
end generate;
+ HC_STAT_ack_waiting( 0+31 downto 0+MII_NUMBER) <= (others => '0');
+ HC_STAT_ack_waiting(32+31 downto 32+MII_NUMBER) <= (others => '0');
+ HC_STAT_ack_waiting(64+31 downto 64+MII_NUMBER) <= (others => '0');
+ HC_STAT_ack_waiting(96+31 downto 96+MII_NUMBER) <= (others => '0');
+
+
---------------------------------------------------------------------
--Debugging Signals
MY_ADDRESS_OUT <= HUB_ADDRESS;
STAT_REGS <= HC_STAT_REGS;
STAT_CTRL_REGS <= HC_CTRL_REGS(255 downto 0);
- HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+15 downto 5*32);
+ HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32);
HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
STAT_DEBUG <= buf_STAT_DEBUG;
HUB_STAT_GEN <= (others => '0');
CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);
FEE_DATAREADY_OUT : out std_logic;
FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
- CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
+ CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1');
+ CTRL_TIMER_TICK : in std_logic_vector (1 downto 0)
);
end component;
REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
STAT : out std_logic_vector (15 downto 0);
- STAT_locked : out std_logic;
+ STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
- STAT_TIMEOUT : out std_logic_vector (31 downto 0);
+ STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
- CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
- CTRL_activepoints : in std_logic_vector (31 downto 0)
+ CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
+ CTRL_activepoints : in std_logic_vector (31 downto 0);
+ CTRL_TIMER_TICK : in std_logic_vector (1 downto 0)
);
end component;
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
- CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
+ CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1');
+ CTRL_TIMER_TICK : in std_logic_vector (1 downto 0)
);
end entity;
signal enable_packing : std_logic;
- type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(31 downto 0);
+ type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(15 downto 0);
signal timeout_counter : timeout_counter_t;
signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0);
signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0);
signal timeout_found : std_logic;
+ signal reg_CTRL_TIMEOUT_TIME : std_logic_vector(3 downto 0);
+
+ signal timer_us_tick : std_logic;
+ signal timer_ms_tick : std_logic;
signal saved_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
signal last_REPLY_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*3-1 downto 0);
end generate;
+ reg_timer_ticks : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ timer_us_tick <= CTRL_TIMER_TICK(0);
+ timer_ms_tick <= CTRL_TIMER_TICK(1);
+ end if;
+ end process;
----------------------------------
--Check for Timeouts
begin
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
+ reg_CTRL_TIMEOUT_TIME <= CTRL_TIMEOUT_TIME;
timeout_found <= or_all(connection_timed_out);
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or CTRL_TIMEOUT_TIME = x"0" then
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then
timeout_counter(i) <= (others => '0');
- elsif timeout_counter(i)(to_integer(unsigned('0'&CTRL_TIMEOUT_TIME)+to_unsigned(16,5))) = '1' then
+ elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'0'))) = '1' then
connection_timed_out(i) <= '1';
- else
+ elsif timer_ms_tick = '1' then
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
end if;
end if;
STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
- CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
+ CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1');
+ CTRL_TIMER_TICK : in std_logic_vector (1 downto 0)
);
end entity;
signal register_buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0');
- type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(31 downto 0);
+ type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(15 downto 0);
signal timeout_counter : timeout_counter_t;
signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0);
signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0);
signal timeout_found : std_logic;
+ signal reg_CTRL_TIMEOUT_TIME : std_logic_vector(3 downto 0);
+
+ signal timer_us_tick : std_logic;
+ signal timer_ms_tick : std_logic;
begin
end process;
+
+ reg_timer_ticks : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ timer_us_tick <= CTRL_TIMER_TICK(0);
+ timer_ms_tick <= CTRL_TIMER_TICK(1);
+ end if;
+ end process;
+
----------------------------------
--Check for Timeouts
----------------------------------
proc_timeout_counters : process (CLK)
begin
if rising_edge(CLK) then
+ reg_CTRL_TIMEOUT_TIME <= CTRL_TIMEOUT_TIME;
connection_timed_out(i) <= '0';
timeout_found <= or_all(connection_timed_out);
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or CTRL_TIMEOUT_TIME = 0 then
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then
timeout_counter(i) <= (others => '0');
- elsif timeout_counter(i)(conv_integer(('0'&CTRL_TIMEOUT_TIME)+16)) = '1' then
+ elsif timeout_counter(i)(conv_integer(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'0')) = '1' then
connection_timed_out(i) <= '1';
- else
+ elsif timer_ms_tick = '1' then
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
end if;
end if;
CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);
FEE_DATAREADY_OUT : out std_logic;
FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
STAT_GEN : out std_logic_vector (31 downto 0);
STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
CTRL_GEN : in std_logic_vector (31 downto 0);
+ CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0'); --0..15 for init, 16..31 for reply
STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0) := "00"
);
end entity;
INT_READ_OUT => INT_INIT_READ_OUT,
STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer,
CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer,
- STAT_DEBUG => STAT_INIT_OBUF_DEBUG
+ CTRL_SETTINGS => CTRL_OBUF_settings(15 downto 0),
+ STAT_DEBUG => STAT_INIT_OBUF_DEBUG,
+ TIMER_TICKS_IN => TIMER_TICKS_IN
);
end generate;
genINITOBUF2 : if INIT_CAN_SEND_DATA = 0 generate
INT_READ_OUT => INT_REPLY_READ_OUT,
STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer,
CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer,
- STAT_DEBUG => STAT_REPLY_OBUF_DEBUG
+ CTRL_SETTINGS => CTRL_OBUF_settings(31 downto 16),
+ STAT_DEBUG => STAT_REPLY_OBUF_DEBUG,
+ TIMER_TICKS_IN => TIMER_TICKS_IN
);
end generate;
genREPLYOBUF2 : if REPLY_CAN_SEND_DATA = 0 generate
MED_READ_IN => MED_REPLY_READ_IN,
STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer,
CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer,
+ --CTRL_SETTINGS => CTRL_OBUF_settings(31 downto 16),
STAT_DEBUG => STAT_REPLY_OBUF_DEBUG
);
INT_REPLY_READ_OUT <= '0';
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetOBUF
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net16_obuf is
-- Status and control port
STAT_BUFFER : out std_logic_vector (31 downto 0);
CTRL_BUFFER : in std_logic_vector (31 downto 0);
- STAT_DEBUG : out std_logic_vector (31 downto 0)
+ CTRL_SETTINGS : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (31 downto 0);
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0)
);
end entity;
attribute syn_hier : string;
attribute syn_hier of trb_net16_obuf_arch : architecture is "flatten, firm";
- component trb_net16_sbuf is
- generic (
- VERSION : integer := 0
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in std_logic; --comb logic provides data word
- COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle
- COMB_READ_IN: in std_logic; --comb logic IS reading
- COMB_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- COMB_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out std_logic;
- SYN_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- SYN_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- SYN_READ_IN: in std_logic;
- -- Status and control port
- STAT_BUFFER: out std_logic
- );
- end component;
-
- component trb_net_CRC is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- CRC_OUT : out std_logic_vector(15 downto 0);
- CRC_match : out std_logic
- );
- end component;
signal current_output_data_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
signal current_output_num_buffer : STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
signal int_packet_num_in_i: std_logic_vector(2 downto 0);
signal last_buf_INT_READ_OUT : std_logic;
+ signal wait_for_ack_timeout : std_logic;
+ signal wait_for_ack_counter : unsigned(8 downto 0);
+ signal wait_for_ack_max_bit : std_logic_vector(2 downto 0);
+ signal timer_tick : std_logic;
begin
end process reg_TRANSMITTED_BUFFERS;
end generate;
+
+ proc_reg_setting : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ wait_for_ack_max_bit <= CTRL_SETTINGS(2 downto 0);
+ timer_tick <= TIMER_TICKS_IN(1);
+ end if;
+ end process;
+
+ proc_ack_timeout_counters : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ wait_for_ack_timeout <= '0';
+ if TRANSMITTED_BUFFERS(1) = '0' or wait_for_ack_max_bit = x"0" then
+ wait_for_ack_counter <= (others => '0');
+ elsif wait_for_ack_counter(conv_integer(wait_for_ack_max_bit)+1) = '1' then
+ wait_for_ack_timeout <= '1';
+ elsif timer_tick = '1' then
+ wait_for_ack_counter <= wait_for_ack_counter + to_unsigned(1,1);
+ end if;
+ end if;
+ end process;
+
+
STAT_DEBUG(0) <= comb_dataready;
STAT_DEBUG(3 downto 1) <= transfer_counter;
STAT_DEBUG(4) <= buf_MED_DATAREADY_OUT;
STAT_DEBUG(14 downto 13) <= TRANSMITTED_BUFFERS;
STAT_DEBUG(17 downto 15) <= REC_BUFFER_SIZE_IN(2 downto 0);
STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0); --used in hub monitoring!
-STAT_DEBUG(20) <= '1';
+STAT_DEBUG(20) <= wait_for_ack_timeout; --used in hub monitoring
STAT_DEBUG(31 downto 21) <= (others => '0');
end architecture;
LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
TIMER_US_TICK : out std_logic; --1 tick every microsecond
+ TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds
--Common Register in / out
COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
if rising_edge(CLK) then
-- global_time(15 downto 0) <= next_global_time(15 downto 0);
-- global_time_overflow <= '0';
+ TIMER_MS_TICK <= '0';
if global_time_write = '1' then
global_time_i <= saved_Reg_high & saved_Reg_low;
elsif us_tick_i = '1' then
global_time_i <= global_time_i + 1;
+ if global_time_i(9 downto 0) = "0000000000" then
+ TIMER_MS_TICK <= '1';
+ end if;
-- next_global_time(15 downto 0) <= global_time(15 downto 0) + 1;
-- if or_all(global_time(15 downto 0)) = '1' then
-- global_time_overflow <= '1';
-- for whole architecture
attribute HGROUP of trb_net16_term_buf_arch : architecture is "TRMBUF_group";
+ attribute syn_hier : string;
+ attribute syn_hier of trb_net16_term_buf_arch : architecture is "firm";
+
signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0);
signal saved_packet_type : std_logic_vector(3 downto 0);
signal INIT_transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal buf_MED_REPLY_DATA_OUT, next_MED_REPLY_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal send_REPLY_trm : std_logic;
signal next_send_REPLY_trm : std_logic;
+
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_sharing : string;
+ attribute syn_sharing of trb_net16_term_buf_arch : architecture is "off";
+ attribute syn_preserve of saved_packet_type : signal is true;
+ attribute syn_keep of saved_packet_type : signal is true;
+
+
begin
MED_READ_OUT <= '1';
CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);
FEE_DATAREADY_OUT : out std_logic;
FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
STAT_GEN : out std_logic_vector (31 downto 0);
STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
CTRL_GEN : in std_logic_vector (31 downto 0);
+ CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');
STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0)
);
end component;
-- Status and control port
STAT_BUFFER: out std_logic_vector (31 downto 0);
CTRL_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DEBUG : out std_logic_vector (31 downto 0)
+ CTRL_SETTINGS : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (31 downto 0);
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0)
);
end component;
LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
TIMER_US_TICK : out std_logic; --1 tick every microsecond
+ TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds
--Common Register in / out
COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
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