RESET : in std_logic;\r
GSR_N : in std_logic;\r
CLK_125_OUT : out std_logic;\r
- CLK_RX_OUT : out std_logic;\r
- CLK_TX_OUT : out std_logic;\r
- CLK_125_TX_IN : in std_logic; -- gk 28.04.10 used when intclk\r
- CLK_125_RX_IN : in std_logic; -- gk 28.04.10 used when intclk\r
+ CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk\r
--SGMII connection to frame transmitter (tsmac)\r
FT_TX_CLK_EN_OUT : out std_logic;\r
FT_RX_CLK_EN_OUT : out std_logic;\r
ffc_trst : in std_logic;\r
ff_txfullclk : out std_logic;\r
ff_txhalfclk : out std_logic;\r
- refck2core : out std_logic;\r
ffs_plol : out std_logic);\r
\r
end component;\r
\r
-- Reset state machine for SerDes\r
THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe\r
-port map( SYSCLK => refclkcore,\r
- RESET => '0', -- really?\r
- CLEAR => RESET, -- from 100MHz PLL, includes async part\r
- -- status signals\r
- SFP_MISSING_IN => SD_PRSNT_N_IN,\r
- SFP_LOS_IN => SD_LOS_IN,\r
- SD_LINK_OK_IN => '1', -- not used\r
- SD_LOS_IN => '0', -- not used\r
- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol\r
- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol\r
- -- control signals\r
- FULL_RESET_OUT => quad_rst,\r
- LANE_RESET_OUT => lane_rst,\r
- USER_RESET_OUT => user_rst,\r
- -- debug signals\r
- TIMING_CTR_OUT => open,\r
- BSM_OUT => reset_bsm,\r
- DEBUG_OUT => reset_debug\r
- );\r
+port map(\r
+ SYSCLK => refclkcore,\r
+ RESET => '0', -- really?\r
+ CLEAR => RESET, -- from 100MHz PLL, includes async part\r
+ -- status signals\r
+ SFP_MISSING_IN => SD_PRSNT_N_IN,\r
+ SFP_LOS_IN => SD_LOS_IN,\r
+ SD_LINK_OK_IN => '1', -- not used\r
+ SD_LOS_IN => '0', -- not used\r
+ SD_TXCLK_BAD_IN => sd_link_error(2), -- plol\r
+ SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol\r
+ -- control signals\r
+ FULL_RESET_OUT => quad_rst,\r
+ LANE_RESET_OUT => lane_rst,\r
+ USER_RESET_OUT => user_rst,\r
+ -- debug signals\r
+ TIMING_CTR_OUT => open,\r
+ BSM_OUT => reset_bsm,\r
+ DEBUG_OUT => reset_debug\r
+);\r
\r
-- gk 28.04.10\r
-- SerDes for GbE\r
-clk_int : if (USE_125MHZ_EXTCLK = 0) generate \r
+clk_int : if (USE_125MHZ_EXTCLK = 0) generate\r
+\r
+ refclkcore <= CLK_125_IN;\r
+\r
SERDES_GBE : serdes_gbe_0_intclock_8b\r
port map(\r
- core_txrefclk => CLK_125_TX_IN,\r
- core_rxrefclk => CLK_125_RX_IN,\r
+ core_txrefclk => CLK_125_IN,\r
+ core_rxrefclk => CLK_125_IN,\r
hdinp0 => SD_RXD_P_IN,\r
hdinn0 => SD_RXD_N_IN,\r
hdoutp0 => SD_TXD_P_OUT,\r
hdoutn0 => SD_TXD_N_OUT,\r
- ff_rxiclk_ch0 => sd_rx_clk,\r
- ff_txiclk_ch0 => sd_tx_clk,\r
- ff_ebrd_clk_0 => sd_rx_clk,\r
+ ff_rxiclk_ch0 => sd_rx_clk,\r
+ ff_txiclk_ch0 => sd_tx_clk,\r
+ ff_ebrd_clk_0 => sd_rx_clk,\r
ff_txdata_ch0 => sd_tx_data,\r
ff_rxdata_ch0 => sd_rx_data,\r
ff_tx_k_cntrl_ch0 => sd_tx_kcntl,\r
ff_rx_k_cntrl_ch0 => sd_rx_kcntl,\r
- ff_rxfullclk_ch0 => sd_rx_clk,\r
+ ff_rxfullclk_ch0 => sd_rx_clk,\r
ff_xmit_ch0 => '0',\r
ff_correct_disp_ch0 => sd_tx_correct_disp,\r
ff_disp_err_ch0 => sd_rx_disp_error,\r
ffc_macro_rst => '0',\r
ffc_quad_rst => quad_rst,\r
ffc_trst => '0',\r
- ff_txfullclk => sd_tx_clk,\r
- ff_txhalfclk => open,\r
- refck2core => refclkcore,\r
+ ff_txfullclk => sd_tx_clk,\r
+ ff_txhalfclk => open,\r
ffs_plol => sd_link_error(2)\r
);\r
end generate clk_int;\r
\r
\r
SGMII_GBE_PCS : sgmii_gbe_pcs32\r
-port map( rst_n => GSR_N, \r
- signal_detect => sd_link_ok, \r
- gbe_mode => '1', \r
- sgmii_mode => MR_MODE_IN, \r
- operational_rate => "10", \r
- debug_link_timer_short => '0', \r
- rx_compensation_err => pcs_rx_comp_err, \r
- -- MAC interface\r
- tx_clk_125 => refclkcore, -- original clock from SerDes\r
- tx_clock_enable_source => pcs_tx_clk_en,\r
- tx_clock_enable_sink => pcs_tx_clk_en,\r
- tx_d => FT_TXD_IN, -- TX data from MAC\r
- tx_en => FT_TX_EN_IN, -- TX data enable from MAC\r
- tx_er => FT_TX_ER_IN, -- TX error from MAC\r
- rx_clk_125 => refclkcore, -- original clock from SerDes \r
- rx_clock_enable_source => pcs_rx_clk_en,\r
- rx_clock_enable_sink => pcs_rx_clk_en,\r
- rx_d => pcs_rx_d, -- RX data to MAC\r
- rx_dv => pcs_rx_dv, -- RX data enable to MAC\r
- rx_er => pcs_rx_er, -- RX error to MAC\r
- col => FT_COL_OUT,\r
- crs => FT_CRS_OUT,\r
- -- SerDes interface\r
- tx_data => sd_tx_data, -- TX data to SerDes\r
- tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes\r
- tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes)\r
- serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream\r
- rx_data => sd_rx_data, -- RX data from SerDes\r
- rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes\r
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal\r
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)\r
- rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes\r
- rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes\r
- -- Autonegotiation stuff\r
- mr_an_complete => pcs_mr_an_complete,\r
- mr_page_rx => pcs_mr_page_rx,\r
- mr_lp_adv_ability => pcs_mr_ability,\r
- mr_main_reset => pcs_mr_reset,\r
- mr_an_enable => MR_AN_ENABLE_IN,\r
- mr_restart_an => MR_RESTART_AN_IN,\r
- mr_adv_ability => MR_ADV_ABILITY_IN\r
- ); \r
+port map(\r
+ rst_n => GSR_N,\r
+ signal_detect => sd_link_ok,\r
+ gbe_mode => '1',\r
+ sgmii_mode => MR_MODE_IN,\r
+ operational_rate => "10",\r
+ debug_link_timer_short => '0',\r
+ rx_compensation_err => pcs_rx_comp_err,\r
+ -- MAC interface\r
+ tx_clk_125 => refclkcore, -- original clock from SerDes\r
+ tx_clock_enable_source => pcs_tx_clk_en,\r
+ tx_clock_enable_sink => pcs_tx_clk_en,\r
+ tx_d => FT_TXD_IN, -- TX data from MAC\r
+ tx_en => FT_TX_EN_IN, -- TX data enable from MAC\r
+ tx_er => FT_TX_ER_IN, -- TX error from MAC\r
+ rx_clk_125 => refclkcore, -- original clock from SerDes\r
+ rx_clock_enable_source => pcs_rx_clk_en,\r
+ rx_clock_enable_sink => pcs_rx_clk_en,\r
+ rx_d => pcs_rx_d, -- RX data to MAC\r
+ rx_dv => pcs_rx_dv, -- RX data enable to MAC\r
+ rx_er => pcs_rx_er, -- RX error to MAC\r
+ col => FT_COL_OUT,\r
+ crs => FT_CRS_OUT,\r
+ -- SerDes interface\r
+ tx_data => sd_tx_data, -- TX data to SerDes\r
+ tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes\r
+ tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes)\r
+ serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream\r
+ rx_data => sd_rx_data, -- RX data from SerDes\r
+ rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes\r
+ rx_err_decode_mode => '0', -- receive error control mode fixed to normal\r
+ rx_even => '0', -- unused (receive error control mode = normal, tie to GND)\r
+ rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes\r
+ rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes\r
+ -- Autonegotiation stuff\r
+ mr_an_complete => pcs_mr_an_complete,\r
+ mr_page_rx => pcs_mr_page_rx,\r
+ mr_lp_adv_ability => pcs_mr_ability,\r
+ mr_main_reset => pcs_mr_reset,\r
+ mr_an_enable => MR_AN_ENABLE_IN,\r
+ mr_restart_an => MR_RESTART_AN_IN,\r
+ mr_adv_ability => MR_ADV_ABILITY_IN\r
+);\r
\r
pcs_mr_reset <= MR_RESET_IN or RESET or user_rst;\r
\r
\r
-- Clock games\r
CLK_125_OUT <= refclkcore;\r
-CLK_RX_OUT <= sd_rx_clk;\r
-CLK_TX_OUT <= sd_tx_clk;\r
\r
-- Fakes\r
STAT_OP <= (others => '0');\r
jspc29 / trbnet.git / commitdiff