--x"0"debug, x"1" 2 hit in one word, x"2" test data,
DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0);
+ ERROR_DATA_INFO_IN : in std_logic_vector(11 downto 0);
DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
end tdc_readout;
signal saved_data : std_logic_vector(35 downto 0);
signal reg_token_tdc_readout_i, next_token_tdc_readout_i : std_logic_vector(3 downto 0);
signal reg_flag_event_counter_in : std_logic_vector(3 downto 0);
---signal pulse_init_tdc_readout : std_logic;
-------------------------------------------------------------------------------
-- new format signals (2 hits in one dataword)
-- process: it gets the token from entity "send_token",
-- it is back I send to TRB
------------------------------------------------------------------------------
- save_data: process (CLK)
+ save_data : process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
saved_data <= (others => '0');
elsif (next_state = save_H_word_state_next) then
+
saved_data(35 downto 32) <= reg_flag_event_counter_in;
- saved_data(31 downto 26) <= reg_flag_event_counter_in & "00";--x"0";
- saved_data(25 downto 23) <= '0' & "00";--mb_number;
- saved_data(22 downto 19) <= x"0";--reg_bus_number;--x"1";
- saved_data(18 downto 12) <= A_ADD_IN(8 downto 2);
- saved_data(11) <= A_RESERV_IN; --11th bit is reserv!
- saved_data(10 downto 9) <= A_ADD_IN(1 downto 0);
- saved_data(8 downto 0) <= saved_data(8 downto 0);
+ saved_data(31) <= '0'; --DATA MODE
+ saved_data(30 downto 29) <= "00"; --DATA TYPE
+ saved_data(28 downto 22) <= A_ADD_IN(8 downto 2); --TDC NR and TDC CH
+ saved_data(21) <= A_RESERV_IN; --11th bit is reserv! HIT NR
+
+--DEBUG INFO TO PUT IN THE DATA, used to generate wrror pattern
+ saved_data(20 downto 11) <= "00" & x"00";
+
+ saved_data(10 downto 9) <= A_ADD_IN(1 downto 0); --TDC DATA
+ saved_data(8 downto 0) <= saved_data(8 downto 0);--TDC DATA
elsif (next_state = save_L_word_state_next) then
- saved_data(18 downto 9) <= saved_data(18 downto 9);
- saved_data(8 downto 0) <= A_ADD_IN(8 downto 0);
+ saved_data(18 downto 9) <= saved_data(18 downto 9);
+ saved_data(8 downto 0) <= A_ADD_IN(8 downto 0);
end if;
end if;
end process save_data;
signal debug_register_tdc_readout_i : std_logic_vector(3 downto 0);
signal reg_trigger_type : std_logic_vector(3 downto 0);
signal token_tdc_readout_i : std_logic_vector(3 downto 0);
- signal reg_first_header : std_logic_vector(51 downto 0);
+ signal reg_first_header : std_logic_vector(71 downto 0);
signal data_tdc_readout_i : std_logic_vector(35 downto 0);
signal write_fee_data_fifo_i : std_logic;
signal flag_event_counter : std_logic_vector(3 downto 0);
signal pulse_init_tdc_readout : std_logic;
-
+ signal counter_timing_trigger : std_logic_vector (15 downto 0);
+
signal next_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
signal fee_data_fifo_out_i : std_logic_vector(35 downto 0);
- signal header_data_fifo_out_i : std_logic_vector(51 downto 0);
- signal data_header_fifo_in_i : std_logic_vector(51 downto 0);
+ signal header_data_fifo_out_i : std_logic_vector(71 downto 0);
+ signal data_header_fifo_in_i : std_logic_vector(71 downto 0);
signal reg_debug_register_fsm_header, next_debug_register_fsm_header : std_logic_vector(7 downto 0);
signal write_header_fifo_i, next_write_header_fifo_i : std_logic;
signal next_ipu_error_pattern : std_logic_vector(31 downto 0);
signal next_flag_in_header : std_logic_vector(3 downto 0);
signal init_tdc_readout_i : std_logic_vector(3 downto 0);
+ signal error_data_header_info_i : std_logic_vector(19 downto 0);
+ signal clear_counter_error_token_back : std_logic;
+ signal counter_error_token_back : std_logic_vector(12 downto 0);
+
begin -- behavioral
INIT_TDC_READOUT_IN_0_PULSE : edge_to_pulse
DATA_VALID_OUT => write_fee_data_fifo_i,
DATA_BUS_OUT => data_tdc_readout_i,
INIT_TDC_READOUT_IN => INIT_TDC_READOUT_IN, --init from common_stop_
- --generator after send
- --token
+ --generator after send
+ --token
FULL_FIFO_IN => '0',
+ ERROR_DATA_INFO_IN => (others => '0'),
DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN,
DEBUG_REGISTER_OUT => debug_register_tdc_readout_i);
RdEn => read_fee_data_fifo,
Reset => RESET,
AmEmptyThresh => "0000000000100",
- AmFullThresh => "1110000000000",
+ AmFullThresh => "1110000000000",
Q => fee_data_fifo_out_i,
WCNT => word_count_fee_data_fifo,
Empty => empty_flag_fee_data_fifo_i,
AlmostEmpty => almost_empty_flag_fee_data_fifo_i,
AlmostFull => almost_full_flag_fee_data_fifo_i);
-
- HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out
+ HEADER_FIFO: fifo_512depth_72width_reg_out
port map (
- Data => reg_first_header,
- Clock => CLK,
- WrEn => write_header_fifo_i,
- RdEn => read_header_fifo,
- Reset => RESET,
- AmEmptySetThresh => '0'& x"00",
- AmEmptyClrThresh => '0' & x"00",
- Q => header_data_fifo_out_i,
- WCNT => word_count_header_fifo,
- Empty => empty_flag_header_data_fifo_i,
- Full => full_flag_header_data_fifo_i,
- AlmostEmpty => almost_empty_flag_header_data_fifo_i,
- AlmostFull => almost_full_flag_header_data_fifo_i);
-
-
-
+ Data => reg_first_header,
+ Clock => CLK,
+ WrEn => write_header_fifo_i,
+ RdEn => read_header_fifo,
+ Reset => RESET,
+ AmEmptyThresh => '0'& x"00",
+ AmFullThresh => '0'& x"00",
+ Q => header_data_fifo_out_i,
+ WCNT => word_count_header_fifo,
+ Empty => empty_flag_header_data_fifo_i,
+ Full => full_flag_header_data_fifo_i,
+ AlmostEmpty => almost_empty_flag_header_data_fifo_i,
+ AlmostFull => almost_full_flag_header_data_fifo_i);
+
+-- HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out
+-- port map (
+-- Data => reg_first_header,
+-- Clock => CLK,
+-- WrEn => write_header_fifo_i,
+-- RdEn => read_header_fifo,
+-- Reset => RESET,
+-- AmEmptySetThresh => '0'& x"00",
+-- AmEmptyClrThresh => '0' & x"00",
+-- Q => header_data_fifo_out_i,
+-- WCNT => word_count_header_fifo,
+-- Empty => empty_flag_header_data_fifo_i,
+-- Full => full_flag_header_data_fifo_i,
+-- AlmostEmpty => almost_empty_flag_header_data_fifo_i,
+-- AlmostFull => almost_full_flag_header_data_fifo_i);
+
+
-- Count number of dataword per event written to fifo
a_add_data_counter : process (CLK)
begin
IPU_DATAREADY_OUT <= next_ipu_dataready;
IPU_READOUT_FINISHED_OUT <= reg_ipu_finished;
IPU_LENGTH_OUT <= header_data_fifo_out_i(51 downto 36);
- IPU_ERROR_PATTERN_OUT <= reg_ipu_error_pattern;
+ IPU_ERROR_PATTERN_OUT <= reg_ipu_error_pattern ;
process (CLK)
begin
if rising_edge(CLK) then
- reg_first_header <= words_in_event & --(15 downto 0)
- flag_event_counter & --(3 downto 0)
- "0000" & --(3 downto 0)
- reg_lvl1_trg_type & --(3 downto 0)
- reg_lvl1_trg_code & --(7 downto 0)
- reg_lvl1_trg_number; --(15 downto 0);
+ reg_first_header <= error_data_header_info_i &-- (71 downto 52)
+ words_in_event & --(15 downto 0)
+ flag_event_counter & --(3 downto 0)
+ "0000" & --(3 downto 0)
+ reg_lvl1_trg_type & --(3 downto 0)
+ reg_lvl1_trg_code & --(7 downto 0)
+ reg_lvl1_trg_number; --(15 downto 0);
end if;
end process;
next_debug_register_fsm_header <= (others => '0');
next_lvl1_busy_i <= '0';
data_header_fifo_in_i <= reg_first_header;
+ clear_counter_error_token_back <= '0';
next_state <= current_state;
case current_state is
+-------------------------------------------------------------------------------
+-- with INIT_TDC_READOUT_IN(0) = '1' the timing trigger has been sended, the
+-- TDCs deliver data and the HEADER is build and written into the fifo after TOKEN
+-- and LVL1 info has been read.
+-------------------------------------------------------------------------------
when idle_state =>
next_debug_register_fsm_header <= x"00";
next_write_header_fifo_i <= '0';
-----------------------------------------------------------------------
--WAIT FOR TOKEN:
--I have to wait the event which is being collected is complete.
---When the event is complete the second header is generated and loaded
+--When the event is complete the header is generated and loaded
--in the fifo.
---When I wait in this state the data is written in the data_fifo.
+--When I wait in this state the TDC data is written in the data_fifo.
-----------------------------------------------------------------------
when wait_for_token =>
next_debug_register_fsm_header <= x"02";
next_write_header_fifo_i <= '0';
data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '1';
- if (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '0') then
+ --are we sure firt we get the timing trigger and then lvl1 info???
+ if (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '0' and reg_lvl1_trg_received = '1') then
next_state <= send_second_header_state;
elsif (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '1') then
next_state <= busy_header_state;
next_write_header_fifo_i <= '0';
data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '1';
+ clear_counter_error_token_back <= '1';
if (almost_full_flag_fee_data_fifo_i = '0') then
-- clear_counter_pulse_not_empty <= '1';
next_state <= send_second_header_state;
next_ipu_finished <= '0';
next_flag_in_header<= reg_flag_in_header;
next_ipu_data <= header_data_fifo_out_i(31 downto 0);
- next_ipu_error_pattern <= reg_ipu_error_pattern;
+ --next_ipu_error_pattern <= reg_ipu_error_pattern;
case current_state_fsm_multiplexer is
when idle_state_fsm_multiplexer =>
- next_ipu_error_pattern <= (others => '0');
+ -- next_ipu_error_pattern <= (others => '0');
next_debug_register_fsm_multiplexer <= x"00";
- if reg_ipu_start_readout_in = '1' and empty_flag_header_data_fifo_i = '0' then
+ if (reg_ipu_start_readout_in = '1' and empty_flag_header_data_fifo_i = '0') then
read_header_fifo <= '1';
next_state_fsm_multiplexer <= wait_for_header_fifo_ready;
end if;
-- end if;
-- end process;
+-------------------------------------------------------------------------------
+-- check if the timing trigger received and the LVL1 trigger are the same
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ counter_timing_trigger <= (others => '0');
+ elsif (pulse_init_tdc_readout = '1') then
+ counter_timing_trigger <= counter_timing_trigger + 1;
+ else
+ counter_timing_trigger <= counter_timing_trigger;
+ end if;
+ end if;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- write debug info in the data header event
+-------------------------------------------------------------------------------
+ error_data_header_info_i(0) <= '1' when (counter_error_token_back(0) = '1') else '0';--TOKEN NOT BACK
+
+ error_data_header_info_i(1) <= '1'; --test
+
+-------------------------------------------------------------------------------
+-- decoder debug info in the data header event for error pattern
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1' or next_ipu_finished = '1') then
+ next_ipu_error_pattern <= (others => '0');
+ elsif (last_read_header_fifo = '1') then
+ next_ipu_error_pattern(25) <= header_data_fifo_out_i(52); --TOKEN NOT BACK
+ next_ipu_error_pattern(26) <= header_data_fifo_out_i(53); --TEST
+ else
+ next_ipu_error_pattern <= next_ipu_error_pattern;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- counter token not back
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1' or clear_counter_error_token_back = '1') then
+ counter_error_token_back <= (others => '0');
+ elsif (TOKEN_IN = x"2") then
+ counter_error_token_back <= counter_error_token_back + 1;
+ else
+ counter_error_token_back <= counter_error_token_back;
+ end if;
+ end if;
+ end process;
+
-------------------------------------------------------------------------------
-- PROCESS to count how many word the TRB net reads from the FIFO_HADER
-------------------------------------------------------------------------------
jspc29 / mdcoep.git / commitdiff