replaced parts of gbe_frame_constr

diff --git a/gbe_hub/config_compile_gsi.pl b/gbe_hub/config_compile_gsi.pl
index 9ff231cff280f8b4e8bf4064f09a27a19ed53821..c63e8ec16c4cc2bf3a74165b27b889d9d416dd60 100644 (file)
--- a/gbe_hub/config_compile_gsi.pl
+++ b/gbe_hub/config_compile_gsi.pl
@@ -8,7 +8,8 @@ synplify_command             => "/opt/synplicity/R-2020.09-SP1/bin/synplify_prem
 nodelist_file                => 'nodelist.txt',
 #pinout_file                  => '',
 par_options                  => '../par.p2t',
-mapper_options               => '-u -retime -split_node',
+#mapper_options               => '-u -retime -split_node',
+mapper_options               => '-retime -split_node',
     
 include_TDC                  => 0,
 include_GBE                  => 1,

diff --git a/gbe_hub/par.p2t b/gbe_hub/par.p2t
index 8b65fde61bab606e7c5a5e5dc7a832b871ab9921..7825494c1b962419fa0fd813c1e0e0b4198435c3 100644 (file)
--- a/gbe_hub/par.p2t
+++ b/gbe_hub/par.p2t
@@ -1,7 +1,7 @@
 -w
 -l 5
 -s 12
--t 34 # seed setting here! # 32
+-t 1 # seed setting here! # 34 32
 -c 1
 -e 2
 -i 15

diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj
index c2b3a24a96a4752e678f853ec92f912b730b2926..1984e79847e75afe10d0bff6bbab722faae6c9c4 100644 (file)
--- a/gbe_hub/trb3sc_gbe_hub.prj
+++ b/gbe_hub/trb3sc_gbe_hub.prj
@@ -186,6 +186,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_interface_single.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_single.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"

diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd
index 29fd6d993a5230983fc9ddf7eb6d43dea96622b5..2fd2d82b1fd55fb52028056975e1123da39dfa6d 100644 (file)
--- a/gbe_hub/trb3sc_gbe_hub.vhd
+++ b/gbe_hub/trb3sc_gbe_hub.vhd
@@ -158,12 +158,12 @@ architecture trb3sc_arch of trb3sc_gbe_hub is
   -- 9 : fifo_wr
   -- 8 : fifo_eof
   -- 7..0: fifo_data
-  type dl_rx_data_t is array(1 to 3) of std_logic_vector(10 downto 0);
+  type dl_rx_data_t is array(0 to 3) of std_logic_vector(10 downto 0);
   signal dl_rx_data : dl_rx_data_t;
-  signal dl_rx_frame_req            : std_logic_vector(3 downto 1);
-  signal dl_rx_frame_ack            : std_logic_vector(3 downto 1);
-  signal dl_rx_frame_avail          : std_logic_vector(3 downto 1);
-  signal dl_tx_fifofull             : std_logic_vector(3 downto 1);
+  signal dl_rx_frame_req            : std_logic_vector(3 downto 0);
+  signal dl_rx_frame_ack            : std_logic_vector(3 downto 0);
+  signal dl_rx_frame_avail          : std_logic_vector(3 downto 0);
+  signal dl_tx_fifofull             : std_logic_vector(3 downto 0);
   
   -- 10: frame_start
   -- 9 : fifo_wr
@@ -171,14 +171,17 @@ architecture trb3sc_arch of trb3sc_gbe_hub is
   -- 7..0: data
   signal ul_rx_data                 : std_logic_vector(10 downto 0);
   signal ul_tx_data                 : std_logic_vector(10 downto 0);
+  signal ul_tx_data_q               : std_logic_vector(10 downto 0);
   signal ul_tx_fifofull             : std_logic;
   signal ul_rx_frame_avail          : std_logic;
   signal ul_rx_frame_req            : std_logic;
   signal ul_rx_frame_ack            : std_logic;
   signal ul_rx_fifofull             : std_logic;
   
-  signal port_sel                   : std_logic_vector(3 downto 1);
+  signal port_sel                   : std_logic_vector(3 downto 0);
   
+  signal pcs_an_ready               : std_logic;
+  signal link_active                : std_logic;
   
 begin
 
@@ -245,9 +248,9 @@ begin
     FRAME_ACK_OUT(0)            => ul_rx_frame_ack,
     FRAME_AVAIL_OUT(0)          => ul_rx_frame_avail,
     -- FIFO interface TX           
-    FIFO_WR_IN(0)               => ul_tx_data(9),
-    FIFO_DATA_IN(8 downto 0)    => ul_tx_data(8 downto 0),
-    FRAME_START_IN(0)           => ul_tx_data(10),
+    FIFO_WR_IN(0)               => ul_tx_data_q(9),
+    FIFO_DATA_IN(8 downto 0)    => ul_tx_data_q(8 downto 0),
+    FRAME_START_IN(0)           => ul_tx_data_q(10),
     FIFO_FULL_OUT(0)            => ul_tx_fifofull,
     -- SerDes 1 - DOWNLINK         
     -- FIFO interface RX           
@@ -308,7 +311,9 @@ begin
     TX_PLOL_LOL_OUT             => tx_pll_lol_c_i,
     TX_PCS_RST_IN               => tx_pcs_rst_i,
     RX_LINK_READY_OUT           => open,
-    TX_LINK_READY_IN            => open,
+    TX_LINK_READY_IN            => link_tx_ready_i,
+    PCS_AN_READY_OUT(0)         => pcs_an_ready, --open, -- for internal SCTRL
+    LINK_ACTIVE_OUT(0)          => link_active, --open, -- for internal SCTRL
     -- Debug                   
     STATUS_OUT                  => status_raw(3 * 32 - 1 downto 2 * 32),
     DEBUG_OUT                   => open
@@ -320,7 +325,7 @@ begin
     CLK                       => clk_sys,
     RESET                     => reset_i,
     --
-    FIFO_FULL_IN(3 downto 1)  => dl_tx_fifofull(3 downto 1),
+    FIFO_FULL_IN(3 downto 0)  => dl_tx_fifofull(3 downto 0),
     FIFO_FULL_OUT             => ul_rx_fifofull,
     FRAME_AVAIL_IN            => ul_rx_frame_avail,
     FRAME_REQ_OUT             => ul_rx_frame_req,
@@ -335,10 +340,10 @@ begin
     CLK                          => clk_sys,
     RESET                        => reset_i,
     --
-    FRAME_AVAIL_IN(3 downto 1)   => dl_rx_frame_avail,
-    FRAME_REQ_OUT(3 downto 1)    => dl_rx_frame_req,
-    FRAME_ACK_IN(3 downto 1)     => dl_rx_frame_ack,
-    PORT_SELECT_OUT(3 downto 1)  => port_sel,
+    FRAME_AVAIL_IN(3 downto 0)   => dl_rx_frame_avail,
+    FRAME_REQ_OUT(3 downto 0)    => dl_rx_frame_req,
+    FRAME_ACK_IN(3 downto 0)     => dl_rx_frame_ack,
+    PORT_SELECT_OUT(3 downto 0)  => port_sel,
     CYCLE_DONE_OUT               => open,
     --
     DEBUG                        => open
@@ -347,42 +352,37 @@ begin
   THE_QUICK_MUX: process( port_sel, dl_rx_data )
   begin
     case port_sel is
-      when b"001" => ul_tx_data <= dl_rx_data(1);
-      when b"010" => ul_tx_data <= dl_rx_data(2);
-      when b"100" => ul_tx_data <= dl_rx_data(3);
-      when others => ul_tx_data <= (others => '0');
+      when b"0001" => ul_tx_data <= dl_rx_data(0);
+      when b"0010" => ul_tx_data <= dl_rx_data(1);
+      when b"0100" => ul_tx_data <= dl_rx_data(2);
+      when b"1000" => ul_tx_data <= dl_rx_data(3);
+      when others  => ul_tx_data <= (others => '0');
     end case;
   end process THE_QUICK_MUX;
   
-  DBG(0)            <= ul_rx_frame_avail;
-  DBG(3 downto 1)   <= dl_rx_frame_avail;
-  DBG(4)            <= ul_rx_frame_req;
-  DBG(7 downto 5)   <= dl_rx_frame_req;
-  DBG(8)            <= ul_rx_frame_ack;
-  DBG(11 downto 9)  <= dl_rx_frame_ack;
-  DBG(12)           <= ul_tx_fifofull;
-  DBG(15 downto 13) <= dl_tx_fifofull;
-  DBG(16)           <= ul_rx_fifofull;
-  DBG(19 downto 17) <= port_sel;
-  DBG(20)           <= '0';
-  DBG(21)           <= '0';
-  DBG(22)           <= '0';
-  DBG(23)           <= '0';
-  DBG(24)           <= '0';
-  DBG(25)           <= '0';
-  DBG(26)           <= '0';
-  DBG(27)           <= '0';
-  DBG(28)           <= '0';
-  DBG(29)           <= '0';
-  DBG(30)           <= '0';
-  DBG(31)           <= '0';
-  DBG(32)           <= '0';
+  ul_tx_data_q <= ul_tx_data when rising_edge(clk_sys);
+
+  -- 10: frame_start
+  -- 9 : fifo_wr
+  -- 8 : fifo_eof
+  -- 7..0: data
+  
+  DBG(3 downto 0)   <= dl_rx_frame_avail;
+  DBG(7 downto 4)   <= dl_rx_frame_req;
+  DBG(11 downto 8)  <= dl_rx_frame_ack;
+  DBG(19 downto 12) <= ul_rx_data(7 downto 0);
+  DBG(20)           <= ul_rx_frame_avail;
+  DBG(21)           <= ul_rx_frame_req;
+  DBG(22)           <= ul_rx_frame_ack;
+  DBG(23)           <= dl_rx_data(0)(9);
+  DBG(31 downto 24) <= dl_rx_data(0)(7 downto 0);
+  DBG(32)           <= dl_rx_data(0)(8);
   DBG(33)           <= clk_sys;
 
 ---------------------------------------------------------------------------
 -- GbE wrapper without med interface
 ---------------------------------------------------------------------------    
-  GBE : entity work.gbe_wrapper_raw
+  GBE : entity work.gbe_wrapper_fifo
     generic map(
       DO_SIMULATION             => 0,
       INCLUDE_DEBUG             => 0,
@@ -411,27 +411,24 @@ begin
       GSR_N                    => reset_n_i,
       -- Trigger
       TRIGGER_IN               => '0',
-      -- MAC
-      MAC_READY_CONF_IN        => mac_ready_conf,  
-      MAC_RECONF_OUT           => mac_reconf,
-      MAC_AN_READY_IN          => mac_an_ready,
-      MAC_FIFOAVAIL_OUT        => mac_fifoavail,
-      MAC_FIFOEOF_OUT          => mac_fifoeof,
-      MAC_FIFOEMPTY_OUT        => mac_fifoempty,
-      MAC_RX_FIFOFULL_OUT      => mac_rx_fifofull,
-      MAC_TX_DATA_OUT          => mac_tx_data,
-      MAC_TX_READ_IN           => mac_tx_read,
-      MAC_TX_DISCRFRM_IN       => mac_tx_discrfrm,
-      MAC_TX_STAT_EN_IN        => mac_tx_stat_en,
-      MAC_TX_STATS_IN          => mac_tx_stats,
-      MAC_TX_DONE_IN           => mac_tx_done,
-      MAC_RX_FIFO_ERR_IN       => mac_rx_fifo_err,
-      MAC_RX_STATS_IN          => mac_rx_stats,
-      MAC_RX_DATA_IN           => mac_rx_data,
-      MAC_RX_WRITE_IN          => mac_rx_write,
-      MAC_RX_STAT_EN_IN        => mac_rx_stat_en,
-      MAC_RX_EOF_IN            => mac_rx_eof,
-      MAC_RX_ERROR_IN          => mac_rx_err,
+      -- we connect to FIFO interface directly
+      -- FIFO interface RX
+      FIFO_DATA_OUT            => dl_rx_data(0)(8 downto 0),
+      FIFO_FULL_IN             => ul_tx_fifofull,
+      FIFO_WR_OUT              => dl_rx_data(0)(9),
+      FRAME_REQ_IN             => dl_rx_frame_req(0),
+      FRAME_ACK_OUT            => dl_rx_frame_ack(0),
+      FRAME_AVAIL_OUT          => dl_rx_frame_avail(0),
+      FRAME_START_OUT          => dl_rx_data(0)(10),
+      -- FIFO interface TX
+      FIFO_FULL_OUT            => dl_tx_fifofull(0),
+      FIFO_WR_IN               => ul_rx_data(9),
+      FIFO_DATA_IN             => ul_rx_data(8 downto 0),
+      FRAME_START_IN           => ul_rx_data(10),
+      --
+      PCS_AN_READY_IN          => pcs_an_ready,
+      LINK_ACTIVE_IN           => link_active,
+      --                        
       -- unique adresses
       MC_UNIQUE_ID_IN          => timer.uid,
       MY_TRBNET_ADDRESS_IN     => timer.network_address,
@@ -633,9 +630,6 @@ begin
 
   LED_RJ_GREEN(0)    <= not status_raw(0 * 8 + 2); -- A0
   LED_RJ_RED(0)      <= not status_raw(0 * 8 + 5);
-
---  LED_RJ_GREEN(1)    <= not '0';
---  LED_RJ_RED(1)      <= not '0';
   
   
 ---------------------------------------------------------------------------
@@ -685,7 +679,7 @@ begin
     SD_TXDIS_OUT(0)       => HUB_TXDIS(5),
     SD_TXDIS_OUT(1)       => HUB_TXDIS(6),
     SD_TXDIS_OUT(2)       => HUB_TXDIS(7), --open,
-    SD_TXDIS_OUT(3)       => HUB_TXDIS(8), --open,mac_ready_conf
+    SD_TXDIS_OUT(3)       => HUB_TXDIS(8), --open,
     -- SerDes control
     TX_PLOL_LOL_OUT       => tx_pll_lol_b_i,
     TX_PCS_RST_IN         => tx_pcs_rst_i,