--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 27 11:44:02.265" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 08 27 11:44:00.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2014 08 27 11:44:00.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2014 08 27 11:44:00.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2014 08 27 11:44:00.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 08 27 11:44:00.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 08 27 11:44:00.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.1
+ModuleName=serdes_sync_upstream
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/27/2014
+Time=11:44:00
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=DISABLED
+_mode2=DISABLED
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=200
+_tx_protocol0=DISABLED
+_tx_protocol1=DISABLED
+_tx_protocol2=DISABLED
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=200
+_tx_ficlk_rate1=200
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=200
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=EXTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2
+_rx_datarange1=2.5
+_rx_datarange2=2.5
+_rx_datarange3=2
+_rx_protocol0=DISABLED
+_rx_protocol1=DISABLED
+_rx_protocol2=DISABLED
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=200
+_rxrefclk_rate1=250.0
+_rxrefclk_rate2=250.0
+_rxrefclk_rate3=200
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=DISABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=DISABLED
+_rx_ficlk_rate0=200
+_rx_ficlk_rate1=250.0
+_rx_ficlk_rate2=250.0
+_rx_ficlk_rate3=200
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=AC
+_rx_dcc2=AC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=00
+_k02=00
+_k03=01
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00000000
+_byten02=00000000
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
+Regen=module
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_upstream.pp=pp
+serdes_sync_upstream.tft=tft
+serdes_sync_upstream.txt=pcs_module
+serdes_sync_upstream.sym=sym
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_1_125_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 26 14:19:29.243" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="sfp_1_125_int.lpc" type="lpc" modified="2014 11 26 14:19:25.000"/>
+ <File name="sfp_1_125_int.pp" type="pp" modified="2014 11 26 14:19:25.000"/>
+ <File name="sfp_1_125_int.sym" type="sym" modified="2014 11 26 14:19:25.000"/>
+ <File name="sfp_1_125_int.tft" type="tft" modified="2014 11 26 14:19:25.000"/>
+ <File name="sfp_1_125_int.txt" type="pcs_module" modified="2014 11 26 14:19:25.000"/>
+ <File name="sfp_1_125_int.vhd" type="top_level_vhdl" modified="2014 11 26 14:19:25.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=sfp_1_125_int
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/26/2014
+Time=14:19:25
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=RXTX
+_mode2=DISABLED
+_mode3=DISABLED
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2.5
+_pll_txsrc=INTERNAL
+_refclk_mult=20X
+_refclk_rate=125.0
+_tx_protocol0=DISABLED
+_tx_protocol1=G8B10B
+_tx_protocol2=DISABLED
+_tx_protocol3=DISABLED
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=16
+_tx_data_width1=16
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=ENABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=ENABLED
+_tx_ficlk_rate0=125.0
+_tx_ficlk_rate1=125.0
+_tx_ficlk_rate2=250.0
+_tx_ficlk_rate3=250.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=EXTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2
+_rx_datarange1=2.5
+_rx_datarange2=2
+_rx_datarange3=2
+_rx_protocol0=DISABLED
+_rx_protocol1=G8B10B
+_rx_protocol2=DISABLED
+_rx_protocol3=DISABLED
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=100
+_rxrefclk_rate1=125.0
+_rxrefclk_rate2=100
+_rxrefclk_rate3=100
+_rx_data_width0=16
+_rx_data_width1=16
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=100
+_rx_ficlk_rate1=125.0
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=200
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=DC
+_rx_dcc2=AC
+_rx_dcc3=AC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=2
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=01
+_k02=00
+_k03=00
+_k10=01
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00011100
+_byten02=00000000
+_byten03=00000000
+_byten10=00011100
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=1
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=ENABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+sfp_1_125_int.pp=pp
+sfp_1_125_int.tft=tft
+sfp_1_125_int.txt=pcs_module
+sfp_1_125_int.sym=sym
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_1_200_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 09 15 10:47:45.036" version="8.1" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="sfp_1_200_int.lpc" type="lpc" modified="2011 09 15 10:47:41.000"/>
+ <File name="sfp_1_200_int.pp" type="pp" modified="2011 09 15 10:47:41.000"/>
+ <File name="sfp_1_200_int.tft" type="tft" modified="2011 09 15 10:47:41.000"/>
+ <File name="sfp_1_200_int.txt" type="pcs_module" modified="2011 09 15 10:47:41.000"/>
+ <File name="sfp_1_200_int.vhd" type="top_level_vhdl" modified="2011 09 15 10:47:41.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=sfp_1_200_int
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/04/2014
+Time=09:44:40
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=RXTX
+_mode2=DISABLED
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=200
+_tx_protocol0=DISABLED
+_tx_protocol1=G8B10B
+_tx_protocol2=DISABLED
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=16
+_tx_data_width1=16
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=ENABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=100
+_tx_ficlk_rate1=100
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=200
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2
+_rx_datarange1=2
+_rx_datarange2=2
+_rx_datarange3=2
+_rx_protocol0=DISABLED
+_rx_protocol1=G8B10B
+_rx_protocol2=DISABLED
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=200
+_rxrefclk_rate1=200
+_rxrefclk_rate2=200
+_rxrefclk_rate3=200
+_rx_data_width0=16
+_rx_data_width1=16
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=DISABLED
+_rx_ficlk_rate0=100
+_rx_ficlk_rate1=100
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=200
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=DC
+_rx_dcc2=AC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=2
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=01
+_k02=00
+_k03=00
+_k10=01
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00011100
+_byten02=00000000
+_byten03=00000000
+_byten10=00011100
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=1
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=ENABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
+Regen=module
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+sfp_1_200_int.pp=pp
+sfp_1_200_int.tft=tft
+sfp_1_200_int.txt=pcs_module
+sfp_1_200_int.sym=sym
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_2_200_int" module="sfp_2_200_int" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 10 11:11:13.056" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="sfp_2_200_int.lpc" type="lpc" modified="2014 12 10 11:10:10.000"/>
+ <File name="sfp_2_200_int.pp" type="pp" modified="2014 12 10 11:10:10.000"/>
+ <File name="sfp_2_200_int.sym" type="sym" modified="2014 12 10 11:10:10.000"/>
+ <File name="sfp_2_200_int.tft" type="tft" modified="2014 12 10 11:10:10.000"/>
+ <File name="sfp_2_200_int.txt" type="pcs_module" modified="2014 12 10 11:10:10.000"/>
+ <File name="sfp_2_200_int.vhd" type="top_level_vhdl" modified="2014 12 10 11:10:10.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=sfp_2_200_int
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/10/2014
+Time=11:10:10
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=RXTX
+_mode2=DISABLED
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=200
+_tx_protocol0=DISABLED
+_tx_protocol1=G8B10B
+_tx_protocol2=DISABLED
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=16
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=ENABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=200
+_tx_ficlk_rate1=100
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=200
+_pll_rxsrc0=EXTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2.5
+_rx_datarange1=2
+_rx_datarange2=2.5
+_rx_datarange3=2
+_rx_protocol0=DISABLED
+_rx_protocol1=G8B10B
+_rx_protocol2=DISABLED
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=250.0
+_rxrefclk_rate1=200
+_rxrefclk_rate2=250.0
+_rxrefclk_rate3=200
+_rx_data_width0=8
+_rx_data_width1=16
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=DISABLED
+_rx_ficlk_rate0=250.0
+_rx_ficlk_rate1=100
+_rx_ficlk_rate2=250.0
+_rx_ficlk_rate3=200
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=AC
+_rx_dcc1=DC
+_rx_dcc2=AC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=00
+_k01=01
+_k02=00
+_k03=00
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00000000
+_byten01=00011100
+_byten02=00000000
+_byten03=00000000
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
+Regen=module
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+sfp_2_200_int.pp=pp
+sfp_2_200_int.tft=tft
+sfp_2_200_int.txt=pcs_module
+sfp_2_200_int.sym=sym
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="ctsc" device="LFE3-150EA-8FN672C" default_implementation="ctsc">
+ <Options/>
+ <Implementation title="ctsc" dir="ctsc" description="ctsc" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="Cu_trb3_periph_soda_client" top="Cu_trb3_periph_soda_client"/>
+ <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_client.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/ip/sfp_2_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/ip/sfp_2_200_int.lpc" type="LPC_Module" type_short="LPC">
+ <Options/>
+ </Source>
+ <Source name="code/ip/sfp_2_200_int.ipx" type="IPX_Module" type_short="IPX">
+ <Options/>
+ </Source>
+ <Source name="code/trb_net16_soda_sync_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trb3/base/version.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/Cu_trb3_periph_soda_client.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="Cu_trb3_periph_soda_client"/>
+ </Source>
+ <Source name="ctsc.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="ctsc1.sty"/>
+</BaliProject>
--- /dev/null
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+#################################################################
+#GSR_NET NET "GSR_N";
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "TRB_MEDIA_AND_SODA_SYNC_UPLINK/PCSD_INST" SITE "PCSA" ;
+
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/sci*" 20.000000 ns ;
+#MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+BLOCK JTAGPATHS ;
+## IOBUF ALLPORTS ;
+USE PRIMARY NET "clk_200_osc" ;
+USE PRIMARY NET "clk_100_osc" ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+
+FREQUENCY NET "rx_full_clk" 200.000000 MHz ;
+FREQUENCY NET "rx_half_clk" 100.000000 MHz ;
+#FREQUENCY NET "tx_full_clk" 200.000000 MHz ;
+#FREQUENCY NET "tx_half_clk" 100.000000 MHz ;
\ No newline at end of file
jspc29 / soda.git / commitdiff