signal status_ipu_handler_i : std_logic_vector(31 downto 0);
signal debug_data_handler_i : std_logic_vector(31 downto 0);
signal reset_ipu_i : std_logic;
+ signal buf_STAT_DATA_BUFFER_LEVEL : std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
begin
CLOCK => CLOCK,
RESET => reset_ipu_i,
- --From LVL1 Handler
+-- From LVL1 Handler
LVL1_VALID_TRIGGER_IN => LVL1_VALID_TRIGGER_IN,
LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,
LVL1_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, --internal number for flags
LVL1_STATUSBITS_OUT => dat_lvl1_statusbits,
LVL1_TRG_RELEASE_OUT => dat_lvl1_release,
- --From FEE
+-- From FEE
FEE_DATA_IN => FEE_DATA_IN,
FEE_DATA_WRITE_IN => FEE_DATA_WRITE_IN,
FEE_DATA_FINISHED_IN => FEE_DATA_FINISHED_IN,
FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT,
- --To IPU Handler
+-- To IPU Handler
IPU_DATA_OUT => ipu_data,
IPU_DATA_READ_IN => ipu_data_read,
IPU_DATA_EMPTY_OUT => ipu_data_empty,
IPU_HDR_DATA_READ_IN => ipu_header_read,
IPU_HDR_DATA_EMPTY_OUT => ipu_header_empty,
TMG_TRG_ERROR_IN => TMG_TRG_ERROR_IN,
- --Status
- STAT_DATA_BUFFER_LEVEL => STAT_DATA_BUFFER_LEVEL,
+-- Status
+ STAT_DATA_BUFFER_LEVEL => buf_STAT_DATA_BUFFER_LEVEL,
STAT_HEADER_BUFFER_LEVEL => STAT_HEADER_BUFFER_LEVEL,
- --Debug
+-- Debug
DEBUG_OUT => debug_data_handler_i
);
begin
if rising_edge(CLOCK) then
gen_buffer_stat : for i in 0 to DATA_INTERFACE_NUMBER-1 loop
- if STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then
+ if buf_STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then
timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1);
end if;
end loop;
when 19 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_idle);
when 20 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_working);
when 21 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_waiting);
+ when others => STATISTICS_DATA_OUT <= (others => '0');
end case;
STATISTICS_READY_OUT <= '1';
STATISTICS_UNKNOWN_OUT <= '0';