]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Tue, 7 Dec 2010 21:11:27 +0000 (21:11 +0000)
committerhadeshyp <hadeshyp>
Tue, 7 Dec 2010 21:11:27 +0000 (21:11 +0000)
special/handler_trigger_and_data.vhd

index 58e94b950dba06c9f60a106cf7a695e9bf7d3265..9a0b4e3a24d949b75f625b0e32a6d9ff486fcb1c 100644 (file)
@@ -124,6 +124,7 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is
   signal status_ipu_handler_i    : std_logic_vector(31 downto 0);
   signal debug_data_handler_i    : std_logic_vector(31 downto 0);
   signal reset_ipu_i             : std_logic;
+  signal buf_STAT_DATA_BUFFER_LEVEL : std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
 
 
 begin
@@ -174,7 +175,7 @@ begin
       CLOCK                        => CLOCK,
       RESET                        => reset_ipu_i,
 
-      --From LVL1 Handler
+--       From LVL1 Handler
       LVL1_VALID_TRIGGER_IN        => LVL1_VALID_TRIGGER_IN,
       LVL1_TRG_DATA_VALID_IN       => LVL1_TRG_DATA_VALID_IN,
       LVL1_TRG_TYPE_IN             => LVL1_TRG_TYPE_IN,
@@ -183,12 +184,12 @@ begin
       LVL1_TRG_NUMBER_IN           => LVL1_INT_TRG_NUMBER_IN,  --internal number for flags
       LVL1_STATUSBITS_OUT          => dat_lvl1_statusbits,
       LVL1_TRG_RELEASE_OUT         => dat_lvl1_release,
-      --From FEE
+--       From FEE
       FEE_DATA_IN                  => FEE_DATA_IN,
       FEE_DATA_WRITE_IN            => FEE_DATA_WRITE_IN,
       FEE_DATA_FINISHED_IN         => FEE_DATA_FINISHED_IN,
       FEE_DATA_ALMOST_FULL_OUT     => FEE_DATA_ALMOST_FULL_OUT,
-      --To IPU Handler
+--       To IPU Handler
       IPU_DATA_OUT                 => ipu_data,
       IPU_DATA_READ_IN             => ipu_data_read,
       IPU_DATA_EMPTY_OUT           => ipu_data_empty,
@@ -198,10 +199,10 @@ begin
       IPU_HDR_DATA_READ_IN         => ipu_header_read,
       IPU_HDR_DATA_EMPTY_OUT       => ipu_header_empty,
       TMG_TRG_ERROR_IN             => TMG_TRG_ERROR_IN,
-      --Status
-      STAT_DATA_BUFFER_LEVEL       => STAT_DATA_BUFFER_LEVEL,
+--       Status
+      STAT_DATA_BUFFER_LEVEL       => buf_STAT_DATA_BUFFER_LEVEL,
       STAT_HEADER_BUFFER_LEVEL     => STAT_HEADER_BUFFER_LEVEL,
-      --Debug
+--       Debug
       DEBUG_OUT                    => debug_data_handler_i
       );
 
@@ -263,7 +264,7 @@ begin
       begin
         if rising_edge(CLOCK) then
           gen_buffer_stat : for i in 0 to DATA_INTERFACE_NUMBER-1 loop
-            if STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then
+            if buf_STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then
               timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1);
             end if;
           end loop;
@@ -315,6 +316,7 @@ begin
               when 19 => STATISTICS_DATA_OUT    <= x"00" &  std_logic_vector(timer_ipu_idle);
               when 20 => STATISTICS_DATA_OUT    <= x"00" &  std_logic_vector(timer_ipu_working);
               when 21 => STATISTICS_DATA_OUT    <= x"00" &  std_logic_vector(timer_ipu_waiting);
+              when others => STATISTICS_DATA_OUT <= (others => '0');
             end case;
             STATISTICS_READY_OUT   <= '1';
             STATISTICS_UNKNOWN_OUT <= '0';